JP2000031794A - Master and slave type flip-flop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a master/slave type flip-flop circuit of less power consumption and element number usable by single phase clock signals by providing a master side latch and a slave side latch respectively constituted of a logical gate and a latch means. SOLUTION: This circuit is composed of the master side latch 11 for inputting data signals DA, opposite phase data signals DA/ and clock signals CK and the slave side latch 12 connected to the output side of the master side latch 11. The master side latch 11 and the slave side latch 12 are respectively provided with the logical gates 20-1, 20-2 and 20-3 and 20-4 and the latch means 30-1 and 30-2 of a reset/set type. When the clock signals CK become L, the data signals DA are fetched to the latch means 30-1 inside the master side latch 11. When the clock signals CK become H, the fetched data signals DA are transmitted to the slave side latch 12 and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master-slave type FF (hereinafter, referred to as "MS-FF"), which is one of flip-flop circuits (hereinafter, referred to as "FF").

[0002]

2. Description of the Related Art Conventionally, as a technique relating to this kind of MS-FF, for example, there is a technique described in the following literature. Literature: Masamichi Omori, "Ultra High-Speed Compound Semiconductor Devices", First Edition (Showa 61-11-30), Baifukan, P. 274-276 Conventionally, there are various methods for configuring the MS-FF.
What is shown in the above-mentioned literature is also an example. In the above document, 2
Since it is used as a frequency divider, the output is returned to the input, but when feedback is stopped and viewed as a simple MS-FF,
The circuit is as shown in FIG.

FIG. 10 is a circuit diagram of a conventional MS-FF. The MS-FF includes a master-side latch 1 to which a clock signal CK, a data signal DA, and an inverted-phase data signal DA / are input, and a slave-side connected to the output side and to which an inverted-phase clock signal CK / is input. And a latch 2. The master side latch 1 includes a two-input NOR gate 1a for inputting the data signal DA and the clock signal CK,
A two-input NOR gate 1b for inputting the inverted-phase data signal DA / and the clock signal CK, and two two-input NOR gates 1c and 1d cross-connected to the output terminals of the NOR gates 1a and 1b. Have been.
The slave-side latch 2 has the same configuration as the master-side latch 1, and includes a negative-phase clock signal CK / and a NOR gate 1c.
A two-input NOR gate 2a for inputting the output signal of
A two-input NOR gate 2b for inputting the output signal of the R gate 1d and the inverted-phase clock signal CK /, and two two-input NOR gates 2c and 2d cross-connected to the output terminals of the NOR gates 2a and 2b. ,It is configured. An output terminal Q is provided on the output side of the NOR gates 2c and 2d.
And the negative-phase output terminal Q / are connected to each other.

FIG. 11 is a timing chart showing the operation of the MS-FF of FIG. The operation of the MS-FF in FIG. 10 will be described with reference to FIG. First, as an initial state, the low level (hereinafter, referred to as “L”) of the clock signal CK and the data signal DA are input from the outside, and the high level of the negative-phase clock signal CK / and the negative-phase data signal DA / (Hereinafter, referred to as “H”). At this time, the output signal of the NOR gate 1a becomes "H" and the output signal of the NOR gate 1b becomes "L". Since the output signal of the NOR gate 1a is "H", NO
The output signal of the R gate 1c becomes "L", and the NOR gate 1d becomes "H" since the input signals are all "L". Since the inverted phase clock signal CK / is "H", the NOR gate 2a
And the output signals of 2b become "L", and the output terminal Q and the negative-phase output terminal Q / are in an undefined state in which the state is not yet determined.

At time t1, when the states of the clock signal CK and the data signal DA become "H", the output signals of the NOR gates 1a and 1b become "L", but the output signals of the NOR gates 1c and 1d are held. You. On the other hand, at the same time when the clock signal CK changes,
When K / changes to "L", the state of the master side latch 1 is taken into the slave side latch 2, and the output signal of the NOR gate 2a changes to "H". Since the output signal of the NOR gate 1d is "H", the output signal of the NOR gate 2b remains "L". When the output signal of the NOR gate 2a becomes "H", the output terminal Q on the output side of the NOR gate 2c changes to "L". At the same time, the NOR gate 2d outputs "H" because the input signals are all "L", and the state of the inverted-phase output terminal Q / is determined to be "H". At time t2, when the state of the clock signal CK changes to "L", the master side latch 1 takes in the data signal DA, the output signal of the NOR gate 1a is "L", the output signal of the NOR gate 1b is "H", The output signal of the NOR gate 1c changes to "H" and the output signal of the NOR gate 1d changes to "L". However, since the inverted phase clock signal CK / is “H”, the state of the master side latch 1 is not transmitted to the slave side latch 2, and the output terminal Q and the inverted phase output terminal Q / are “L”, respectively.
It is kept at “H”.

At time t3, the clock signal CK changes to "H" and the data signal DA changes to "L". Even if the data signal DA changes, since the clock signal CK is "H" and the data signal DA is not taken into the master side latch 1, the output signals of the NOR gates 1c and 1d become "H" and "L". "As it is. The slave-side latch 2 captures the state of the master-side latch 1 because the negative-phase clock signal CK / becomes “L”, and the output terminal Q and the negative-phase output terminal Q / change to “H” and “L”, respectively. I do. As described above, when the state of the clock signal CK is "L", the MS-FF of FIG.
And the clock signal CK is changed from “L” to “H”.
The data signal DA is output at the timing when the clock signal CK changes to "H", and the state is held for one clock when the clock signal CK next changes from "L" to "H".

[0007]

However, the conventional MS-FF has the following problems. Conventional MS
In the FF, it is necessary to supply the clock signal CK and the data signal DA in both the normal phase and the negative phase. When the MS-FF is configured by an integrated circuit (hereinafter, referred to as an “IC”), always arranging a clock signal line and a data line in both phases inside the IC is a large-scale circuit in order to increase a wiring area. Is not suitable for realizing the above, which is not preferable in terms of layout. Care must be taken to match the timing of the two-phase signals. For this reason, a method of creating an inverted-phase signal by adding an inverter inside the MS-FF is often used.
In this case, the number of elements increases, the power consumption increases, and a timing shift of one stage of the inverter occurs between the two-phase signals, so that the phase margin of the MS-FF is reduced accordingly. SUMMARY OF THE INVENTION It is an object of the present invention to solve the problems of the prior art and to provide an MS-FF that can be used with a single-phase clock signal and has low power consumption and a small number of elements.

[0008]

According to a first aspect of the present invention, there is provided a load driving element connected between a first power supply potential and a load-side node. A first switching element connected between the load-side node and an output terminal and turned on and off by a signal input from a first input terminal; a second power supply potential lower than the first power supply potential; A second switching element connected between the output terminal and an on / off operation in response to a signal input from a second input terminal; and a charge discharging impedance element connected in parallel to the second switching element. And a gate connected between the first and second input terminals, and a signal input from the first and second input terminals is latched by the two gates. And complementary And a basic latch means for outputting from the first and second output terminals, the master latch and the slave latch provided with the master latch and the slave latch as follows. Make up.

The master side latch is constituted by the basic logic gate, a first input terminal receives a data signal, and a second input terminal receives a clock signal.
A second logic gate, comprising: a logic gate of the formula (1); and the basic logic gate, wherein the first input terminal receives an inverted-phase data signal, and the second input terminal receives the clock signal. The first and second latch means.
And first latch means respectively connected to the output terminals of the first and second logic gates. Further, the slave-side latch is constituted by the basic logic gate, the clock signal is input to the first input terminal, and the second input terminal is connected to a first output terminal of the first latch means. A clock signal is input to the first input terminal, and the second input terminal is connected to the first logic terminal.
A fourth logic gate connected to a second output terminal of the latch means, and the basic latch means, wherein the first and second input terminals are output terminals of the third and fourth logic gates. And second latch means respectively connected to the second and third latches. By adopting such a configuration, a data signal is fetched while the clock signal is, for example, "L", and the fetched data signal is sent out, for example, at the rising edge of the clock signal.

In the invention according to claim 2, MS-FF is
The master side latch and the slave side latch of claim 1 are interchanged. By adopting such a configuration, the state of the data signal is read when the clock signal is, for example, "H", and the read data signal is transmitted at, for example, the falling edge of the clock signal. According to a third aspect of the present invention, a signal inputted from the first input terminal and the signal inputted from the second input terminal are fetched in response to the signal inputted from the second input terminal. An MS-FF including a master side latch and a slave side latch configured by a basic gate output from an output terminal, wherein the master side latch and the slave side latch are configured as follows. The master-side latch includes the basic gate, a first gate to which a data signal is input to the first input terminal, and a clock signal to the second input terminal, and the basic gate. The first input terminal receives the clock signal, and the second input terminal receives a reverse-phase data signal. The second gate includes the basic latch means. 2 input terminal is the first input terminal.
And a first gate connected to an output terminal of the second gate, respectively.
Latch means. Further, the slave-side latch is constituted by the basic logic gate, the clock signal is input to the first input terminal, and the second input terminal is connected to a first output terminal of the first latch means. A third logic gate connected thereto and the basic logic gate, wherein the clock signal is input to the first input terminal;
The second input terminal is composed of a fourth logic gate connected to a second output terminal of the first latch means, and the basic latch means, and the first and second input terminals are connected to the second input terminal. 3
And second latch means respectively connected to the output terminals of the fourth logic gate. By adopting such a configuration, similarly to the first aspect of the present invention, a data signal is fetched while the clock signal is at "L", for example, and the fetched data signal is sent out at the rising edge of the clock signal, for example. .

In the invention according to claim 4, the MS-FF is:
The master side latch and the slave side latch of the third aspect are interchanged. With this configuration,
Similarly to the invention according to claim 2, when the clock signal is, for example, "H", the state of the data signal is read, and the read data signal is transmitted at, for example, the falling edge of the clock signal. In the invention according to claim 5, the signal inputted from the first input terminal and the signal inputted from the second input terminal are taken in in response to the signal inputted from the second input terminal. An MS-FF including a master side latch and a slave side latch configured by a basic gate output from an output terminal, wherein the master side latch and the slave side latch are configured as follows. The master side latch includes the basic gate, a first gate to which a clock signal is input to the first input terminal, and a data signal to the second input terminal, and a basic logic gate. A second logic gate, wherein the data signal is input to the first input terminal, and the clock signal is input to the second input terminal, and the basic latch means;
The first and second input terminals are connected to the first gate and the second
And first latch means respectively connected to the output terminals of the logic gates. Further, the slave-side latch is constituted by the basic logic gate, the clock signal is input to the first input terminal, and the second input terminal is connected to a first output terminal of the first latch means. The clock signal is input to the first input terminal, and the second logic gate is connected to the third logic gate and the basic logic gate.
Of the first latch means is connected to a second input terminal of the first latch means, and the basic latch means, the first and second input terminals of the third and third input terminals And second latch means respectively connected to the output terminals of the four logic gates. With this configuration, the data signal is fetched while the clock signal is "L", for example, and the fetched data signal is sent out at the rising edge of the clock signal, for example, as in the first aspect of the invention.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment (1) The configuration, (2) operation, and (3) effects of the first embodiment will be described. (1) Configuration FIG. 1 is a circuit diagram of an MS-FF according to the first embodiment of the present invention. The MS-FF includes a master latch 11 to which the data signal DA, the opposite-phase data signal DA /, and the clock signal CK are input, and a slave latch 12 connected to an output side of the master latch 11. ,It is configured. The master-side latch 11 includes two first and second logic gates 20-1 and 20-2 each configured by a basic logic gate (a so-called vertical product gate), and a reset set (hereinafter, referred to as a basic set) configured by basic latch means. (Referred to as "RS") type first latch means 30-1.

The first logic gate 20-1 has a first input terminal N21, a second input terminal N22 and an output terminal N23.
And a load driving element (for example, a field effect transistor, hereinafter referred to as “FET”) 21 and a first switching element (for example, FET) between these input / output terminals.
22, a second switching element (for example, FET) 2
3, and an impedance element for charge release (for example, F
ET) 24 is connected. The drain electrode of the FET 21 is connected to a first power supply potential (for example, a positive power supply potential) VDD, and the source electrode and the gate electrode are connected to the load-side node N20. FETs 22 and 23 are cascaded between the load-side node N20 and a second power supply potential (for example, ground potential) VSS lower than the first power supply potential. That is, the drain electrode of the FET 22 is connected to the load-side node N20, and the gate electrode is connected to the first input terminal N21 to which the data signal DA is input. The source electrode of the FET 22 is connected to the drain electrode of the FET 23 via the output terminal N23. F
The gate electrode of ET23 is connected to the second input terminal N22 to which the clock signal CK is input, and the source electrode is connected to the ground potential VSS.

An FET 24 is connected in parallel with the FET 23. That is, the drain electrode of the FET 24 is connected to the output terminal N23, and the source electrode and the gate electrode
It is connected to the ground potential VSS. FET 24
It is a transistor having an impedance higher than the ON state of the FETs 22 and 23 and lower than the OFF state. In the present embodiment, the FET 24 is used as a constant current source, but may be configured with another impedance element such as a resistor if the conditions are satisfied. Such a first logic gate 20-1
The circuit parameter of each element is the FET 23 on the ground side.
Is turned off and the potential of the output terminal N23 is set to "H" only when the load-side FET 22 is turned on, and is set to "L" in other states.

The second logic gate 20-2 has the same circuit configuration as the first logic gate 20-1. However, the opposite-phase data signal DA / is input to the first input terminal N21 of the second logic gate 20-2, and the clock signal CK is input to the second input terminal N22. First
And the output terminals N of the second logic gates 20-1 and 20-2
The first and second input terminals N31 and N32 of the first latch means 30-1 are connected to 23 and N23, respectively. The first latch means 30-1 has two 2-input NOs.
R gates 31 and 32 are connected to first and second input terminals N31 and N31, respectively.
It is cross-connected to N32. That is, the first input side of one of the two-input NOR gates 31 is connected to the first input terminal N.
31, the second input side is connected to the output side of the other two-input NOR gate 32, the output side of the NOR gate 31 is connected to the first input side of the other two-input NOR gate 32, and 1 output terminal N33. A second input side of the other two-input NOR gate 32 is connected to a second input terminal N32, and an output side of the NOR gate 32 is connected to a second output terminal N34. Similarly to the master side latch 11, the slave side latch 12 has the third and fourth logic gates 2 composed of basic logic gates.
0-3, 20-4, and RS constituted by basic latch means.
Mold second latch means 30-2.

The third logic gate 20-3 has the same circuit configuration as the first logic gate 20-1, except that a clock signal CK is applied to a first input terminal N21 of the third logic gate 20-3. Is input, and the second input terminal N22 is connected to the output terminal N33 of the first latch means 30-1.
The fourth logic gate 20-4 is also connected to the first logic gate 20-
1 has the same circuit configuration as that of the fourth logic gate 2
The clock signal CK is input to the first input terminal N21 of the first latch circuit 30 and the first input terminal N22 of the first latch means 30.
-1 output terminal N34. The second latch means 30-2 has the same circuit configuration as the first latch means 30-1, except that the first
Is connected to the output terminal N23 of the third logic gate 20-3, and the second input terminal N32 is connected to the output terminal N23 of the fourth logic gate 20-3.
The first output terminal N33 of the second latch means 30-2 is connected to the negative-phase output terminal Q /, and the second output terminal N
34 is connected to the output terminal Q.

(2) Operation FIG. 2 is a timing chart of the MS-FF of FIG. The operation of the MS-FF of FIG. 1 will be described with reference to FIG. First, as an initial state, the master side latch 11
, The “L” of the data signal DA, the “H” of the inverted-phase data signal DA /, and the “L” of the clock signal CK are input. At this time, the FETs 22 and 23 of the logic gate 20-1
Are both turned off. In the logic gate 20-1, F
Since the off-state impedance of the ET 22 is higher than that of the FET 24, the potential of the output terminal N23 becomes "L". On the other hand, in the second logic gate 20-2, the FET
Since the FET 22 is on and the FET 23 is off and the impedance of the FET 22 at the time of on is lower than that of the FET 24, the potential of the output terminal N23 becomes "H". In the first latch means 30-1, the output signal of the NOR gate 32 becomes "L" because one of the inputs is "H". At the same time, the NOR gate 31 outputs "H" because the inputs are all "L".

At this time, the state of the slave side latch 12 is
Since the clock signal CK is “L”, the third logic gate 2
0-3 FET 22 and the fourth logic gate 20-4 F
ET22 is off. Logic gate 20-3
, The potential of the output terminal N23 is naturally “L” when the FET 22 is off and the FET 23 is on, but the impedance of the charge discharging FET 24 is
Since the impedance is set lower than the off-state impedance of the FET 22, it becomes “L” even when the FET 23 is off. Therefore, when the clock signal CK is “L”, the logic gate 20
-3 and the potential of the output terminal N23 of 20-4 are always "L".
And the state of the master side latch 11 is not transmitted to the slave side latch 12, so that the latch means 30-2 in the slave side latch 12 maintains the current state. As a result, as an initial state, the output terminal Q and the negative-phase output terminal Q / are in an undefined state.

At time t1, the clock signal CK changes to "H", and at the same time, the data signal DA changes to "H" and the inverted-phase data signal DA / changes to "L". Logic gate 2
Since the potential of the output terminal N23 of 0-1 and 20-2 becomes "L" when the FET 23 on the ground side is on regardless of the state of the FET 22 on the load side, while the clock signal CK is "H", Data signal DA and inverted-phase data signal DA /
Of the latch means 3 in the master side latch 11 regardless of the state of
The state of 0-1 is maintained. At this time, in the slave side latch 12, both the FETs 22 and 23 of the logic gate 20-3 are turned on, the output terminal N23 is kept at "L", the FET 22 of the logic gate 20-4 is turned on, and the FET 23 is turned off. The output terminal N23 becomes "H". Therefore, the output terminal Q is determined to be “L”, and the antiphase output terminal Q / is also determined to be “H”. At time t2, the clock signal CK becomes “L”.
, The latch means 30- in the slave side latch 12
While the output signal of No. 2 is held, the data signal DA is taken into the latch means 30-1 in the master side latch 11.
At time t3, when the clock signal CK goes to “H”, the fetched data signal DA is
And transmitted as an output signal of the MS-FF. As described above, in the MS-FF of the present embodiment, the data signal DA is taken in while the clock signal CK is “L”, and sent out at the rising edge of the clock signal CK.

(3) Effect FIG. 3 shows the configuration of the MS-FF of FIG. 1 of the first embodiment and the conventional MS-FF of FIG. 10 using GaAs MESFETs, and their operations were compared by transient analysis simulation. It is a figure showing a simulation result. Of the device parameters used in this simulation,
Representative ones are shown below. Load driving FET of each inverter (load F of NOR gates 1a, 1b, 2a, 2b)
ET and FET2 of each logic gate 20-1 to 20-4
1) and the FETs 24 for charge release of each of the logic gates 20-1 to 20-4 have a gate length Lg = 0.5 μm, a threshold voltage V _th = −0.75 V, and a gate width Wg = K per 10 μm.
-Value = 2.001 mS / V, drain-source current Idss = 100 μA / μm (drain-source voltage Vds = 1.0 V, gate-source voltage Vgs = 0 V),
Switching elements (NOR gates 1a, 1b, 2a, 2
b switching FET and each of the logic gates 20-1 and 20-2
The FETs 22 and 23 of 0-4 have Lg = 0.5 μm and V _th
= 99.7 mV, Wg = K-Value per 10 μm =
3.685 mS / V. Gate width is NOR gate 1
The load driving FETs a, 1b, 2a and 2b, the FET 21 of each logic gate 20-1 to 20-4 are 3 μm, and the FET 24 of each logic gate 20-1 to 20-4 is 0.5 μm.
m, the number of FETs 22 of each of the logic gates 20-1 to 20-4 is 2
7 μm, FET23 of each logic gate 20-1 to 20-4
The switching FETs of the NOR gates 1a, 1b, 2a, 2b were 9 μm. In addition, VDD was set to 2V.

As shown in FIG. 3, FIG.
In the MS-FF, the data signal DA captured while the clock signal CK is "L" is output at the rising timing of the clock signal CK, and the conventional MS-FF of FIG.
It can be seen that the operation is the same as that of F. N-channel MOSFET (hereinafter referred to as "NMOS") or G
In a circuit such as aAsMESFET, when the MS-FF is to be operated with a single-phase clock signal CK as in the circuit of the first embodiment, usually, an inverter is added inside the FF and the reverse-phase clock signal CK is used. / Will be made.
In this case, the power consumption for one inverter increases,
When the output signal of the FF is received by another FF, the timing of the clock signal CK on the slave side is delayed by one stage of the inverter compared with the master side, so that the transmission delay until the latch on the master side of the next FF closes. Time tolerance will be reduced. In addition, it is not preferable to route the clock signal line in both phases in the IC from the viewpoint of easiness of layout and the like.

On the other hand, when an N-channel type FET is used in a Schottky gate device such as a GaAs MESFET, a NOR circuit is generally used as in the conventional circuit of FIG.
Logic is formed by the gates 1a to 2d. In such a circuit,
When the output signal of each of the NOR gates 1a,... Is "L", a substantially constant current always flows as a Schottky current of the next-stage input FET when the output signal is "H". On the other hand, in the logic gates 20-1 to 20-4 used in the first embodiment, the load driving FEs are used.
When the FET 22 on the T21 side is off, the current is cut, so that there is an advantage that the current consumption can be reduced. In the simulation, when the gate widths of the load driving FETs of the gates used in the circuit of the first embodiment and the conventional circuit are all the same, the power consumption of the circuit of the first embodiment is 42.7 mW. And the conventional one was 55.6 mW. As described above, in the first embodiment, the MS-FF of the present embodiment is considered to be effective because it can be used with the single-phase clock signal CK and the power consumption can be reduced.

Second Embodiment FIG. 4 is a circuit diagram of an MS-FF showing a second embodiment of the present invention. This MS-FF is configured by replacing the master-side latch 11 and the slave-side latch 12 of the first embodiment shown in FIG. That is, M of the second embodiment
In the S-FF, a master latch 11-1 having the same configuration as the slave latch 12 in FIG.
1 and a slave latch 12-1 having the same configuration. For example, in a circuit such as a multiplexer or a demultiplexer, the data signal DA is converted to the clock signal CK.
In some cases, the use of the laser beam shifted by half a wavelength is an effective means for providing a margin in the timing inside the IC and operating at a high speed. In the MS-FF of the second embodiment, the slave latch 12 and the master latch 11 shown in FIG.
In the first embodiment, the function of reading the state of the data signal DA when the clock signal CK is “L” and sending out the data signal DA at the rising edge of the clock signal CK is a function of the clock signal CK in the first embodiment. When the signal CK is at "H", the state of the data signal DA is read and the function is changed to a function of sending out the data signal DA at the falling edge of the clock signal CK.

In the conventional MS-FF of FIG. 10, the same operation is performed by using the clock signal CK on the master side as the inverted clock signal CK / and the inverted clock signal CK / on the slave side as the clock signal CK. be able to. However, when an inverted-phase clock signal CK / is generated by inserting an inverter into the clock signal CK, there is a difference between sending the data signal DA at the rising edge of the clock signal CK and sending the data signal DA at the falling edge. One of them is shifted from the edge of the clock signal CK by the delay of one stage of the inverter. On the other hand, the MS-FF of the second embodiment
Since there is no deviation from the edge of the clock signal CK, it can be said that the circuit is an effective circuit when it is desired to use the timing of both the rising edge and the falling edge of the clock signal CK.

The third embodiment of the third embodiment (1) Configuration, (2) explaining the operation, and (3) effects. (1) Configuration FIG. 5 is a circuit diagram of an MS-FF according to the third embodiment of the present invention. Elements common to those in FIG. 1 according to the first embodiment are denoted by the same reference numerals. Have been. This MS-FF
Is a master-side latch 11A having a configuration different from that of FIG.
The first output terminal N33 of the second latch means 30-2 in the slave latch 12 is connected to the output terminal Q, and the second output terminal N34 is connected to the second output terminal N34. It is connected to the negative phase output terminal Q /. Master-side latch 11A captures and outputs a signal input from a first input terminal in response to a signal input from a second input terminal, similarly to master-side latch 1 shown in FIG. The first consisting of the basic gate output from the terminal
And a second gate (for example, a two-input NOR gate) 4
1 and 42, and first latch means 30-1 similar to FIG. 1 connected to these output sides. First
NOR gate 41 has a data signal D at its first input terminal.
A is input, the clock signal CK is input to the second input terminal, and the output terminal is connected to the first input terminal N31 of the first latch means 30-1. The second NOR gate 42 has a first input terminal to which the clock signal CK is input, a second input terminal to which the inverted-phase data signal DA / is input, and an output terminal to the first latch means 30-1. 2 input terminal N31. The circuit parameters of the elements constituting the MS-FF are almost the same as in the first embodiment.

(2) Operation FIG. 6 is a timing chart of the MS-FF in FIG. The operation of the MS-FF of FIG. 5 will be described with reference to FIG. First, as an initial state, the master side latch 11
“A” is input to “A” of the data signal DA, “H” of the inverted-phase data signal DA /, and “L” of the clock signal CK. At this time, the potential of the output terminal of the NOR gate 41 becomes “H” and the potential of the output terminal of the NOR gate 42 becomes “L”. The output terminal N33 of the NOR gate 31 of the latch means 30-1 becomes "L" because one of the inputs is "H". Similarly, the NOR gate 32 of the latch means 30-1
Output terminal N34 outputs "H" because all inputs are "L". At this time, the state of the slave side latch 12 is such that the FET 22 of the logic gates 20-3 and 20-4 is in the off state because the clock signal CK is "L", and the logic gates 20-3 and 20-4 The potential of the output terminal N23 becomes "L" and the state of the master side latch 11A is not transmitted to the slave side, so that the latch means 30-2 in the slave side latch 12 maintains the current state. In the initial state, the output terminal Q and the negative-phase output terminal Q / are in an undefined state.

At time t1, the clock signal CK changes to "H", and at the same time, the data signal DA changes to "H" and the inverted-phase data signal DA / changes to "L". Since the clock signal CK is "H", the output terminals of the NOR gates 41 and 42 both become "L", and the master side latch means 30 does not depend on the state of the data signal DA and the reverse phase data signal DA /.
The state of -1 is maintained. At this time, on the slave side, the FET 22 of the logic gate 20-3 is turned on, the FET 23 is turned off, and the output terminal N23 changes to "H". Also,
Since both the FETs 22 and 23 of the logic gate 20-4 are on, the output terminal N23 remains "L". As a result, the output terminal Q is set to “L”, and the antiphase output terminal Q / is also set to “H”. At time t2, the clock signal CK
Becomes "L", the data signal DA is taken into the master latch 11A while the output of the slave latch 12 is held. At time t3, when the clock signal CK becomes “H”, the fetched data signal is transmitted to the slave side latch 12 and sent out as the output of the MS-FF. Thus, in the MS-FF of the third embodiment,
While the clock signal CK is "L", the data signal DA is taken in and sent out at the rising edge of the clock signal CK.

(3) Effect The third embodiment is effective in that it operates with a single-phase clock signal CK without adding an inverter as compared with the conventional MS-FF. Moreover, the slave side latch 1
2 as in the first embodiment, the logic gates 20-3 and 20-3
Since 0-4 are used, the power consumption is expected to be smaller than that of the conventional one, though not as much as in the first embodiment. Further, the logic gates 20-1 and 20-2 in FIG.
0-2 is composed of four elements, whereas NOR gate 4
The master latches 1 and 42 can be composed of three elements.
By configuring 1A only with the NOR gates 41, 42, 31, 32, the number of elements can be reduced as compared with the MS-FF of the first embodiment.

The fourth embodiment of the fourth embodiment (1) Configuration, (2) explaining the operation, and (3) effects. (1) Configuration FIG. 7 is a circuit diagram of an MS-FF according to a fourth embodiment of the present invention, which is common to the elements in FIGS. 1 and 5 illustrating the first and third embodiments. Are denoted by common symbols. This MS-FF includes a master-side latch 11B having a configuration different from those of FIGS. 1 and 5, and a slave-side latch 12 having the same configuration as that of FIG. 5, and receives only a single-phase clock signal CK and a data signal DA, respectively. To be entered. The master side latch 11B is the master side latch 1 of FIG.
1, the first logic gate 20-1 is connected to the NOR gate of FIG.
The circuit configuration has been replaced with a gate 41. NOR
The gate 41 and the second logic gate 20-2 receive the clock signal CK and the data signal DA. The circuit parameters of each element constituting the MS-FF are the same as in the first embodiment.

(2) Operation FIG. 8 is a timing chart of the MS-FF in FIG. The operation of the MS-FF of FIG. 7 will be described with reference to FIG. First, as an initial state, the master side latch 11
“L” of the data signal DA and “L” of the clock signal CK are input to B. At this time, since both inputs of the NOR gate 41 are "L", the potential of the output terminal becomes "H". Since both the FETs 22 and 23 of the logic gate 20-2 are turned off, the potential of the output terminal N23 becomes "L".
Output terminal N3 of NOR gate 31 of latch circuit 30-1
3 becomes “L” because one of the inputs is “H”. At the same time, the NOR gate 32 of the latch circuit 30-1 outputs "H" from the output terminal N34 because all inputs are "L". At this time, the state of the slave-side latch 12 is such that the FETs 22 of the logic gates 20-3 and 20-4 are both in the OFF state, so that the output terminals N of the logic gates 20-3 and 20-4 are
23 are both "L", and the latch means 30-2 maintains the current state. In the initial state, the output terminal Q and the negative-phase output terminal Q / are in an undefined state.

At time t1, the clock signal CK changes to "H", and at the same time, the data signal DA changes to "H". While the clock signal CK is “H”, the NOR gate 41
And the potential of the output terminal N23 of the logic gate 20-2 are both "L", and the state of the master-side latch means 30-1 is maintained. At this time, on the slave side, the FET 22 of the logic gate 20-3 is turned on, the FET 23 is turned off, and the potential of the output terminal N23 becomes "H". Since both the FETs 22 and 23 of the logic gate 20-4 are on, the potential of the output terminal N23 becomes "L" and the output terminal Q
Is set to “L”, and the inverted-phase output terminal Q / is set to “H”. At time t2, when the clock signal CK becomes “L”, the data signal DA is taken into the master side latch 11B while the output state of the slave side latch 12 is maintained. At time t3, when the clock signal CK becomes “H”, the fetched data signal DA is transmitted to the slave side latch 12 and sent out as an output of the MS-FF. Thus, in the MS-FF of the fourth embodiment, the clock signal C
While K is "L", it takes in data signal DA and sends it out at the rising edge of clock signal CK.

(3) Effect In the first and third embodiments, only the clock signal CK has a single phase. However, in the MS-FF of the fourth embodiment, the input of the data signal DA is also a single-phase input. Is fine. As described in the effect of the first embodiment, if the clock signal line is not routed inside the IC while keeping both phases, the NMOS
In a circuit using a device such as a GaAs MESFET or the like, an inverter is generally inserted in order to generate a negative-phase signal. When the data signal DA is branched and one is input to the master side latch 11B as it is and the other is input via the inverter in the form of the inverted data signal DA /, the transmission time of both signals is the delay of one stage of the inverter. There is a difference, which reduces the phase margin. On the other hand, since the MS-FF of the fourth embodiment operates with the single-phase data signal DA, the difference between the arrival times when the data signal DA and the negative-phase data signal DA / are input to the master-side latch. There is an advantage that you do not need to worry about. In addition, as a secondary effect, a reduction in power consumption due to the use of the logic gates 20-2, 20-3, and 20-4 can be expected as in the first and third embodiments.

Fifth Embodiment FIG. 9 is a circuit diagram of an MS-FF showing a fifth embodiment of the present invention, and is common to elements shown in FIG. 5 showing a third embodiment. Are given. This MS-FF
Now, the slave latch 12 and the master latch 1 shown in FIG.
1A is replaced with a master latch 11-2 having the same configuration as the slave latch 12 in FIG. 5 and a slave latch 12-2 having the same configuration as the master latch 11A in FIG. This MS-FF has a function of reading the state of the data signal DA when the clock signal CK is "H" and sending it out at the falling edge of the clock signal CK, as in FIG. 4 showing the second embodiment. The same operation and effect as those of the second embodiment can be obtained.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) and (b). (A) The latch means 30-1 and 30-2 are provided with two NOs.
Although the gates are constituted by the R gates 31 and 32, they may be constituted by other gates such as a NAND gate. (B) NOR gates 41 and 4 for taking in data signal DA
2 may be constituted by another gate such as a NAND gate.

[0035]

As described above in detail, according to the first aspect of the present invention, the master side latch is constituted by the first and second logic gates and the first latch means,
Since the slave-side latch is constituted by the third and fourth logic gates and the second latch means, it can be used with a single-phase clock signal. Further, when the first switching element in the logic gate is off, the current is reduced Since it is cut, power consumption can be reduced. According to the second aspect of the present invention, since the master side latch and the slave side latch of the first aspect are interchanged, there is no deviation from the edge of the clock signal.
This is an effective circuit when it is desired to use both the rising edge and the falling edge of the clock signal. According to the third aspect of the present invention, the master side latch is constituted by the first and second gates and the first latch means, and the slave side latch is constituted by the third and fourth logic gates and the second latch means. Therefore, it can be used with a single-phase clock signal. Further, since a logic gate is used for the slave side latch as in the first aspect of the invention, power consumption can be reduced as compared with the conventional one. Moreover, while the logic gate is composed of four elements, the first and second gates can be composed of, for example, three elements, so that the number of elements can be reduced as compared with the first aspect of the present invention. According to the fourth aspect of the present invention, since the master side latch and the slave side latch of the third aspect are interchanged, substantially the same effects as those of the second aspect can be obtained.
According to the fifth aspect of the present invention, the master side latch is constituted by the first gate, the second logic gate and the first latch means,
Since the slave-side latch is constituted by the third and fourth logic gates and the second latch means, it can be used with a single-phase clock signal and data signal. In addition, since the logic gate is used, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an MS-FF (master-slave flip-flop circuit) according to a first embodiment of the present invention.

FIG. 2 is a timing chart of FIG.

FIG. 3 is a diagram showing simulation results of FIGS. 1 and 10;

FIG. 4 is a circuit diagram of an MS-FF showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram of an MS-FF according to a third embodiment of the present invention.

FIG. 6 is a timing chart of FIG.

FIG. 7 is a circuit diagram of an MS-FF showing a fourth embodiment of the present invention.

FIG. 8 is a timing chart of FIG.

FIG. 9 is a circuit diagram of an MS-FF showing a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram of a conventional MS-FF.

FIG. 11 is a timing chart of FIG.

[Explanation of symbols]

11, 11-1, 11-2, 11A, 11B Master side latch 12, 12-1, 12-2 Slave side latch 20-1 to 20-4 Logic gate 21 to 24 FET 30-1, 30-2 Latching means 31, 32, 41, 42 NOR gate

Claims (5)

[Claims] 1. A load driving element connected between a first power supply potential and a load-side node, and turned on by a signal connected between the load-side node and an output terminal and input from a first input terminal. , A first switching element that is turned off,
A second switching element connected between a second power supply potential lower than the power supply potential and the output terminal and turned on and off by a signal input from a second input terminal; and the second switching element A basic logic gate having a charge discharging impedance element connected in parallel to the first and second input terminals; and a first and second input terminal having two gates cross-connected between first and second input terminals. And a basic latch means for latching a signal inputted from the two gates with the two gates and outputting a complementary signal from the first and second output terminals. A slave flip-flop circuit, wherein the master-side latch includes the basic logic gate, a data signal is input to the first input terminal, and a clock signal is input to the second input terminal. And a first logic gate to which a clock signal is inputted to the first input terminal and the clock signal is inputted to the second input terminal. 2 logic gates, and first latch means comprising the basic latch means, wherein the first and second input terminals are respectively connected to the output terminals of the first and second logic gates, The slave side latch includes the basic logic gate, the clock signal is input to the first input terminal, and the second input terminal is connected to a first output terminal of the first latch means. A third logic gate, and the basic logic gate, wherein the clock signal is input to the first input terminal, and the second input terminal is connected to a second output terminal of the first latch means. A fourth logic gate connected; A second latch means comprising basic latch means, wherein the first and second input terminals are respectively connected to the output terminals of the third and fourth logic gates. Slave flip-flop circuit. 2. A master-slave flip-flop circuit, wherein the master-side latch and the slave-side latch of claim 1 are interchanged. 3. A basic logic gate and basic latch means according to claim 1, wherein a signal inputted from a first input terminal is taken in response to a signal inputted from a second input terminal, and said signal is taken from an output terminal. A master-slave flip-flop circuit comprising a master-side latch and a slave-side latch, the master-side latch comprising the basic gate, and a first input terminal connected to the first input terminal. A first gate to which a data signal is input and a clock signal to be input to the second input terminal; and the basic gate, wherein the clock signal is input to the first input terminal, A second gate to which an inverted-phase data signal is input to an input terminal; and the basic latch means, wherein the first and second input terminals are connected to output terminals of the first and second gates, respectively. The slave-side latch comprises the basic logic gate, the clock signal is input to the first input terminal, and the second input terminal is connected to the first input terminal. A third logic gate connected to a first output terminal of the latch means; and the basic logic gate. The clock signal is input to the first input terminal, and the second input terminal is connected to the second input terminal. A fourth logic gate connected to a second output terminal of the first latch means; and the basic latch means, wherein the first and second input terminals are outputs of the third and fourth logic gates. A master-slave flip-flop circuit comprising: a second latch means connected to each of the terminals. 4. A master-slave flip-flop circuit, wherein the master-side latch and the slave-side latch of claim 3 are interchanged. 5. A basic logic gate and basic latch means according to claim 1, wherein a signal inputted from a first input terminal is taken in response to a signal inputted from a second input terminal, and said signal is taken from an output terminal. A master-slave flip-flop circuit comprising a master-side latch and a slave-side latch, the master-side latch comprising the basic gate, and a first input terminal connected to the first input terminal. A first gate to which a clock signal is input and a data signal to be input to the second input terminal; and a basic logic gate, wherein the data signal is input to the first input terminal, A second logic gate for inputting the clock signal to an input terminal thereof, and the basic latch means, wherein the first and second input terminals are outputs of the first gate and the second logic gate. First latch means connected to the respective terminals, wherein the slave-side latch is configured by the basic logic gate, the clock signal is input to the first input terminal, and the second input terminal is A third logic gate connected to a first output terminal of the first latch means; and a basic logic gate, wherein the clock signal is input to the first input terminal, and the second input A fourth logic gate whose terminal is connected to a second input terminal of the first latch means; and the basic latch means, wherein the first and second input terminals are the third and fourth input terminals. A master-slave flip-flop circuit comprising: a second latch means connected to an output terminal of the logic gate.