JP2000031740A - Oscillator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the attenuation of the oscillation amplitude of an output terminal side at the time of switching a gate for oscillation and to prevent the defect of clock pulses by detecting an oscillation state on the input terminal side of the gate for the oscillation. SOLUTION: By the ON of an NMOS transistor N1, an oscillation operation started by the positive feedback loop of an NMOS inverter by a load circuit 2 and the NMOS transistor N2 and an oscillator 1. An oscillation detection circuit 3 outputs inversion pulses synchronized with the oscillation amplitude on the side of an input terminal X1 and the output terminal (q) of a pulse counting circuit 4 is shifted to an H level. A PMOS transistor P3 is turned OFF and the load circuit 2 is turned to an OFF state. The output of an inverter G1 becomes an L level and the PMOS transistor P1 is turned ON. A CMOS inverter composed of the PMOS transistor P2 and the NMOS transistor N2 is turned to an active state and the gate for the oscillation is switched from the NMOS inverter to a CMOS inverter type.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit using a crystal oscillator, a ceramic oscillator, or the like, and is particularly suitable for being incorporated in a semiconductor integrated circuit such as a microprocessor for low voltage operation and low current consumption. Oscillation circuit.

[0002]

2. Description of the Related Art In an oscillation circuit that performs an oscillation operation by forming a positive feedback loop of an oscillation gate having the function of an inverting amplifier and an oscillator such as a crystal oscillator or a ceramic oscillator, a CMOS gate is used as the oscillation gate. If you use
In order to start oscillation, a power supply voltage at least equal to the sum of the respective threshold voltages of the PMOS transistor and the NMOS transistor forming the CMOS gate is required, which is an obstacle to lowering the voltage. On the other hand, for example, the PMOS transistor side is replaced with a constant current source or a load such as a resistor, and N
If the gate configuration of a MOS inverter is used, the NMOS
Since the operation of the oscillation gate can be performed even under a low voltage near the threshold voltage of the transistor, the gate configuration is effective for lowering the voltage. However, in this case, since a through current flows to the NMOS transistor side, the oscillation amplitude increases, and in a state where the oscillation is stable, there is a disadvantage in terms of current consumption as compared with the case using the CMOS gate. Therefore,
Japanese Patent Application Laid-Open Nos. 4-167806 and 6-97732 propose a method of operating the oscillation gate such that the above-described NMOS inverter or the like suitable for low-voltage operation is activated when the oscillation is started, and switching to only the CMOS gate configuration after the oscillation is stabilized. JP-A-7-154143
And a number of proposals have been made, for example, Japanese Patent Application Laid-Open No. 8-8650. Among them, the oscillation circuit described in JP-A-7-154143 is shown in FIG.
Shown in

In FIG. 3, an oscillator 1 such as a crystal oscillator or a ceramic oscillator and a feedback resistor RF are provided in parallel between a terminal X1 and a terminal X2, and a terminal X1 and a reference potential (hereinafter referred to as GND) are provided. ), And between the terminal X2 and GND, respectively.

A PMO constituting a CMOS inverter
An S transistor P8 and an NMOS transistor N5, and a PMOS transistor P7 and an NMOS transistor N4 for controlling selection / non-selection thereof are connected to a power supply terminal VCC.
And PMOS transistor P8, and GND and NMO
The gate of the NMOS transistor N4 is provided between the PMOS transistor P7 and the S transistor N5.
Connected to the output of the inverter G8 whose input is connected to the gate of the inverter G8.

The NMOS transistor N7 and the resistor R2 connected to its drain constitute an NMOS inverter,
A PMOS transistor P9 and an NMOS transistor N6 for controlling selection / non-selection thereof are provided between the power supply terminal VCC and the resistor R2 and between the GND and the NMOS transistor N7, respectively. It is connected to the output of an inverter G9 whose input is connected to the gate of the transistor P9.
Then, the PMOS transistor P8, the NMOS transistor N5, and the NMO
Each gate of the NMOS transistor N7 constituting the S inverter is connected to the terminal X1, and each drain is connected to the terminal X2.

On the side of the terminal X2, an amplitude detecting circuit 6 for outputting a high-level detection signal when the amplitude of the terminal X2 exceeds a certain value, and a NAND gate for connecting one input to the output of the amplitude detecting circuit 6 G12 and one input are NAND
A NAND gate G11 having the other input connected to the output of the gate G12 and the terminal X2, and an output connected to the other input of the NAND gate G12;
2 and an inverter G13 for connecting the input to the internal clock terminal CLK and the output to the internal clock terminal CLK, respectively. NAN
The output of the D gate G12 is connected to the PMOS transistor P
7 and through the inverter G10 to the PMOS
Each is connected to the gate of the transistor P9.

Although the inverter G13 is not disclosed in the above publication, assuming that the oscillation amplitude of the terminal X2 is taken in as an internal clock of the semiconductor integrated circuit, the oscillation amplitude of the terminal X2 as in the inverter G13 is in any case. There is a buffer gate for receiving and supplying this as an internal clock. Here, for convenience, an inverter G13 is provided and its output is regarded as an oscillation circuit output, that is, an internal clock of the semiconductor integrated circuit.

The operation of the oscillation circuit shown in FIG. 3 will be described below.

First, immediately after the power supply voltage is applied to the power supply terminal VCC, if the oscillation amplitude of the terminal X2 has not yet expanded, the output of the amplitude detection circuit 6 is at the low level.
Therefore, the output of the NAND gate G12 goes to the high level, the PMOS transistor P7 connecting the gate to the output is OFF, and the output of the inverter G8 goes to the low level, and the NMOS transistor N4 connecting the gate to the output also goes to the O level.
It is in the FF state. Therefore, the PMOS transistors P8, N
The CMOS inverter including the MOS transistor N5 is in a non-selected state.

On the other hand, the output of the inverter G10 is at a low level, and the PMOS transistor P9 connecting the gate to the output is ON, and the output of the inverter G9 is at the high level, and the NMOS transistor N6 is connected to the gate.
Is also in the ON state, the NMOS inverter side including the resistor R2 and the NMOS transistor N7 is in the selected state.

Therefore, initially, when the power supply voltage is applied, NM
Since the OS inverter operates to start oscillation, an oscillation gate configuration suitable for starting oscillation under low voltage can be obtained.

After the power supply voltage is applied, an oscillation operation is started by a positive feedback loop between the NMOS inverter and the oscillator 1. When the oscillation amplitude gradually increases and the oscillation amplitude at the terminal X2 reaches a predetermined amplitude, the amplitude is detected. The output of the circuit 6 changes to the high level. When the output of the amplitude detection circuit 6 transitions to the high level, the output of the NAND gate G12 becomes low.
Level to the PMOS transistor P7 and NM
The OS transistor N4 is turned on, and the CMOS inverter including the PMOS transistor P8 and the NMOS transistor N5 is in a selected state. On the other hand, the output of the inverter G10 becomes High level, the PMOS transistor P9 and the NMOS transistor N6 are turned off, and the resistors R2 and NM
The NMOS inverter composed of the OS transistor N7 switches to the non-selected state.

At this time, the oscillation amplitude at the terminal X1 is
PMOS transistors P8 and N constituting the S inverter
If the voltage is equal to or higher than each threshold voltage Vth of the MOS transistor N5, this CMOS inverter can function as an inverting amplifier, and the oscillation operation is maintained. That is,
For example, if the potential of the terminal X1 with respect to GND when the oscillation amplitude of the terminal X1 swings to the high potential side is equal to or higher than the threshold voltage Vth of the NMOS transistor N5, the NMOS transistor N5 can be in an active state. Terminal X
Power supply terminal VC when the oscillation amplitude on the 1 side swings to the low potential side
The potential difference between C and the terminal X1 is the PMOS transistor P8
The threshold voltage | Vth | of the PMOS transistor P8 can be in an active state.
If the oscillation amplitude on the 1 side is equal to or more than | Vth |, CM
The operation of the OS inverter is secured. That is, if the power supply voltage is equal to or higher than | Vth |
This means that the oscillation operation can be maintained by the CMOS inverter when the oscillation is stabilized.

However, immediately after the start of the oscillation, the oscillation amplitude is in a very small amplitude state, and the terminals X1 and X2 are short-circuited by the feedback resistor RF. As a result, the potential between the input and output of the oscillation gate is the same, that is, The logic threshold voltage VLT is DC-biased. If the above-mentioned CMOS inverter is used as the oscillation gate here, in order to amplify the small amplitude of the terminal X1 as an inverting amplifier, the PM constituting the CMOS inverter must be used.
Since both the OS transistor P8 and the NMOS transistor N5 need to be active at the DC operating point, the power supply voltage is set to the PMOS transistor P8 and the NMOS transistor N5 constituting the CMOS inverter.
Need to be equal to or higher than the sum of the respective threshold voltages | Vth |

On the other hand, in the oscillation gate configuration using the NMOS inverter, a through current is generated from the resistor R2 whenever the oscillation amplitude at the terminal X2 swings to the high potential side and the NMOS transistor N7 is turned on. The current consumption increases. In the CMOS inverter, since the PMOS transistor P8 and the NMOS transistor N5 operate exclusively, the through current can be suppressed, which is effective for reducing the current consumption in the stable oscillation state.

Therefore, according to the configuration of FIG. 1, the oscillation gate configuration can be automatically switched to the NMOS inverter when the oscillation is activated, and to the CMOS inverter when the oscillation is stabilized with the increased oscillation amplitude. In addition, it is possible to obtain an oscillation circuit that achieves both low consumption current when oscillation is stable.

[0017]

When the oscillation gate is switched to the CMOS inverter side as described above, the oscillation amplitude at the terminal X2 can be temporarily attenuated due to a change in the gain of the oscillation gate. There is. This is shown in FIG.

FIG. 4 is a conceptual diagram showing operation waveforms at the output of the amplitude detection circuit 6, the terminal X2, and the internal clock terminal CLK in FIG. In FIG. 4, after the oscillation is started, the oscillation amplitude is gradually increased by the NMOS inverter, and the clock pulse is applied to the internal clock terminal CLK from the time when the amplitude of the terminal X2 crosses the logical threshold voltage VLT of the inverter G13. Appear. Thereafter, when the output of the amplitude detection circuit 6 transits to the high level, the oscillation gate is switched to the CMOS inverter. At this time, the amplitude of the terminal X2 changes to the amplitude of the terminal X2 due to the fluctuation of the gain of the oscillation gate.
Attenuation occurs as shown in FIG. 3 and the output of the inverter G13, that is, the clock pulse of the internal clock terminal CLK is a
Defects may occur as indicated by the dots. Further, once a clock pulse is lost, an abnormal pulse such as a narrow pulse may be generated before returning to a normal clock pulse again. When such a loss of the clock pulse occurs, a microprocessor or the like that operates using the clock pulse as a system clock has an abnormal operation.

In order to prevent the loss of the clock pulse, the oscillation gate is switched after the amplitude of the terminal X2 has been sufficiently increased, so that the influence of the amplitude attenuation at the time of switching does not affect the output side of the inverter G13. There is a need to. Therefore, the amplitude detection circuit 6 needs to set the detection amplitude with a sufficient margin in consideration of this. This leads to an increase in the period from the start of oscillation to the switching of the gate for oscillation. In applications where the start and stop of oscillation are repeated frequently, the operation period of the NMOS inverter becomes relatively long, thereby reducing current consumption. It also becomes a hindrance factor.

A first object of the present invention is to provide an oscillation circuit capable of reducing the attenuation of the oscillation amplitude on the terminal X2 side when the oscillation gate is switched and easily preventing the loss of the clock pulse. is there.

Further, a second object of the present invention is to prevent the above-mentioned clock pulse from being lost, and at the same time to prevent the CM of the oscillation gate from being early.
An object of the present invention is to provide an oscillation circuit which can be switched to an OS gate to further reduce current consumption.

[0022]

The first object is achieved by detecting the oscillation amplitude at the terminal X1 and switching the oscillation gate.

The second object is to provide an amplifying circuit between the terminal X2 and the internal clock terminal CLK which can always amplify the minute amplitude on the terminal X2 side, and detect the oscillation amplitude on the terminal X1 side to oscillate. It is achieved by switching the gate for use.

The above specific circuit configuration and other means will be clarified in the embodiments.

The oscillation amplitude at the terminal X2 is always larger than the oscillation amplitude at the terminal X1 which is the input amplitude due to the amplification effect of the oscillation gate. Therefore, the terminal X1
When the oscillation amplitude is detected and the oscillation gate is switched, if the detected amplitude is the same, the amplitude attenuation at the terminal X2 side at the time of switching can be made milder, and the above-described clock pulse deficiency can be prevented. Can be achieved.

By providing an amplifying circuit that can always amplify the minute amplitude on the terminal X2 side, the influence of the amplitude attenuation on the terminal X2 side when the oscillation gate is switched can be reduced, so that the earlier oscillation can be achieved. Gate can be switched, and the current consumption can be further reduced.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, an oscillator 1 and a feedback resistor RF are provided in parallel between a terminal X1 and a terminal X2, as in the conventional example of FIG. 3, and are provided between the terminal X1 and the GND, and between the terminal X1 and the terminal X2. Capacitors C1 and C2 are provided between X2 and GND, respectively.

Also, a PMOS transistor P2 and an NMOS
The transistor N2 forms a CMOS inverter type oscillation gate, and the NMOS transistor N2 and the GND
, An NMOS transistor N1 having a gate connected to the control terminal CS, and a PMOS transistor P1 provided between the PMOS transistor P2 and the power supply terminal VCC. The gates of the PMOS transistor P2 and the NMOS transistor N2 constituting the CMOS inverter are connected to the terminal X1, and the drains are connected to the terminal X2.
Are connected in common.

A load circuit 2 comprising a resistor R1 having one end connected to the terminal X2 and a PMOS transistor P3 connected between the other end of the resistor R1 and the power supply terminal VCC, between the terminal X2 and the power supply terminal VCC. Is provided, and when the PMOS transistor P3 is turned on, the resistor R1 and the NMOS transistor N2 form an NMOS inverter.

An oscillation detecting circuit 3 comprising a Schmitt type NAND gate G3 having one input connected to the terminal X1.
And a pulse counting circuit 4 for connecting the pulse input terminal ck to the output of the oscillation detecting circuit 3. The output terminal q of the pulse counting circuit 4 is connected to the gate of the PMOS transistor P3 and via the inverter G1. The gate is connected to the gate of the PMOS transistor P1 and the other input of the Schmitt type NAND gate G3.

The oscillation amplitude of the terminal X2 is equal to that of the inverter G2.
To the internal clock terminal CLK.

The pulse counting circuit 4 includes capacitors C3 and C4 each having one end connected to GND, a PMO having a gate connected to the pulse input terminal ck, and a source connected to the power supply terminal VCC.
S transistor P4, current suppressing means 5 connected between the drain of PMOS transistor P4 and capacitor C3,
Inverter G4 that connects input to pulse input terminal ck
And a gate connected to the output of the inverter G4, and a capacitor C3
PMOS transistor P6 connected between the capacitor C4
And an inverter G7 connecting the input to the reset terminal r
And a gate connected to the output of the inverter G7, and a capacitor C4
NMOS transistor N3 provided in parallel with
And an inverter G5 connecting an input to a connection point between the capacitor C4 and the PMOS transistor P6, and an inverter G6 connecting an input to an output of the inverter G5 and an output to an output terminal q, respectively. The means 5 is constituted by a PMOS transistor P5 whose gate is connected to GND.

The operation of this embodiment will be described below with reference to FIG. FIG. 2 shows operation waveforms of the present embodiment.

First, in the oscillation stop state, the control terminal C
S and the reset terminal r of the pulse counting circuit 4 are both at the low level, the NMOS transistor N1 is in the OFF state, the output terminal q of the pulse counting circuit 4 is at the low level output, and the PMOS transistor P3 whose gate is connected to this is turned on. State. At this time, the terminal X2 is biased by the load circuit 2 to the potential of the power supply terminal VCC, and the terminal X1 is also biased to the potential of the power supply terminal VCC by the feedback resistor RF.

In the pulse counting circuit 4, the NMO
When the S-transistor N3 is turned on, the capacitor C4 is in a discharged state, so that its terminal potential becomes the GND potential, and the output terminal q becomes the low level output. Schmitt type NA
The ND gate G3 outputs a low level because all inputs are at a high level. In response to this, the PMOS transistor P4 turns on and charges the capacitor C3 to the potential of the power supply terminal VCC. The PMOS transistor P6 is in the OFF state in response to the High level output of the inverter G4, and cuts off between the capacitors C3 and C4.

Subsequently, the control terminal CS and the pulse counting circuit 4
, The oscillation amplitude of the terminals X1 and X2 is still in a minute amplitude state immediately after that, and the Schmitt type NAND gate G3 does not respond to this. There is no change in the state of No. 4, and the output terminal q maintains the Low level. Therefore, the PMOS transistor P1 is OFF, and the load circuit 2 is ON. When the NMOS transistor N1 is turned ON, an NMOS inverter is formed by the load circuit 2 and the NMOS transistor N2, and oscillation is performed by a positive feedback loop between the NMOS inverter and the oscillator 1. The operation starts.

When the oscillation amplitude on the terminal X1 side is increased to exceed the hysteresis width of the input threshold voltage of the Schmitt NAND gate G3, the Schmitt NAND
The gate G3 starts outputting an inverted pulse synchronized with the oscillation amplitude of the terminal X1. In response, the PMOS transistor P4 and the PMOS transistor P6 in the pulse counting circuit 4
Perform an ON / OFF operation alternately, and alternately perform charging of the capacitor C3 and distribution of charge to the capacitor C4 to gradually increase the terminal voltage of the capacitor C4.

That is, when the pulse input terminal ck is low, the PMOS transistor P4 is turned on to charge the capacitor C3, and the PMOS transistor P6 is turned off to block the transfer of charge from the capacitor C3 to the capacitor C4. . At this time, since the charging current peak to the capacitor C3 can be suppressed by the current suppressing means 5, it is effective in reducing radiation noise and the like. The channel length of the PMOS transistor P4 may be increased to provide a current suppressing function to itself, but in that case, the gate capacity is increased, which is disadvantageous in terms of current consumption.

Next, when the pulse input terminal ck goes high, the PMOS transistor P4 is turned off to stop charging the capacitor C3, and the PMOS transistor P6 is turned on to transfer the charge of the capacitor C3 to the capacitor C3.
Distribute to 4 sides.

The terminal voltage VC4 of the capacitor C4 is
Assuming that the respective capacitance coefficients of C4 are C3 and C4 and the number of times of charge distribution is n, the following theoretical formulas can be used.

[0042]

VC4 = VCC [1- {C4 / (C3 + C4)} ⁿ ] Inverter G receiving terminal voltage VC4 of capacitor C4
When the logical threshold voltage VLT reaches 5, the output terminal q transitions to the high level. As shown in the above equation, the respective capacitance coefficients of the capacitors C3 and C4 must be set appropriately. As a result, the rate of increase in the terminal voltage VC4 of the capacitor C4 can be adjusted, so that the transition timing of the output terminal q to the high level can be set to a desired value.

As described above, the output terminal q of the pulse counting circuit 4
Transitions to the high level, the P connecting the gate to this
The MOS transistor P3 is turned off, and the load circuit 2
It turns off. On the other hand, the output of the inverter G1 becomes low level, the PMOS transistor P1 connecting the gate to the output turns on, the CMOS inverter consisting of the PMOS transistor P2 and the NMOS transistor N2 becomes active, and the oscillation gate is changed from the NMOS inverter to the CM.
It is switched to the OS inverter type. Further, since one input of the Schmitt type NAND gate G3 becomes Low, the output of the Schmitt type NAND gate G3 is fixed to High level. Therefore, the pulse counting circuit 4 stops its operation thereafter, but the charge of the capacitor C4 is held, so that the pulse counting circuit 4 maintains the high output. By stopping the operation of the pulse counting circuit 4, it is possible to reduce the invalid current consumption after switching the oscillation gate. When the operation of the pulse counting circuit 4 is not stopped, the Schmitt NAND
What is necessary is just to connect all the inputs of the gate G3 to the terminal X1.

At this time, although the amplitude on the terminal X2 side is slightly attenuated as shown in FIG. 2 due to the gain fluctuation before and after the switching of the oscillation gate, the clock at the internal clock terminal CLK as shown in FIG. It does not lead to pulse loss. This is because the oscillation amplitude of the terminal X1 corresponding to the input side of the oscillation gate is detected and switched, and
This is because the oscillation amplitude at the terminal X1 at the time of switching to the CMOS inverter can be set to an amplitude that can sufficiently activate the PMOS transistor P2 and the NMOS transistor N2 constituting the CMOS inverter. Note that the (slight) amplitude attenuation on the terminal X2 side at the time of switching has almost no effect on the oscillation amplitude on the terminal X1 side because the feedback resistance RF is usually a high resistance on the order of MΩ. It is possible to transmit a stable clock pulse without interruption in CLK.

As described above, according to this embodiment, in addition to the effects of lowering the operating voltage and lowering the current consumption as in the conventional example of FIG. 1, it is also effective for stabilizing the internal clock when switching the oscillation gate. An oscillation circuit can be obtained. Further, the oscillation gate switching timing can be easily adjusted by setting the capacitances C3 and C4 in the pulse counting circuit 4, so that the oscillation circuit can further easily reduce the current consumption by optimizing the oscillation gate switching timing. Is obtained.

FIG. 5 shows a second embodiment of the present invention.

In this embodiment, an amplifying circuit 7 is used instead of the inverter G2 in the first embodiment shown in FIG.
Is provided.

Further, instead of the Schmitt type NAND gate G3, the oscillation detection circuit 3 is provided by a Schmitt type inverter G14.
Is replaced with a PMOS transistor P3 and a resistor R1 and PM
Each of the load circuits 2 is constituted by the OS transistor P10. However, these are not essentially different from those in FIG. 1. For example, the PMOS transistor P10 attempts to substitute the resistor R1 in FIG. 1 with its ON resistance, and may be replaced with the configuration in FIG.

The amplifying circuit 7 includes a coupling capacitor C5 having one end connected to the terminal X2, an NMOS transistor N8 having a gate connected to the other end of the coupling capacitor C5, a drain connected to the internal clock terminal CLK, and a source connected to GND. And the gate to GND, the internal clock terminal C
It comprises a PMOS transistor P11 having a drain connected to LK and a source connected to the power supply terminal VCC, and a resistor R3 connected between the gate and drain of the NMOS transistor N8.

The pulse counting circuit 4 has the same configuration as that shown in FIG. 1, and a detailed description of the circuit configuration is omitted.

The operation of this embodiment is basically the same as that of the first embodiment shown in FIG. 1, but has the following features by employing the amplifier circuit 7.

That is, since the amplifier circuit 7 has a configuration of an NMOS inverter using the PMOS transistor P11 as a load MOS, it can cope with low-voltage operation, and is affected by the DC operating point on the terminal X2 side by the coupling capacitance C5. Without changing its DC operating point by NM
Since it can be biased to the logic threshold voltage VLT as an OS inverter, it can function as a high gain inverting amplifier. Therefore, regardless of the DC operating point of the terminal X2, the minute amplitude is always amplified and the internal clock terminal C
Since the signal can be sent to the LK, a stable clock pulse output can be obtained even when the amplitude of the terminal X2 is attenuated when the oscillation gate is switched. Therefore, the switching of the oscillation gate can be performed early, and the current consumption of the oscillation gate can be reduced.

The configuration of the amplifier circuit 7 is not limited to that shown in FIG. 5, but may be another configuration as long as it has the above functions. A plurality of amplifier circuits 7 may be provided to obtain an internal clock.

According to this embodiment, in addition to the same effects as those of the first embodiment, further stabilization of the internal clock and reduction of the current consumption of the oscillation gate by early switching of the oscillation gate are achieved. Thus, an oscillation circuit that can be operated is obtained.

FIG. 6 shows a third embodiment of the present invention.

In the present embodiment, in addition to the second embodiment shown in FIG.
Are provided.

The pulse counting circuit 8 has a circuit configuration similar to that of the pulse counting circuit 4, and has a reset terminal r.
Is connected to the output terminal q of the pulse counting circuit 4, and the pulse input terminal ck is a Schmitt type inverter G that forms the oscillation detection circuit 3 together with the pulse input terminal ck of the pulse counting circuit 4.
14 outputs. The output terminal q is connected to the gate of the PMOS transistor P11 in the amplifier circuit 7 and serves as a control input of the clock selection circuit 9.

The clock selection circuit 9 includes a clocked inverter G16 for connecting the input to the output of the amplification circuit 7 and the output to the internal clock terminal CLK, and the oscillation detection circuit 3
, An input to an output of the clocked inverter G17, and an inverter G15 to connect an input to a control input of the clocked inverter G17 and an output to a control input of the clocked inverter G16, respectively. The inverter G15
Is connected to the output terminal q of the pulse counting circuit 8 as a control input terminal. Note that the clocked inverters G16 and G17 function as inverters when a high-level signal is given to the control input, and the control input becomes low.
When it is at the level, it is assumed that the output is in a high impedance state.

The operation of this embodiment will be described below.

As in the first embodiment shown in FIG. 1, the terminals X1 and X2 are biased to the high level by the load circuit 2 before the oscillation is started when both the control terminal CS and the reset terminal r of the pulse counting circuit 4 are at the low level. And the pulse counting circuit 4 outputs a low level in the reset state,
In response to this, the pulse counting circuit 8 is also placed in the reset state and outputs a low level. Therefore, the PMOS transistor P11 that connects the output terminal q of the pulse counting circuit 8 to the gate is in the ON state,
The OS inverter is placed in the active state. In the clock selection circuit 9, the control input on the clocked inverter G16 side becomes High, and the clocked inverter G16
Are in a state of functioning as an inverter, and the clocked inverter G17 is in an output high impedance state because the control input is low.

Next, the control terminal CS and the pulse counting circuit 4
When the oscillation start is performed by setting both of the reset terminals r to the High level, the load circuit 2 and the NMOS
The oscillating operation is started by the oscillating gate of the NMOS inverter configuration by the transistor N2. The minute oscillation amplitude at the terminal X2 immediately after the start of the oscillation is determined by the amplification circuit 7
And transmitted to the internal clock terminal CLK via the clocked inverter G16.

When the amplitude of the terminal X1 increases until it exceeds the hysteresis width of the input threshold voltage of the Schmitt inverter G14, an inverted pulse is output from the oscillation detection circuit 3 in synchronization with the amplitude of the terminal X1. When the pulse counting circuit 4 counts this and counts a predetermined number of pulses, the output terminal q is shifted to the high level.

When the output terminal q of the pulse counting circuit 4 transitions to the high level, the load circuit 2 is switched, as in the first embodiment.
Is turned off, and the oscillation gate is formed by a PMOS transistor P2 and an NMOS transistor N2.
Switching to the inverter is performed, but the clock pulse is supplied to the internal clock terminal CLK without being affected by the switching of the oscillation gate by the amplifying circuit 7 as in the second embodiment of FIG.

The output terminal q of the pulse counting circuit 4
In response to the high transition, the pulse counting circuit 8 sets the oscillation detection circuit 3
Start counting output pulses. Then, when the predetermined number of pulses are counted, the output terminal q is changed to the high level, whereby the PMOS transistor P in the amplifier circuit 7 is changed.
11 is turned off, the clocked inverter G17 is switched to the active state, and an oscillation pulse from the oscillation detection circuit 3 is sent to the internal clock terminal CLK. At this time, the control input of the clocked inverter G16 is low, and the output of the clocked inverter G16 is switched to the high impedance state.

As described above, the current consumption in the amplifier circuit 7 can be reduced by switching the clock pulse source from the amplifier circuit 7 side to the oscillation detection circuit 3 side. This is extremely effective in reducing the current consumption of the oscillation circuit in the case where an NMOS inverter type gate configuration or the like is employed for the low voltage operation of the amplifier circuit 7 as shown in FIGS.

After switching the oscillation gate,
By counting the output pulses of the oscillation detection circuit 3 again and switching the clock pulse source, even if the output pulse of the oscillation detection circuit 3 is deficient due to the amplitude attenuation on the terminal X1 accompanying the switching of the oscillation gate, This can be prevented from being transmitted to the internal clock terminal CLK.

In an oscillation circuit mounted on a microprocessor or the like, an external clock may be input and used. In this case, the external clock is usually input to the input terminal side of the oscillation gate, that is, the terminal X1. Is done.
It is necessary to narrow down the current driving capability of the oscillation gate as much as possible from the viewpoint of reducing the current consumption. However, if the external clock input mode is provided, the floating gate on the terminal X2 side follows the external clock. The load must be driven, which is a regulating factor in reducing the current consumption of the oscillation gate.
However, according to the configuration of the present embodiment shown in FIG. 6, since the output pulse from the oscillation detection circuit 3 is finally taken in as the internal clock, the oscillation gate should take the external clock input mode into consideration. Therefore, optimization can be independently performed, which is advantageous for reducing current consumption.

According to the present embodiment, it is possible to obtain an oscillation circuit in which the current consumption is further reduced in addition to the effects of the first and second embodiments. Further, according to the present embodiment, it is possible to obtain an oscillation circuit which is also suitable for the purpose of inputting an external clock to the terminal X1.

FIG. 7 shows a fourth embodiment of the present invention.

In FIG. 7, each gate is connected to terminal X1.
In addition, a PMOS transistor P13 and an NMOS transistor N10 each having a drain connected to the terminal X2 form a CMOS inverter type oscillation gate.
A PMOS transistor P12 having a gate connected to the control terminal CS via an inverter G18 is provided between the MOS transistor P13 and the power supply terminal VCC, and an NMOS transistor N is provided between the NMOS transistor N10 and GND.
9 are connected to each other. The load circuit 1 includes a resistor R4 having one end connected to the terminal X2 and an NMOS transistor N11 connected between the other end of the resistor R4 and GND.
0 is configured. The output terminal q of the pulse counting circuit 4 is connected to the gate of the NMOS transistor N9.
The NMOS transistor N is connected via the inverter G19.
11 and one input of a Schmitt NAND gate G3. Except for the above, the configuration is the same as that of the first embodiment in FIG.

In the first embodiment shown in FIG. 1, the oscillation gate configuration of the NMOS inverter type is employed at the time of oscillation start. In FIG. 7, however, the oscillation gate configuration is of the PMOS inverter type. That is, since the output terminal q of the oscillation start pulse counting circuit 4 is at the low level, NM
OS transistor N9 is off, and inverter G19
The output becomes High, the NMOS transistor N11 connecting the gate to this turns ON, and the PMOS transistor P1
3 and the load circuit 10 are activated. When the oscillation amplitude of the terminal X1 increases and the output terminal q of the pulse counting circuit 4 transitions to the high level,
NMOS transistor N9 is ON, and inverter G1
9 output becomes low and NMOS transistor N11 becomes O
FF, the oscillation gate is a PMOS transistor P13,
The configuration is switched to the CMOS inverter configuration including the NMOS transistor N10.

As described above, according to the configuration of FIG.
An operation similar to that of the first embodiment shown in FIG. 1 can be performed by using an inverter configuration. This can be applied to the second and third embodiments shown in FIGS.

According to the present embodiment, it is possible to obtain an oscillation circuit having the same effects as in the first embodiment.

[0074]

According to the present invention, the oscillation amplitude on the input terminal side of the oscillation gate is detected to switch the oscillation gate configuration, thereby reducing the oscillation amplitude attenuation on the output terminal side during switching. Therefore, an oscillation circuit which can easily prevent the loss of the clock pulse can be obtained.

According to the present invention, the provision of the amplifier circuit 7 makes it possible to switch the oscillation gate configuration at an early stage.
An oscillation circuit in which the current consumption of the oscillation gate is further reduced can be obtained.

Further, according to the present invention, by switching the clock pulse source after oscillation stabilization from the oscillation gate output to the oscillation detection circuit 3 output side, it is possible to reduce the current consumption in the amplifier circuit 7 and reduce the external clock input mode. Thus, it is possible to obtain an oscillation circuit in which the oscillation gate can be optimized independently of the above.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a voltage waveform chart showing the operation of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional configuration.

FIG. 4 is a voltage waveform diagram showing a conventional operation.

FIG. 5 is a circuit diagram showing a configuration of a second example of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a fourth embodiment of the present invention.

[Explanation of symbols]

1: oscillator, 2, 10: load circuit, 3: oscillation detection circuit,
4, 8 pulse counting circuit, 5 current suppressing means, 6 amplitude detection circuit, 7 amplification circuit, 9 clock selection circuit, VC
C: power supply terminal, CS: control terminal, CLK: internal clock terminal, X1, X2: terminal, RF: feedback resistor, R1, R
2, R3, R4: resistance, C1, C2, C3, C4: capacitance, C5: coupling capacitance, P1, P2, P3, P
4, P5, P6, P7, P8, P9, P10, P11,
P12, P13 ... PMOS transistors, N1, N2
N3, N4, N5, N6, N7, N8, N9, N10, N
11 ... NMOS transistors, G1, G2, G4, G
5, G6, G7, G8, G9, G10, G13, G1
5, G18, G19: inverter, G3: Schmitt type NAND gate, G11, G12: NAND gate, G
14: Schmidt type inverter, G16, G17: Clocked inverter.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tadashi Sanbe 3-1-1, Sachimachi, Hitachi-shi, Ibaraki Pref. Hitachi, Ltd. Hitachi Plant (72) Inventor Katsunori Koike 3-2-2, Sachimachi, Hitachi-shi, Ibaraki No. 1 Hitachi Engineering Co., Ltd. (72) Inventor Satoshi Sugai 3-1-1, Sachimachi, Hitachi City, Ibaraki Prefecture Inside Hitachi Works, Ltd.Hitachi Plant (72) Inventor Hiroyuki Kida Hiroyuki Kida, Ibaraki Prefecture 3-Chome 1-1 F-term in Hitachi, Ltd. Hitachi Plant (reference) 5J079 BA24 BA39 BA41 EA04 EA11 EA15 EA16 FA05 FA14 FA21 FB01 FB03 FB04 FB20 FB32 FB34 FB37 FB48 GA05 GA09 GA14 GA18 GA19 JA01 JA06 KA01

Claims (7)

[Claims] An oscillation circuit which forms a positive feedback loop of an oscillation gate and an oscillator connected in parallel between the input and output terminals of the oscillation gate to perform an oscillation operation, wherein the oscillation gate has a first mode. The oscillation circuit according to claim 1, wherein the oscillation state is detected at the input terminal side of the oscillation gate when detecting the oscillation state and switching to the second mode. 2. A first form of the oscillation gate is a load type inverter comprising a MOS transistor and a load circuit for supplying a load current to the MOS transistor, and a second form is a CMOS type inverter. The oscillation circuit according to claim 1, wherein 3. An oscillation circuit for performing an oscillation operation by forming a positive feedback loop of an oscillation gate having a gate configuration switching function and an oscillator connected in parallel between the input and output of the oscillation gate, An oscillation detection circuit connected to the input terminal side,
An oscillation circuit, comprising: a pulse counting circuit that counts output pulses of an oscillation detection circuit; and switching the gate configuration of an oscillation gate according to an output signal of the pulse counting circuit. 4. An oscillation circuit for performing an oscillation operation by forming a positive feedback loop of an oscillation gate having a gate configuration switching function and an oscillator connected in parallel between the input and output of the oscillation gate, An oscillation detection circuit connected to the input terminal side,
A pulse counting circuit that counts output pulses of the oscillation detection circuit, an amplification circuit connected to the output terminal side of the oscillation gate,
An oscillation circuit that switches the gate configuration of an oscillation gate in accordance with an output signal of a pulse counting circuit and extracts an oscillation pulse via an amplifier circuit. 5. An oscillating circuit that performs an oscillating operation by forming a positive feedback loop of an oscillating gate having a gate configuration switching function and an oscillator connected in parallel between the input and output of the oscillating gate. An oscillation detection circuit connected to the input terminal side,
A first pulse counting circuit that counts output pulses of the oscillation detection circuit, a second pulse counting circuit that starts counting output pulses of the oscillation detection circuit with a delay after the first pulse counting circuit, An amplifier circuit connected to the output terminal side,
A selection circuit for selecting and outputting one of the output pulse of the oscillation detection circuit and the output pulse of the amplification circuit; and switching the gate configuration of the oscillation gate by the output signal of the first pulse counting circuit. An oscillation circuit for switching a pulse selection of a selection circuit in accordance with an output signal of a second pulse counting circuit, and extracting and extracting an oscillation pulse from an output pulse of an amplifier circuit to an output pulse of an oscillation detection circuit. 6. The oscillation circuit according to claim 3, wherein said oscillation detection circuit comprises a Schmitt input gate having hysteresis in an input threshold voltage. 7. A pulse counting circuit comprising: a first capacitor connected between a first terminal and a reference potential;
A second capacitor connected between the second terminal and the reference potential;
A first switching means connected between the first terminal and the second terminal; a second switching means and a current suppressing means interposed between the first terminal and the power supply terminal and connected in series with each other; Comprising: a first switching unit and a second switching unit;
6. The oscillation circuit according to claim 3, wherein an exclusive operation is performed in synchronization with the input count pulse, and an output signal is transmitted by a voltage appearing at the second terminal.