JP2000031191A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide CSP(chip size package) type semiconductor device structure for appropriately absorbing the deformation stresses and distortions of both a semiconductor chip and a motherboard caused by the difference in the thermal coefficients of expansion. SOLUTION: An external connection terminal land 19, consisting of a first metal layer 16 that is electrically connected to an arbitrary electrode 3, a buffer layer 17 formed on the first metal layer 16, and a second metal layer 18 that, is electrically connected to the first metal layer 16 while covering the surface of the buffer layer 17 is provided at a surface side, where the electrode 3 of the semiconductor chip 2 is formed in a semiconductor device 1a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to the structure of a CSP (Chip Size Package) type semiconductor device.

[0002]

2. Description of the Related Art With the spread of portable electronic devices such as portable telephones in recent years, further miniaturization of semiconductor devices used therein has been required. To satisfy this demand, semiconductor devices of a type called a CSP have been proposed by various companies.

For example, there is a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 8-340002. FIG. 12 shows a CSP type semiconductor device of this type. The semiconductor device 1 shown here has a passivation film 4 formed in a region other than the electrode 3 on the surface of the semiconductor chip 2 on which the electrode 3 is formed, and an insulating film formed in a surface of the passivation film 4 also in a region other than the electrode 3. A film (insulating sheet) 5 and a wiring pattern 6 formed on the surface of the insulating film 5, one end of which is connected to the electrode 3, and the other end of which is an external connection terminal joint 7, an insulating film 5 and a wiring pattern 6. It comprises an insulating film 8 formed in a region other than the above-mentioned external connection terminal joint 7 and an external connection terminal 9 mounted on the external connection terminal connection 7. According to the semiconductor device 1 having such a configuration, the semiconductor device 1 can be thin and have the same outer diameter as the outer diameter of the semiconductor chip 2.

The semiconductor device 1 of this type generally uses solder balls as the external connection terminals 9.
When the semiconductor device 1 is mounted on the motherboard 10, the external connection terminals 9 formed of solder balls of the semiconductor device 1 are aligned with the pads 11 of the motherboard 10, and then heated to melt the solder balls. 1
And the motherboard 10 are electrically connected.

As described above, the semiconductor device 1 and the motherboard 1
When a solder ball is used for connection to the semiconductor device 1, there are advantages that the semiconductor device 1 can be reduced in size and that a large number of external connection terminals 9 can be connected collectively.

As described above, when the semiconductor device 1 and the motherboard 10 are connected by using the solder balls as the external connection terminals 9, both are mechanically connected via the solder balls. Incidentally, silicon is generally used as the semiconductor chip 2 of the semiconductor device 1, but a glass epoxy resin, a ceramic substrate, or the like is often used as a material of the motherboard 10.

The problem here is that both the semiconductor chip 2 and the motherboard 10 have completely different coefficients of thermal expansion. When the semiconductor device 1 is subjected to a heat cycle such as heating and cooling when the semiconductor device 1 is used or during a reliability evaluation test, the semiconductor device 1 may be subjected to a thermal expansion coefficient difference between the semiconductor chip 2 and the motherboard 10. Stress and mechanical distortion occur. However, the semiconductor chip 2 and the motherboard 10 are connected to the external connection terminals 9 made of solder balls as described above.
Mechanical stress, there is no escape for such stress and strain, and these stress and strain are concentrated on the external connection terminals 9 made of solder balls. However, although the solder balls have high rigidity but lack flexibility, they cannot absorb these stresses and strains. As a result, cracks 12 are generated in the external connection terminals 9 made of the solder balls, and the semiconductor device 1 and the mother board are not connected. There is a problem that the electrical connection with the semiconductor device 10 is lost and the reliability of the semiconductor device 1 is reduced.

In the semiconductor device 1 described above, the insulating film 5 and the insulating film 8 are formed by the semiconductor chip 2 and the motherboard 10.
It is expected to be a buffer layer of various stresses generated between the layers. However, the structure using the insulating film 5 and the insulating film 8 as a buffer layer functions effectively in terms of protecting the surface of the semiconductor chip 2.
It is very difficult to absorb a large deformation stress or strain caused by a difference between the thermal expansion coefficient of the mother board 10 and that of the mother board 10. Therefore, as shown in FIG. 13, an attempt has been made to reduce the load on the solder balls by filling the underfill resin 13 between the semiconductor device 1 and the motherboard 10 and reinforcing the connection between them. .

[0009]

However, in this method, a step of filling the underfill resin 13 is required, so that the lead time is lengthened and new equipment must be introduced for that purpose. there were. Further, there is a problem that repair of the semiconductor device 1 is very difficult. The present invention has been made in view of such circumstances, and has as its object to provide a semiconductor device structure capable of favorably absorbing deformation stress caused by a difference in thermal expansion coefficient between a semiconductor chip and a motherboard.

[0010]

In order to solve the above problems, a semiconductor device according to the present invention has a structure in which a stress buffer layer is provided on a functional surface of a semiconductor chip, whereby heat applied to the semiconductor chip and the motherboard is reduced. It is designed to absorb the repetitive stress of the cycle.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a first metal layer electrically connected to an arbitrary electrode at an arbitrary position on the electrode forming surface side of a semiconductor chip, and a first metal layer formed on the first metal layer. And a second metal layer that covers the surface of the buffer layer and that is electrically connected to the first metal layer.

The buffer layer may be made of a non-conductive resin such as a polymer resin, a polyimide resin, an elastomer resin, an epoxy resin, a silicon resin, a urethane resin, an acrylic resin, or a conductive resin. Although a conductive material such as a paste can be used, it is preferable to use a polyimide coat or a conductive paste in consideration of workability.

When a non-conductive resin material is used for the buffer layer, such a non-conductive resin material generally has a high flexibility, and therefore, the non-conductive resin material has a large thermal expansion coefficient difference between the semiconductor device and the mother board. This has the effect that the deformation stress can be absorbed very well, and the use of a conductive paste as the buffer layer simplifies the structure of the semiconductor device. This has the effect of improving efficiency.

Further, since this buffer layer forming step can be performed using the same equipment as that of a normal wafer fabrication step, it is not necessary to introduce any new special equipment or method, and the semiconductor device can be manufactured in a similar manner. Manufacturing costs can be reduced.

When a conductive paste is used as the buffer layer, the first metal layer and the second metal layer are electrically connected by the conductive paste. When a material is used, the first metal layer and the second metal layer are electrically connected directly, or both are electrically connected via the third metal layer.

Although the buffer layer can be provided at any position on the electrode forming surface of the semiconductor chip, it may be formed on the electrode of the semiconductor chip. Further, external connection terminal lands may be formed on the electrodes. By using the electrodes in this manner, the degree of freedom in forming a wiring pattern on the electrode forming surface of the semiconductor chip can be ensured.

When connecting the semiconductor chip to the motherboard, a land grid array structure may be used in which the external connection terminal lands are directly connected to the electrode pads of the motherboard using a solder paste or the like. A ball grid array structure may be used in which an external connection terminal such as the above is mounted and a connection to the motherboard is made by the external connection terminal. In the case of the land grid array structure, there is an advantage that the semiconductor device can be formed relatively thin, and in the case of the ball grid array structure, the height can be secured between the semiconductor device and the motherboard. This has the advantage that deformation stress can be more easily absorbed.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and manufacturing method of a semiconductor device according to the present invention will be described below in detail with reference to the drawings. The same parts as those in the related art will be described using the same symbols.
FIG. 1 is a diagram showing a semiconductor device of the present invention. In the semiconductor device 1a shown here, a passivation film 4 is formed in a region other than the electrodes 3 on the surface of the semiconductor chip 2 on which the electrodes 3 are formed, and an insulating film 5 is formed in a region on the surface of the passivation film 4 other than the electrodes 3. Are formed.

Here, in this embodiment, the first insulating layer 14 is formed on the surface of the insulating film 5 in a region other than the electrode 3.
Are provided, and a concave portion 15 is formed in a portion of the first insulating layer 14 corresponding to the external connection terminal joining portion. On the surface of the first insulating layer 14, one end is connected to the electrode 3, and the other end is a first surface surrounding the inner surface of the concave portion 15 provided at a position corresponding to the external connection terminal junction and the periphery thereof.
The wiring pattern 6 is formed so as to become the metal layer 16 of FIG.

On the first metal layer 16 formed in the concave portion 15 provided at a position corresponding to the external connection terminal junction,
A buffer layer 17 made of a polyimide coat is formed, and a second metal layer made of copper or the like that covers the surface of the buffer layer 17 and is electrically connected to the first metal layer 16 is formed thereon. 18 are formed. An external connection terminal land 19 is formed by the first metal layer 16, the buffer layer 17, and the second metal layer 18. In addition, each metal layer has a role of maintaining adhesion to the base material, and has a wettability with a base metal formed mainly by sputtering, copper plating having a role of achieving electrical conduction, and further with solder. Made of one or more metals such as gold plating for improving the quality.

Then, the entire surface excluding the surface of the external connection terminal land 19, that is, the buffer layer 17 formed on the wiring pattern 6, the first insulating layer 14, and the electrode 3 is covered with the second insulating layer 20. Thereafter, if necessary, the external connection terminals 9 such as solder balls are mounted on the surfaces of the external connection terminal lands 19 to form the semiconductor device 1a shown in FIG.

Next, a manufacturing process of the semiconductor device 1a shown in FIG. 1 will be described. First, as shown in FIG. 4, a passivation film 4 is formed in a region excluding the electrodes 3 of a semiconductor chip 2 made of silicon on which electrodes 3 made of aluminum are formed on one surface.
To form

Then, as shown in FIG. 5, an insulating film 5 made of an insulating material such as a polyimide coat is applied to a region other than the electrode 3 on the passivation film 4 by a method such as spin coating. When a photosensitive material is used as the insulating material, an insulating film 5 is applied to the entire surface including the electrode 3, and is exposed and developed using a glass mask to perform patterning in a known manner. Alternatively, only the electrode 3 can be exposed by immersion in a solution.

Subsequently, as shown in FIG. 6, the entire surface including the electrode 3 on the insulating film 5 is covered with a first insulating layer 14 made of an insulating material such as a photosensitive solder resist.
Thereafter, the portion of the first insulating layer 14 which becomes the electrode 3 portion and the external connection terminal junction is removed by exposure and development to expose the electrode 3 and form the concave portion 15.
The first insulating layer 14 may be coated with a solder resist by applying a liquid material by spin coating or screen printing. However, the first insulating layer 14 has a certain thickness (0.1 ~ 0.3mm)
Therefore, it is preferable to perform the drying by laminating a dry film. The insulating layer 14 is preferably made of a colored material, preferably a black material, so as not to cause photoexcitation of the device as much as possible.

Next, a metal layer is formed on the surface of the first insulating layer 14 by depositing, sputtering or plating a conductive metal such as copper. Then, a photosensitive resist is applied on the metal layer, and is exposed and developed to perform patterning. Then, an unnecessary portion of the metal layer is removed by etching to form a wiring pattern 6 as shown in FIG. One end of the wiring pattern 6 is connected to the electrode 3, and the other end extends to the concave portion 15 which is an external connection terminal junction. In this case, one or more of chromium, titanium, and tungsten or an alloy thereof may be formed as a barrier layer on the electrode 3 in advance. Here, a conductive metal layer is also formed on the inner side surface of the concave portion 15 and the periphery thereof, and this becomes the first metal layer 16. Note that, in this embodiment, an example in which patterning is performed by etching has been described, but patterning may be performed by an additive method or the like.

Subsequently, as shown in FIG. 8, a buffer layer 17 made of an insulating material such as a polyimide coat is formed on the electrode 3 and on the first metal layer 16 formed in the recess 15.
The buffer layer 17 is formed by applying a liquid insulating material by a spin coating method or the like. In this embodiment, the buffer layer 17 is formed so as to protrude slightly (about 0.01 to 0.1 mm) from the recess 15.

Next, as shown in FIG. 9, a second metal layer 18 made of a conductive metal such as copper so as to cover the surface of the buffer layer 17 and to be electrically connected to the first metal layer 16.
To form The second metal layer 18 is also formed by vapor deposition, sputtering, plating, or the like, similarly to the formation of the wiring pattern 6 described above. In the present embodiment, since the external connection terminal lands are not formed on the electrode 3, the second metal layer 18 is not formed on the surface of the buffer layer 17 on the electrode 3. When forming 19, the second metal layer 18 is also formed on the buffer layer 17 on the electrode 3. When the external connection terminal land 19 is not formed on the electrode 3, the buffer layer 17 may not be formed.

Thereafter, as shown in FIG. 10, the entire region including the first insulating layer 14, the wiring pattern 6, and the second metal layer 18 is covered with a second insulating layer 20 made of an insulating material such as a photosensitive solder resist. Then, only the second metal layer 18 of the external connection terminal land 19 is exposed by photolithography. The formation of the second insulating layer 20 may be performed by applying a liquid insulating material, or by laminating a dry film, similarly to the formation of the first insulating layer 14. The insulating layer 14
It is preferable to use a material that does not cause α-ray damage to the device as much as possible.

Thereafter, the exposed portion of the second metal layer 18 is plated with a metal having good solder wettability. This is completed when using the land grid array structure, but when using the external connection terminal 9 as a means for connecting to the motherboard, FIG.
The external connection terminals 9 made of solder balls are arranged on the second metal layers 18 of the external connection terminal lands 19 exposed from the second insulating layer 20, and are fixed by reflow as shown in FIG.

By the above steps, the semiconductor device 1a of the present invention
Is completed, but the material of each part and the like are not limited to this embodiment, and can be appropriately changed. For example, in the above-described configuration, the passivation film 4 and the like are not necessarily required. Each of the above-described manufacturing steps may be performed for each of the semiconductor chips 2 which are individually separated, or all the steps may be performed at a wafer level, and then each of the semiconductor chips may be divided. In particular, when assembly is performed at the wafer level, work efficiency is improved.

The semiconductor device 1a manufactured as described above
The external connection terminal 9 as described above may be used to mount the semiconductor device on the motherboard, or the portion of the second metal layer 18 of the external connection terminal land 19 is directly bonded to the motherboard via a solder paste or the like. You may do so.

Next, another embodiment of the present invention will be described. FIG. 2 shows another embodiment of the present invention. In the semiconductor device 1b shown here, the buffer layer 17 is not formed on the electrode 3. The wiring pattern 6 is formed on the insulating film 5. Then, on the first metal layer 16 which is one end of the wiring pattern 6, the first metal layer 16
A third metal layer 21 is formed so as to be electrically connected to the third metal layer 21, and the buffer layer 17 is formed on the third metal layer 21. Further, a second metal layer 18 is formed so as to cover the surface of the buffer layer 17 and to be electrically connected to the third metal layer 21.
The external connection terminal lands 19a are constituted by the second metal layer 18, the third metal layer 21, and the buffer layer 17. Other configurations are substantially the same as those in the above-described embodiment, and the same applies to the manufacturing process. In the case of this embodiment, the first metal layer 16 and the second metal layer 18 are
Electrically connected by Although not formed in this embodiment, the buffer layer 17 or the external connection terminal land 19a may be formed on the electrode 3.

FIG. 3 shows still another embodiment of the present invention, in which a conductive paste is used as a buffer layer. In the semiconductor device 1c shown here, the wiring pattern 6 is formed on the insulating film 5 as in the embodiment shown in FIG. A buffer layer 17a made of a conductive paste is formed on the first metal layer 16 which is one end of the wiring pattern 6, and the second metal layer 1 is formed on the surface of the buffer layer 17a.
8 are formed. According to this configuration, the second insulating layer 20 is not necessarily required.

The manufacturing process of the semiconductor device 1c will be briefly described. The process up to the formation of the insulating film 5 is substantially the same as that of the above-described embodiment, but in this embodiment, the insulating film 5 is formed on the insulating film 5 as described above. One end is connected to the electrode 3 by vapor deposition, sputtering, plating, or the like, and the other end forms a wiring pattern 6 serving as an external connection terminal connection portion. Then, the entire surface of the semiconductor chip 2 including the insulating film 5 and the wiring pattern 6 on the electrode 3 forming surface side is made of a first insulating layer 1 made of an insulating material such as a photosensitive solder resist.
4, and then, a portion corresponding to the external connection terminal joint portion of the first insulating layer 14 is removed by exposing and developing to form a concave portion 15. The first metal layer 16 serving as a portion is exposed.

Then, the first metal layer 16 around the first metal layer 16
The recess 15 surrounded by the insulating layer 14 is filled with a conductive paste by a printing method to form the buffer layer 17a. Thereafter, the second metal layer 18 is formed on the surface of the buffer layer 17a by a plating method to form the external connection terminal lands 19b. After that, it is the same as the above-described embodiment. According to the present embodiment, since the structure of the semiconductor device 1c is simplified, the manufacturing process can be simplified, and the work efficiency at the time of manufacturing is improved. Further, in the present embodiment, the buffer layer 17a or the external connection terminal land 19b is not formed on the electrode 3, but may be formed.

Various embodiments other than those described above can be applied without departing from the gist of the present invention. For example, a heat radiating plate may be fixed to the back surface of the semiconductor chip 2 of each of the semiconductor devices 1a, 1b and 1c on the electrode 3 forming surface side via a conductive adhesive. With such a configuration, heat generated by the semiconductor chip 2 can be efficiently radiated. The fixing of the heat sink can also be performed at the wafer level.

Since the semiconductor devices 1a, 1b and 1c in this embodiment are configured as described above, the semiconductor devices 1a, 1b and 1c can be used at the time of use or at the time of reliability evaluation test.
Even when 1b and 1c are exposed to thermal cycles such as heating and cooling, the stress and mechanical strain generated due to the difference in the thermal expansion coefficient between the semiconductor chip 2 and the motherboard are reduced to the external connection terminal lands 19, 19a, The buffer layers 17 and 17a provided in the buffer layer 19b can favorably absorb the stress. As a result, no crack is generated in the external connection terminal 9, and even when the land grid array structure is employed, such a stress can be prevented. And the mechanical strain does not adversely affect the semiconductor chip 2.

[0038]

The present invention is embodied in the form described above, and has the following effects.

Even when the semiconductor device is subjected to a heat cycle such as heating or cooling during use or during a reliability evaluation test, stress and mechanical strain caused by a difference in thermal expansion coefficient between the semiconductor chip and the motherboard are reduced. Since the buffer layer of the external connection terminal land can favorably absorb, when the external connection terminal or the land grid array structure is used, cracks do not occur at the joints of the solder paste or the like. The reliability is significantly improved.

Further, since underfill is not required, repair is easy even after the semiconductor device is once mounted on a motherboard or the like.

Furthermore, the semiconductor device of the present invention can be assembled in an existing wafer fabrication facility such as a wafer coater, and it is not necessary to introduce new facilities and methods, so that it can be manufactured at a relatively low cost. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 2 is a sectional view showing another embodiment of the present invention.

FIG. 3 is a sectional view showing another embodiment of the present invention.

FIG. 4 is an enlarged sectional view of a main part showing a manufacturing process of the present invention.

FIG. 5 is an enlarged sectional view of a main part showing a manufacturing process of the present invention.

FIG. 6 is an enlarged sectional view of a main part showing a manufacturing process of the present invention.

FIG. 7 is an enlarged sectional view of a main part showing a manufacturing process of the present invention.

FIG. 8 is an enlarged sectional view of a main part showing a manufacturing process of the present invention.

FIG. 9 is an enlarged sectional view of a main part showing a manufacturing process of the present invention.

FIG. 10 is an enlarged sectional view of a main part showing a manufacturing process of the present invention.

FIG. 11 is an enlarged sectional view of a main part showing a manufacturing process of the present invention.

FIG. 12 illustrates a conventional semiconductor device.

FIG. 13 illustrates a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 1a, 1b, 1c Semiconductor device 2 Semiconductor chip 3 Electrode 4 Passivation film 5 Insulating film 6 Wiring pattern 7 External connection terminal connection part 8 Insulation film 9 External connection terminal 10 Motherboard 11 Pad 12 Crack 13 Underfill resin 14 First Insulating layer 15 Concave part 16 First metal layer 17, 17a Buffer layer 18 Second metal layer 19, 19a, 19b External connection terminal land 20 Second insulating layer 21 Third metal layer

Claims (6)

[Claims] A first metal layer electrically connected to an arbitrary electrode on an electrode forming surface side of a semiconductor chip having a plurality of electrodes formed on one surface; and a first metal layer on the first metal layer. A buffer layer formed on the first layer and a first layer covering the surface of the buffer layer;
And a second metal layer electrically connected to the first metal layer and an external connection terminal land. 2. The semiconductor device according to claim 1, wherein the buffer layer is made of a conductive paste. 3. The semiconductor device according to claim 1, wherein a third metal layer for electrically connecting the first metal layer and the second metal layer is provided on the external connection terminal land. . 4. The semiconductor device according to claim 1, wherein a buffer layer is formed on an electrode of the semiconductor chip. 5. The semiconductor device according to claim 1, wherein an external connection terminal land is provided on an electrode of the semiconductor chip. 6. The semiconductor device according to claim 1, wherein an external connection terminal is mounted on the external connection terminal land.