JP2000031151A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2000031151A
JP2000031151A JP11190372A JP19037299A JP2000031151A JP 2000031151 A JP2000031151 A JP 2000031151A JP 11190372 A JP11190372 A JP 11190372A JP 19037299 A JP19037299 A JP 19037299A JP 2000031151 A JP2000031151 A JP 2000031151A
Authority
JP
Japan
Prior art keywords
film
dielectric film
semiconductor device
semiconductor substrate
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11190372A
Other languages
Japanese (ja)
Inventor
Yasushi Haga
泰 芳賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP11190372A priority Critical patent/JP2000031151A/en
Publication of JP2000031151A publication Critical patent/JP2000031151A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PROBLEM TO BE SOLVED: To enhance residual polarization characteristics by forming a dielectric film on a semiconductor substrate directly or through other layer and then performing annealing while applying a field to the dielectric film. SOLUTION: Platinum is deposited by DC sputtering onto a first interlayer insulation film, i.e., a silicon oxide film 202, formed on a semiconductor substrate 201 and then a lower electrode 203 is formed by etching followed by formation of a dielectric film 204 by sputtering. Subsequently, the semiconductor substrate 201 is placed in a heating furnace and subjected to annealing while applying a DC voltage of 100 V between parallel plate electrodes. Thereafter, an upper electrode 205 is formed on the dielectric film 204 followed by sequential formation of a second interlayer insulating film 206 of silicon oxide film, a contact hole, an aluminum wiring layer 207 and a protective film 208 thus forming a semiconductor device.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法、
より詳しくは誘電体素子が能動素子の形成された同一半
導体基板上に集積された半導体装置の製造方法に関す
る。
The present invention relates to a method for manufacturing a semiconductor device,
More specifically, the present invention relates to a method for manufacturing a semiconductor device in which a dielectric element is integrated on the same semiconductor substrate on which an active element is formed.

【0002】[0002]

【従来の技術】半導体基板上に直接あるいは他の層を介
して強誘電体膜を形成する工程と、前記誘電体膜をアニ
ールする工程とを含む半導体装置の製造方法において、
残留分極向上のためには前記強誘電体中における自発分
極の方向を揃えること、すなわち結晶の配向軸を一定の
方向にすることが有効であることが知られている。しか
し従来は強誘電体の結晶化の際に強誘電体に対して電界
を印加することなく、熱処理のみを行っていたおり、結
晶化後に改めて前記強誘電体に電界を加えて分極処理を
行なっていたため、結晶化の際に自発分極の方向が各分
域で揃っていず、後から分極処理を行なうがその時の歪
の影響で、前記強誘電体の強誘電特性はバルク結晶に比
べてかなり劣っていた。その特性は例えばジャーナル・
オブ・アプライド・フィジックス(Journal o
f Applied Physics)、1991年、
第70巻、第1号、382項〜388項によれば、前記
強誘電体にPZT(Pb(Zr0.5Ti0.5)O3)を用
いた場合、強誘電体膜厚0.5μmで残留分極Prは約
15μC/cm2程度であった。
2. Description of the Related Art A method of manufacturing a semiconductor device includes a step of forming a ferroelectric film directly or via another layer on a semiconductor substrate, and a step of annealing the dielectric film.
It is known that it is effective to align the direction of spontaneous polarization in the ferroelectric, that is, to make the orientation axis of the crystal constant in order to improve the remanent polarization. However, conventionally, only a heat treatment was performed without applying an electric field to the ferroelectric during crystallization of the ferroelectric, and after the crystallization, a polarization treatment was performed by applying an electric field to the ferroelectric again. Therefore, the direction of spontaneous polarization during crystallization is not aligned in each domain, and polarization processing is performed later, but due to the strain at that time, the ferroelectric characteristics of the ferroelectric are considerably larger than those of the bulk crystal. Was inferior. Its characteristics are, for example,
Of Applied Physics (Journal o
f Applied Physics), 1991,
According to Vol. 70, No. 1, paragraphs 382 to 388, when PZT (Pb (Zr 0.5 Ti 0.5 ) O 3 ) is used as the ferroelectric, the remanent polarization is obtained at a ferroelectric film thickness of 0.5 μm. Pr was about 15 μC / cm 2 .

【0003】[0003]

【発明が解決しようとする課題】しかしながら、前記強
誘電体の半導体基板への集積など微細加工に伴って強誘
電体素子の面積は必然的に制限されるため、この残留分
極の値では実用上不十分であった。
However, since the area of the ferroelectric element is necessarily limited by microfabrication such as integration of the ferroelectric on a semiconductor substrate, the value of this remanent polarization is not practical. It was not enough.

【0004】そこで本発明はかかる問題を解決するもの
で、その目的とするところは残留分極特性を向上させる
ことにある。
The present invention solves such a problem, and an object of the present invention is to improve remanent polarization characteristics.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に直接あるいは他の層を介して
誘電体膜を形成する工程と、前記誘電体膜に電界を印加
した状態でアニールする工程とを含むことを特徴とす
る。前記電界は前記アニール工程の降温時にのみ印加し
てもよく、また印加する電界は交流電界でもよい。さら
に、前記誘電体が2つの電極によって挟まれた構造を有
している場合には前記電界を直接前記電極に印加するこ
とも可能である。また、前記誘電体材料としてPZT
(Pb(ZrTi)O3)等の強誘電体を用いてもよ
い。
According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a dielectric film on a semiconductor substrate directly or through another layer, and applying an electric field to the dielectric film. And annealing step. The electric field may be applied only when the temperature is lowered in the annealing step, and the applied electric field may be an AC electric field. Further, when the dielectric has a structure sandwiched between two electrodes, the electric field can be directly applied to the electrodes. Further, PZT is used as the dielectric material.
A ferroelectric material such as (Pb (ZrTi) O 3 ) may be used.

【0006】[0006]

【実施例】以下に本発明に於ける実施例を図に従って説
明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

【0007】図2は本発明の半導体装置の製造方法の第
1の実施例の説明図である。まず、図2(a)のように
半導体基板201上の第1の層間絶縁膜としてのシリコ
ン酸化膜202上に白金(Pt)をDCスパッタ法にて
0.2μm成膜し、フォト工程を経てアルゴンイオンを
用いたイオンビームエッチングによりエッチングして下
部電極203とする。その後、RFスパッタ法によりP
ZT(Pb(ZrTi)O3)を0.3μm形成し、誘
電体膜204とする(図2(b))。
FIG. 2 is an explanatory view of a first embodiment of a method of manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 2A, 0.2 μm of platinum (Pt) is formed on a silicon oxide film 202 as a first interlayer insulating film on a semiconductor substrate 201 by a DC sputtering method, and a photo process is performed. The lower electrode 203 is formed by etching by ion beam etching using argon ions. After that, P
ZT (Pb (ZrTi) O 3 ) is formed to a thickness of 0.3 μm to form a dielectric film 204 (FIG. 2B).

【0008】次に上記手順で誘電体膜204を形成した
前記半導体基板103を図1(a)に示すような電極間
距離10cmのメッシュ型の平行平板電極101を石英
管ヒーター102の内側に設置した加熱炉にて、平行平
板電極間に100Vの直流電圧を印加した状態で酸素雰
囲気中にて600℃、1時間の熱処理を行なう。
Next, the semiconductor substrate 103 on which the dielectric film 204 is formed by the above procedure is placed on the inside of a quartz tube heater 102 with a mesh-type parallel plate electrode 101 having a distance of 10 cm between electrodes as shown in FIG. In a heating furnace, heat treatment is performed at 600 ° C. for 1 hour in an oxygen atmosphere with a DC voltage of 100 V applied between the parallel plate electrodes.

【0009】この後、前記半導体基板上前記誘電体膜2
04上に上部電極205としてPt0.2μmを成膜、
フォト、エッチングした後(図2(c))、気相成長
(CVD)法によるシリコン酸化膜からなる第2の層間
絶縁膜206の成膜、コンタクトホールの開孔、Al配
線層207の形成、CVD法による保護膜208として
のシリコン窒化膜の形成を経て、図2(d)に示すよう
な断面形状を持つ半導体装置を作成した。本実施例にお
ける半導体装置における強誘電体キャパシタの残留分極
Prを測定したところ、誘電体膜厚0.3μmにおい
て、印加電圧5Vで約30μC/cm2と従来に比べて
大きく向上した。
Thereafter, the dielectric film 2 is formed on the semiconductor substrate.
Pt 0.2 μm is formed as an upper electrode 205 on
After photo-etching (FIG. 2C), a second interlayer insulating film 206 made of a silicon oxide film is formed by a vapor phase epitaxy (CVD) method, a contact hole is opened, an Al wiring layer 207 is formed, After forming a silicon nitride film as the protective film 208 by the CVD method, a semiconductor device having a sectional shape as shown in FIG. When the remanent polarization Pr of the ferroelectric capacitor in the semiconductor device of the present embodiment was measured, it was found to be about 30 μC / cm 2 at a voltage of 5 V at a dielectric film thickness of 0.3 μm.

【0010】図3は本発明の半導体装置の製造方法の第
2の実施例の説明図である。半導体基板301上の第1
の層間絶縁膜としてのシリコン酸化膜302上に白金
(Pt)をDCスパッタ法にて0.2μm成膜し、フォ
ト工程を経てアルゴンイオンを用いたイオンビームエッ
チングによりエッチングして下部電極303とする(図
3(a))。その後、RFスパッタ法によりPZT(P
b(ZrTi)O3)を0.3μm形成し、フォト工
程、エッチング工程により、誘電体膜304を形成する
(図3(b))。しかる後に前記半導体基板上前記誘電
体膜上に上部電極305としてPt0.2μmをDCス
パッタ法により成膜し、前記上部電極と同様にフォト、
エッチング工程を経て図3(c)のような構造を得た。
FIG. 3 is an explanatory view of a second embodiment of the method of manufacturing a semiconductor device according to the present invention. First on the semiconductor substrate 301
Platinum (Pt) is formed by a DC sputtering method on a silicon oxide film 302 as an interlayer insulating film to a thickness of 0.2 μm, and is etched by ion beam etching using argon ions through a photo process to form a lower electrode 303. (FIG. 3 (a)). Then, PZT (P
b (ZrTi) O 3 ) is formed to a thickness of 0.3 μm, and a dielectric film 304 is formed by a photo process and an etching process (FIG. 3B). Thereafter, Pt 0.2 μm is formed as the upper electrode 305 on the dielectric film on the semiconductor substrate by a DC sputtering method.
After the etching step, a structure as shown in FIG. 3C was obtained.

【0011】次に上記手順で上部電極305を形成した
前記半導体基板105を図1(b)に示すような加熱炉
にて、前記半導体基板上第1の層間絶縁膜302上の2
つの電極間に1V、50Hzの交流電圧104を印加し
た状態で600℃、1時間のアニールを行なう。
Next, the semiconductor substrate 105 on which the upper electrode 305 is formed by the above procedure is placed on the first interlayer insulating film 302 on the semiconductor substrate in a heating furnace as shown in FIG.
Annealing is performed at 600 ° C. for 1 hour with an AC voltage 104 of 1 V and 50 Hz applied between the two electrodes.

【0012】この後、第2の層間絶縁膜306としてシ
リコン酸化膜を気相成長(CVD)法で成膜した後、ド
ライエッチングによるコンタクトホールの開孔、スパッ
タリングによるAl配線層307の形成、CVD法によ
る保護膜308としてのシリコン窒化膜の形成を経て、
図3(d)に示すような断面形状を持つ半導体装置を作
成した。
Thereafter, a silicon oxide film is formed as a second interlayer insulating film 306 by a vapor phase growth (CVD) method, a contact hole is opened by dry etching, an Al wiring layer 307 is formed by sputtering, and CVD is performed. Through the formation of a silicon nitride film as a protective film 308 by a method,
A semiconductor device having a sectional shape as shown in FIG.

【0013】本実施例において作成した半導体装置にお
ける強誘電体キャパシタの残留分極Prを測定したとこ
ろ、誘電体膜厚0.3μmにおいて、印加電圧5Vで約
32μC/cm2と従来に比べて大きく向上した。ま
た、容量密度についても約25fF/μm2程度の値を
得ることができた。
When the remanent polarization Pr of the ferroelectric capacitor in the semiconductor device manufactured in the present embodiment was measured, it was found to be about 32 μC / cm 2 at an applied voltage of 5 V at a dielectric film thickness of 0.3 μm. did. Also, a value of about 25 fF / μm 2 was obtained for the capacitance density.

【0014】本実施例においてはアニール時全体に渡っ
て電圧を印加したが、アニール降温時にのみ電圧を印加
してもよく、また交流の周波数は高周波(13.56M
Hz)でもよく、特に制限するものではない。さらに、
誘電体膜が強誘電体の場合には自発分極を制御し、残留
分極を向上するのにはよいが、BaTiO3、(SrB
a)TiO3等のペロブスカイト結晶構造の常誘電体膜
やTaO5,SiO2,SiNx等の容量蓄積キャパシタ
の常誘電体膜の場合においても膜質が向上し、容量密度
を向上することが可能である。また、本実施例において
はPZT(Pb(ZrxTi1ーx)O3)のZr組成比x
を0.5としたが、他の組成でもよい。
In this embodiment, the voltage is applied over the entire annealing time. However, the voltage may be applied only when the temperature of the annealing falls, and the frequency of the alternating current is high (13.56 M).
Hz), and is not particularly limited. further,
When the dielectric film is a ferroelectric, it is good for controlling the spontaneous polarization and improving the remanent polarization, but BaTiO3, (SrB
a) In the case of a paraelectric film having a perovskite crystal structure such as TiO3 or a paraelectric film of a capacitance storage capacitor such as TaO5, SiO2 or SiNx, the film quality can be improved and the capacitance density can be improved. Further, Zr composition ratio x of the In the present embodiment PZT (Pb (ZrxTi1 over x) O 3)
Was set to 0.5, but another composition may be used.

【0015】[0015]

【発明の効果】以上述べたように、本発明の半導体装置
の製造方法においてはアニール時において誘電体膜に電
界を印加することにより、前記誘電体膜が強誘電体の場
合には結晶内の歪を最小にして分極処理を行なうため、
従来より大きな残留分極特性が得られた。また、前記誘
電体膜が常誘電体の場合においても膜質が向上し、容量
密度も従来より大きくなった。これにより、半導体装置
の微細化に伴うキャパシタ面積の縮小化においても十分
な残留分極、あるいは容量密度を実現できるものであ
る。
As described above, in the method of manufacturing a semiconductor device according to the present invention, when an electric field is applied to a dielectric film during annealing, when the dielectric film is a ferroelectric, the inside of the crystal is reduced. In order to perform polarization processing with minimum distortion,
A larger remanent polarization characteristic than before was obtained. Further, even when the dielectric film is a paraelectric material, the film quality is improved and the capacitance density is larger than before. As a result, sufficient remanent polarization or capacitance density can be realized even when the capacitor area is reduced with miniaturization of the semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明における第1及び第2の実施例に於て使
用した加熱炉の模式図。
FIG. 1 is a schematic view of a heating furnace used in first and second embodiments of the present invention.

【図2】本発明における第1の実施例の工程の説明図。FIG. 2 is an explanatory view of a process according to a first embodiment of the present invention.

【図3】本発明における第2の実施例の工程の説明図。FIG. 3 is an explanatory view of a process according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

半導体基板 201、301 第1の層間絶縁膜 202、302 下部電極 203、303 誘電体膜 204、304 上部電極 205、305 第2の層間絶縁膜 206、306 Al配線層 207、307 保護膜 208、308 メッシュ型平行平板電極 101 石英管ヒーター 102 下部電極及び誘電体膜を含む半導体基板 103 交流電源 104 上下電極及び誘電体膜を含む半導体基板 105 Semiconductor substrate 201, 301 First interlayer insulating film 202, 302 Lower electrode 203, 303 Dielectric film 204, 304 Upper electrode 205, 305 Second interlayer insulating film 206, 306 Al wiring layer 207, 307 Protective film 208, 308 Mesh type parallel plate electrode 101 Quartz tube heater 102 Semiconductor substrate including lower electrode and dielectric film 103 AC power supply 104 Semiconductor substrate including upper and lower electrodes and dielectric film 105

─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成11年8月4日(1999.8.4)[Submission date] August 4, 1999 (1999.8.4)

【手続補正1】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】発明の名称[Correction target item name] Name of invention

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【発明の名称】 半導体装置[Title of the Invention] Semiconductor device

【手続補正2】[Procedure amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Correction target item name] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【特許請求の範囲】[Claims]

【手続補正3】[Procedure amendment 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0005[Correction target item name] 0005

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置は、
第1及び第2の電極にて誘電体膜が挟まれた誘電体キャ
パシタを有する半導体装置であって、 前記誘電体膜を超えて第1の方向に延出する第1延出部
を有する前記第1の電極と、 前記誘電体膜を超えて前記第1の方向とは異なる方向に
延出する第2延出部を有する前記第2の電極と、を有す
る事を特徴とする。また、上記内容に加えて、前記第1
及び第2延出部は、同じ層上に配置されてなることを特
徴とする。
According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device having a dielectric capacitor having a dielectric film sandwiched between first and second electrodes, the semiconductor device having a first extending portion extending in a first direction beyond the dielectric film. It has a first electrode and the second electrode having a second extension extending beyond the dielectric film in a direction different from the first direction. In addition, in addition to the above, the first
And the second extension portion is arranged on the same layer.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) // H01L 27/108 21/8242 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) // H01L 27/108 21/8242

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に直接あるいは他の層を介し
て誘電体膜を形成する工程と、前記誘電体膜に電界を印
加した状態でアニールする工程とを含むことを特徴とす
る半導体装置の製造方法。
1. A semiconductor device comprising: a step of forming a dielectric film directly on a semiconductor substrate or via another layer; and a step of annealing the dielectric film in a state where an electric field is applied. Manufacturing method.
【請求項2】半導体基板上に直接あるいは他の層を介し
て誘電体膜を形成する工程と、前記誘電体膜をアニール
する工程とを含む半導体装置の製造方法において、前記
アニール工程の降温時に前記誘電体膜に電界を印加する
ことを特徴とする半導体装置の製造方法。
2. A method for manufacturing a semiconductor device, comprising: a step of forming a dielectric film directly on a semiconductor substrate or through another layer; and a step of annealing the dielectric film. A method for manufacturing a semiconductor device, wherein an electric field is applied to the dielectric film.
【請求項3】請求項1及び2記載の半導体装置の製造方
法において、印加する電界が交流電界であることを特徴
とする半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the applied electric field is an AC electric field.
【請求項4】請求項1及び2及び3記載の半導体装置の
製造方法において、前記誘電体が2つの電極によって挟
まれた構造を持ち、前記電界が前記2つの電極間に印加
されていることを特徴とする半導体装置の製造方法。
4. The method for manufacturing a semiconductor device according to claim 1, wherein said dielectric has a structure sandwiched between two electrodes, and said electric field is applied between said two electrodes. A method for manufacturing a semiconductor device, comprising:
【請求項5】請求項1及び2及び3及び4記載の半導体
装置の製造方法において、前記誘電体がペロブスカイト
結晶構造を有する強誘電体であることを特徴とする半導
体装置の製造方法。
5. The method for manufacturing a semiconductor device according to claim 1, wherein said dielectric is a ferroelectric having a perovskite crystal structure.
JP11190372A 1999-07-05 1999-07-05 Semiconductor device Pending JP2000031151A (en)

Priority Applications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10008617A1 (en) * 2000-02-24 2001-09-06 Infineon Technologies Ag Process for producing a ferroelectric layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10008617A1 (en) * 2000-02-24 2001-09-06 Infineon Technologies Ag Process for producing a ferroelectric layer
US6790676B2 (en) 2000-02-24 2004-09-14 Infineon Technologies Ag Method for producing a ferroelectric layer

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