JP2000031087A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, and a fabrication method thereof, in which resistance of contact formed in p-type impurity region can be decreased. SOLUTION: The fabrication method of semiconductor device comprises a step for forming a first conductivity type well and a second conductivity type well, respectively, in a semiconductor substrate 200, a step for forming a first impurity region in the first conductivity type well, a step for forming a second impurity region in the second conductivity type well, a step for forming an insulation layer on the semiconductor substrate 200, and a step for forming a contact hole by etching the insulation layer until a part of the first and second impurity regions are exposed using a contact hole forming mask such that a contact hole being formed in the first impurity region has larger size than the contact hole being formed in the second impurity region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for manufacturing a contact electrode of a semiconductor device.

[0002]

2. Description of the Related Art As DRAM devices are highly integrated, bit lines are formed of metal to improve performance and reduce chip size. Bit lines made of metal are made of conventional polysilicon
And has a lower sheet resistance than a bit line stacked with tungsten silicide (WSix).

Therefore, when a bit line is formed of metal, the bit line can be formed more minutely than an existing bit line while having the same sheet resistance. In addition, the contact resistance formed in the n-type impurity region can be adjusted to be lower than when using the existing bit line, and a contact can be formed in the p-type impurity region.

FIG. 1 is a cross-sectional view showing a conventional semiconductor device, and FIGS. 2 and 3 are views showing distribution of contact resistance depending on the contact size of each impurity region (anneal).
al 750 ° C for 100 min). First, referring to FIG.
For the contact electrode of the semiconductor device, an n-type well 11 and a p-type well 12 are formed in a semiconductor substrate 10 using a well forming mask.

Thereafter, ap + -type impurity region 13 is formed in the n-type well 11 using the impurity region forming mask, and the p-type well 12 is formed using the impurity region forming mask.
An n + impurity region 14 is formed therein. The impurity implanted into p + impurity region 13 is boron B, and the impurity implanted into n + impurity region 14 is one of arsenic As and phosphorus P.

An oxide film 16 is formed on semiconductor substrate 10 as an insulating film. The contact hole 17 is formed by etching the oxide film 16 using the contact hole forming mask until a portion of each of the n + impurity region 13 and the p + impurity region 14 is exposed. At this time, the contact holes 17 formed in the n + impurity region 13 and the p + impurity region 14 each have the same size of W.

Thereafter, the contact hole 17 is filled with a metal material to form a metal wiring 18. Here, the first method for forming the metal wiring is to form T.sub.T on both side walls and the lower surface of the contact hole 17 and the oxide film 16 by the first method.
After forming an i-film (not shown), the subsequent heat treatment causes titanium to react with silicon
An x layer, that is, an ohmic layer is formed. Then, after removing both side walls of the contact hole 17 and the Ti layer on the oxide film 16 without reacting with the semiconductor substrate 10, the contact hole 1 is removed.
7 is a method of forming a metal wiring by filling TiN or TiN / W.

Second, an ohmic layer is formed by sequentially depositing a Ti film and a TiN film on both side walls and a lower surface of the contact hole 17 and the oxide film 16 and then performing a heat treatment. Thereafter, there is a method of filling the contact hole 17 with W to form a metal wiring. Third, after a Ti film and a TiN film are sequentially deposited on both side walls and a lower surface of the contact hole 17 and the oxide film 16, tungsten is immediately deposited to form a metal wiring. Then, there is a method of forming an ohmic layer by reacting the Si film and the Ti film of the semiconductor substrate 10 in a subsequent heat treatment step.

The metal wiring 18 is formed by any one of the methods described above. As mentioned above, T
When the iSix layer is used as an ohmic layer, boron B ions doped into the p + impurity region 13 by heat treatment applied in a subsequent process and T
A TiB layer is formed by a reaction with the iSix layer.

Since the TiB layer is non-conductive, the contact resistance is increased. Then, the boron ions doped into the p + impurity region 13 escape by the reaction and the doping concentration is reduced, thereby increasing the resistance. The TiSix layer used as the ohmic layer is agglomerated to reduce the surface energy, Contact hole bottom
There is a problem that the effective contact area of the (bottom) is reduced and the resistance is increased. A doped into n + impurity region
s or P does not react with Ti in the TiSix layer.

Referring to FIGS. 2 and 3, when the contact size is A, for example, when the contact size is 0.2
When the thickness is 6 μm, the contact resistance of the n + impurity region shows a value of about 200-300Ω / CNT, and the contact resistance of the p + impurity region shows about 700-800Ω / CNT. However, if the contact size is A / 2
When the diameter is reduced to about 0.15 μm, as shown in FIGS. 2 and 3, the increase in the contact resistance in the p + impurity region 13 is larger than the increase in the contact resistance in the n + impurity region 14. Even if the resistance is low, the contact resistance in p + impurity region 13 sharply increases.

If there is no technique for suppressing such a phenomenon, the chip size is increased unless the target value of the contact resistance in the p + impurity region is set to 5000Ω / CNT or more in the element design. There was nothing else.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of reducing the resistance of a contact formed in a p-type impurity region without increasing the chip size, and a method of manufacturing the same. is there.

[0014]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a first conductivity type well and a second conductivity type well in a semiconductor substrate. Forming a first impurity region in the first conductivity type well; forming a second impurity region in the second conductivity type well; forming an insulating layer on the semiconductor substrate; A contact hole is formed by etching the insulating layer until a portion of the first impurity region and a portion of the second impurity region are each exposed using a formation mask, and the size of the contact hole formed in the first impurity region is reduced. Forming a contact hole formed in the second impurity region to be relatively larger than a contact hole formed in the second impurity region.

According to the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a first conductivity type well formed in the semiconductor substrate; and a semiconductor substrate adjacent to the first conductivity type well. A second conductivity type well formed in the first conductivity type well; a first impurity region formed in the first conductivity type well;
A second impurity region formed in the conductive well, an insulating film formed on the semiconductor substrate, and a first impurity region penetrating the insulating film.
A contact hole electrically connected to the impurity region and the second impurity region, wherein a contact hole formed in the first impurity region has a relatively larger size than a contact hole formed in the second impurity region. .

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first conductivity type well and a second conductivity type well in a semiconductor substrate; Forming a first impurity region in the well, forming a second impurity region in the second conductivity type well, forming an insulating layer on the semiconductor substrate, and using a contact hole forming mask. Etching the insulating layer until a portion of the second impurity region is exposed to form a first contact hole, and filling the first contact hole with a metal material to be electrically connected to the semiconductor substrate. Forming a plug, forming a second insulating layer on the first insulating layer including the plug, and exposing the plug and a portion of the first impurity region using a mask for forming a contact hole, respectively. When The etching the second insulating layer 2
Forming a contact hole and forming a second contact hole formed in the first impurity region to be relatively larger than a size of the first contact hole formed in the second impurity region.

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first conductivity type well and a second conductivity type well in a semiconductor substrate; Forming a first impurity region in the well, forming a second impurity region in the second conductivity type well, forming an insulating layer on the semiconductor substrate, and using a contact hole forming mask. Forming a first contact hole by etching the insulating layer until a portion of the first impurity region is exposed, and filling the first contact hole with a metal material to be electrically connected to the semiconductor substrate. Forming a plug, forming a second insulating layer on the first insulating layer including the plug, exposing portions of the plug and the second impurity region using a contact hole forming mask; When Forming a second contact hole by etching the second insulating layer, and forming the size of the second contact hole in the first impurity region relatively larger than the size of the second contact hole formed in the second impurity region. Stages.

According to the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a first conductivity type well formed in the semiconductor substrate; and a second conductivity type well formed in the semiconductor substrate. A first impurity region formed in the first conductivity type well, a second impurity region formed in the second conductivity type well, a first insulating film formed on the semiconductor substrate, A plug penetrating the film and electrically connected to the second impurity region; a second insulating film formed on the plug and the first insulating film; and a first impurity region penetrating the second insulating film and the plug. And a contact electrode formed in the first impurity region, and the contact hole formed in the first impurity region has a relatively larger size than the contact hole formed in the second impurity region.

Referring to FIGS. 5 and 10, a new semiconductor device and a method for fabricating the same according to an embodiment of the present invention will be described. The contact holes are formed by etching the insulating layer until each is exposed. At this time, the size of the contact hole formed in the first impurity region is relatively larger than the size of the contact hole formed in the second impurity region. By reducing the size of the contact hole formed in the n-type impurity region by such a semiconductor device and the method of manufacturing the same, the contact hole formed in the p-type impurity region is formed wider by the margin generated here. In addition, the contact resistance formed in the p + impurity region can be reduced without increasing the chip size.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6 are views showing a semiconductor device and a method of manufacturing the same according to the embodiment of the present invention in the order of process flow. Referring to FIG. 4, a semiconductor device and a method of manufacturing the same according to the present invention first use a well forming mask to form a semiconductor substrate 10.
An n-type well 101 and a p-type well 102 are respectively formed in 0.

P + impurity region 103 is formed in n-type well 101 using the impurity region forming mask, and n + type impurity region 103 is formed in p-type well 102 using the impurity region forming mask.
+ Impurity region 104 is formed. p + impurity region 10
3 is boron B, and the impurity implanted into the n + impurity region 104 is one of arsenic As and phosphorus P.

After that, referring to FIG.
An oxide film 106 is formed thereon as an insulating film. N + impurity region 10 using contact hole forming mask 108;
The contact hole 109 is formed by etching the oxide film 106 until a portion of the third and p + impurity regions 104 are respectively exposed. At this time, the width W1 between the masks 108 for forming the contact holes in the p + impurity region 103 is relatively wider than the width W2 between the masks 108 for forming the contact holes in the n + impurity region 104.
(W1> W2)

The contact hole 109 may be formed in one of a circular shape, an elliptical shape, and other shapes. Finally, a metal material is filled in the contact hole 109 to form a metal wiring 110 electrically connected to the semiconductor substrate 100 as shown in FIG. The metal material is one of the tungsten W and the TiN film.

Here, the first method is to form a Ti film (not shown) on both side walls and a lower surface of the contact hole 109 and the oxide film 106 by the first method, and then to form a Ti film (not shown). Titanium is converted into semiconductor substrate 10 by heat treatment.
The TiSix layer, that is, the ohmic layer is formed by reacting with the silicon Si of 0. Then, both side walls of the contact hole 109 which does not react with the semiconductor substrate 100 and the oxide film 106 are formed.
After removing the upper Ti layer, T
There is a method of forming metal wiring by filling iN or TiN / W.

Second, an ohmic layer is formed by sequentially depositing a Ti film and a TiN film on both side walls and the lower surface of the contact hole 109 and the oxide film 106 and then performing a heat treatment. Thereafter, there is a method of filling the contact hole 109 with W to form a metal wiring. Third, the side walls and lower surface of the contact hole 109 and the oxide film 10 are formed.
After a Ti film and a TiN film are sequentially deposited on the substrate 6, tungsten is immediately deposited to form a metal wiring. then,
There is a method of forming an ohmic layer by reacting the Si and Ti films of the semiconductor substrate 100 in a subsequent heat treatment step.

The metal wiring 110 is formed by any one of the aforementioned methods. When TiSix is used as an ohmic layer, the size of the contact hole is reduced due to the cohesive action of the TiSix layer during a heat treatment applied in a subsequent process, thereby reducing the effective contact area at the bottom of the contact hole. Although the increase in the contact resistance formed in the region shows a slow value, p +
The contact resistance formed in the impurity region is rapidly increased.

Therefore, in order to prevent an increase in contact resistance due to a reduction in the contact area as described above, in the present invention, by making the pattern width of the mask different,
Contact hole 1 formed in p + impurity region 103
09 can be formed to be relatively wider than the size W2 ′ of the contact hole 109 formed in the n + impurity region 104. (W1 '>W2')

For example, when contact holes of various sizes are formed in the p + impurity region and contact holes of various sizes are formed in the n + impurity region, or contact holes of various sizes are formed only in one impurity region. In this case, the smallest contact hole formed in the p + impurity region is wider than the smallest contact hole formed in the n + impurity region.

Here, the increase in chip size is n +
This can be offset by reducing the size of the contact hole in the impurity region 104. The size of contact hole 109 formed in n + impurity region 104 is reduced by about 10% or more. For example, the conventional p + impurity region 103 and n
When the size of the contact hole formed in the + impurity region 104 is about 200 nm, when the contact hole of the n + impurity region 104 formed according to the embodiment of the present invention is reduced to about 170 nm, the contact hole of the p + impurity region 103 becomes Extendable to about 230 nm.

The size of the contact hole 109 in the p + impurity region 103 is at least 10% larger than the size of the contact hole 109 in the n + impurity region 104, and has a larger size. Referring to FIG. 6, a contact hole W1 ′ formed adjacent to p + impurity region 103 has a relatively larger size than contact hole W2 ′ formed adjacent to n + impurity region 104. Therefore, it is possible to manufacture a semiconductor device capable of reducing the contact resistance of the p + impurity region without increasing the chip size of the semiconductor device.

(Second Embodiment) FIGS. 7 to 10 are sectional views showing a semiconductor device according to a second embodiment of the present invention and a method for fabricating the same in the order of steps. Referring to FIG. 7, in a semiconductor device and a method of manufacturing the same according to the present invention, first, an n-type well 201 and a p-type well 202 are formed in a semiconductor substrate 200 using a well forming mask.

Using an impurity region forming mask, ap + impurity region 203 is formed in n-type well 201, and an n + impurity region 204 is formed in p-type well 202.
The impurity implanted into the p + impurity region 203 is boron B, and the impurity implanted into the n + impurity region 204 is one of arsenic As and phosphorus P. After that, a first oxide film 206 as an insulating film is formed on the semiconductor substrate 200. N using contact hole forming mask 208
By etching the first oxide film 206 until a part of the + impurity region 204 is exposed, a first contact hole 207 is formed as shown in FIG.

Referring to FIG. 9, when the first contact hole 207 is filled with a metal material, a plug 209 electrically connected to the semiconductor substrate 200 is formed. The metal material is one of the tungsten W and the TiN film. A second oxide film 210 having a flat upper surface is formed as an insulating film on the first oxide film 206 including the plug 209. The second contact hole 213 is formed by etching the second oxide film 210 using the contact hole forming mask 212 until the plug 209 and a part of the p + impurity region 203 are exposed.

At this time, the width W1 between the masks 208 for forming the contact holes in the p + impurity region 103 is the first width.
Width W2 between masks 208 for forming contact holes
More relatively wide. Therefore, the second contact hole 213 in the p + impurity region 203 is smaller than the size W2 ′ of the first contact hole 207 formed in the n + impurity region 204.
Are formed relatively wider. (W
1 '>W2')

On the other hand, a first contact hole 207 'may be formed in the p + impurity region 203 to form a plug 208', and a second contact hole 211 'may be formed in the plug 208' and the n + impurity region 204. is there. That is, the size W1 'of the first contact hole 207' of the p + impurity region 203 and the size W of the contact hole 213 'of the n + impurity region 204 (not shown).
It is formed relatively wider than 2 ′. (W1 '> W
2 ')

As described in the first embodiment, the size of the contact hole in n + impurity region 204 is reduced by 10% or more, and the size of the contact hole in p + impurity region 203 can be increased by the margin. Finally, a metal material is filled in the second contact hole 211 'to form a contact electrode 212 as shown in FIG. The metal material is the same material as the material forming the plug 209. FIG.
Referring to, the contact hole W1 ′ formed in the p + impurity region 203 has a relatively larger size than the contact hole W2 ′ formed in the n + impurity region 204.

[0037]

According to the present invention, the size of the contact hole formed in the n-type impurity region is reduced, and the contact hole formed in the p-type impurity region is formed as wide as the margin occurring here, thereby reducing the chip size. P without increase
+ Has the effect of reducing the contact resistance formed in the impurity region.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a conventional semiconductor device and a contact electrode according to a method for manufacturing the same.

FIG. 2 is a diagram illustrating a conventional distribution of contact resistance depending on the size of a contact hole in each impurity region.

FIG. 3 is a diagram illustrating a conventional distribution of contact resistance depending on the size of a contact hole in each impurity region.

FIG. 4 is a diagram showing a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention in the order of process flow.

FIG. 5 is a diagram illustrating a semiconductor device and a method of manufacturing the same according to the embodiment of the present invention in the order of process flow.

FIG. 6 is a diagram showing a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention in the order of process flow.

FIG. 7 is a diagram illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention in the order of process flow.

FIG. 8 is a diagram showing a semiconductor device and a method for manufacturing the same according to the embodiment of the present invention in the order of process flow.

FIG. 9 is a view showing a semiconductor device and a method for manufacturing the same according to the embodiment of the present invention in the order of process flow.

FIG. 10 is a diagram showing a semiconductor device and a method for manufacturing the same according to the embodiment of the present invention in the order of process flow.

[Explanation of symbols]

 100, 200 semiconductor substrate 101, 201 n-type well 102, 202 p-type well 103, 203 p + impurity region 104, 204 n + impurity region 106, 206, 210 oxide film 109, 207, 213 contact hole 207 plug 108, 212 contact electrode

Claims (9)

[Claims] A step of forming a first conductivity type well and a second conductivity type well in a semiconductor substrate; a step of forming a first impurity region in the first conductivity type well; Forming a second impurity region in the mold well; forming an insulating layer on the semiconductor substrate; and using a contact hole forming mask to form a portion of the first impurity region and the second impurity region. The insulating layer is etched to form a contact hole until each is exposed, and the size of the contact hole formed in the first impurity region is relatively larger than the size of the contact hole formed in the second impurity region. Forming a semiconductor device. 2. The method according to claim 1, wherein the first conductivity type well is an n-type well, and the second conductivity type well is a p-type well. 3. The first impurity region is p-type,
2. The method according to claim 1, wherein the second impurity region is n-type. 4. The semiconductor device according to claim 1, wherein the impurity doped in the first impurity region is boron, and the impurity doped in the second impurity region is one of arsenic and phosphorus. 2. The method for manufacturing a semiconductor device according to item 1. 5. The method according to claim 1, wherein the first impurity region has a size larger than that of the second impurity region by 10% or more. 6. A semiconductor substrate, a first conductivity type well formed in the semiconductor substrate, a second conductivity type well formed in the semiconductor substrate, and a first conductivity type well formed in the first conductivity type well. A first impurity region; a second impurity region formed in the second conductivity type well; an insulating film formed on the semiconductor substrate; a first impurity region penetrating the insulating film; A contact hole electrically connected to the impurity region, wherein a contact hole formed in the first impurity region has a relatively larger size than a contact hole formed in the second impurity region. Semiconductor device. 7. A step of forming a first conductivity type well and a second conductivity type well in a semiconductor substrate, a step of forming a first impurity region in the first conductivity type well, and a step of forming the second conductivity type well. Forming a second impurity region in the mold well; forming an insulating layer on the semiconductor substrate; and using a contact hole forming mask until a portion of the second impurity region is exposed. Forming a first contact hole by etching an insulating layer; filling a metal material into the first contact hole to form a plug electrically connected to a semiconductor substrate; Forming a second insulating layer on the first insulating layer; and using the contact hole forming mask until the plug and the first impurity region are partially exposed, respectively.
Forming a second contact hole by etching the insulating layer; forming a second contact hole formed in the first impurity region to be relatively wider than a size of the first contact hole formed in the second impurity region; And a method of manufacturing a semiconductor device. 8. A step of forming a first conductivity type well and a second conductivity type well in a semiconductor substrate, a step of forming a first impurity region in the first conductivity type well, and a step of forming the second conductivity type well. Forming a second impurity region in the mold well; forming an insulating layer on the semiconductor substrate; and using a contact hole forming mask until a portion of the first impurity region is exposed. Forming a first contact hole by etching an insulating layer; filling a metal material into the first contact hole to form a plug electrically connected to a semiconductor substrate; Forming a second insulating layer on the first insulating layer; and using the contact hole forming mask to form the second insulating layer until the plug and a portion of the second impurity region are exposed.
Forming a second contact hole by etching the insulating layer, and forming the first contact hole of the first impurity region relatively larger than the size of the second contact hole formed in the second impurity region. And a method of manufacturing a semiconductor device. 9. A semiconductor substrate, a first conductivity type well formed in the semiconductor substrate, a second conductivity type well formed in the semiconductor substrate, and a first conductivity type well formed in the first conductivity type well. A first impurity region; a second impurity region formed in the second conductivity type well; a first insulating film formed on the semiconductor substrate; and a second impurity formed by penetrating the first insulating film. A plug electrically connected to the region, a second insulating film formed on the plug and the first insulating film, and electrically connected to the first impurity region and the plug by penetrating the second insulating film. And a contact electrode formed in the first impurity region, wherein the contact hole formed in the first impurity region has a relatively larger size than the contact hole formed in the second impurity region.