KR100268410B1 - A semiconductor device and method of fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for reducing contact resistance of a p-type impurity region, wherein an insulating layer is formed until a portion of the first impurity region and the second impurity region are exposed using a contact hole forming mask, respectively. By etching, contact holes are formed. In this case, the size of the contact hole formed in the first impurity region is relatively larger than that of the contact hole formed in the second impurity region. By the manufacturing method of such a semiconductor device, by reducing the size of the contact hole formed in the n-type impurity region, and forming the contact hole formed in the p-type impurity region by the margin generated therein, without increasing the chip size The contact resistance formed in the p-type impurity region can be reduced.

Description

A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for manufacturing a contact electrode of a semiconductor device.

As DRAM devices become more integrated, bit lines are formed of metal to improve performance and reduce chip size. The bit line formed of the metal has a sheet resistance lower than that of a conventional bit line stacked with polysilicon and tungsten silicide (WSix).

Therefore, when the same sheet resistance is desired, even if the pattern is made finer than the existing bit line using metal, there is no problem in the performance of the device. In addition, the contact resistance formed in the n-type impurity region can be controlled to be lower than in the case of using a conventional bit line, and there is an advantage in that a contact can be formed in the p-type impurity region.

1 is a cross-sectional view illustrating a conventional semiconductor device, and FIGS. 2A and 2B are diagrams showing a distribution of contact resistance according to a contact size of each impurity region. (anneal 750 ℃ 100min)

First, referring to FIG. 1, an n-type well 11 and a p-type well 12 are formed in a semiconductor substrate 10 in a contact electrode of a semiconductor device, respectively, using a mask for forming a well.

Next, a p-type impurity region 13 is formed in the n-type well 11 using an impurity region forming mask, and an n + impurity region (in the p-type well 12 is formed using an impurity region forming mask). 14) is formed.

The impurity injected into the p + impurity region 13 is boron (B), and the impurity injected into the n + impurity region 14 is any one of an ashen (As) and a phosphorus (P).

An oxide film 16 is formed on the semiconductor substrate 10 as an insulating film. The contact hole 17 is formed by etching the oxide layer 16 until a portion of the n + impurity region 13 and the p + impurity region 14 are exposed using a contact hole forming mask, respectively. In this case, the contact holes 17 formed in the n + impurity region 13 and the p + impurity region 14 have the same size as W, respectively.

Next, the contact hole 17 is filled with a metal material to form a metal wiring 18.

Here, in the method for forming the pole speed wiring, a Ti film (not shown) is formed on both side walls and the bottom surface of the contact hole 17 and the oxide film 16 as a first method, and then By heat treatment, the titanium reacts with silicon (Si) of the semiconductor substrate 10 to form a TiSix layer, that is, an ohmic layer. After removing the Ti layer on both sidewalls of the contact hole 17 and the oxide layer 16 that do not react with the semiconductor substrate 10, the contact hole 17 is filled with TiN or TiN / W to form a metal wiring. There is a way.

Second, an ohmic layer is formed by sequentially depositing a Ti film and a TiN film on both side walls and the bottom surface of the contact hole 17, and on the oxide film 16. Next, the contact hole 17 is filled with W to form a metal wiring.

In the third method, a Ti film and a TiN film are sequentially deposited on both side walls and the bottom surface of the contact hole 17, and the oxide film 16, and then tungsten is immediately deposited to form a metal wiring. Then, in the subsequent heat treatment step, the Si and the Ti film of the semiconductor substrate 10 is reacted to form an ohmic layer.

The metal wiring 18 is formed by any of the methods described above.

As described above, when the TiSix layer is used as an ohmic layer, the reaction of the TiSix layer with boron (B) ions doped in the p + impurity region 13 by a heat treatment applied in a subsequent process. TiB layer is formed by this.

Since the TiB layer is a non-conductor, the contact resistance is increased. As the boron ions doped in the p + impurity region 13 are released by the reaction and the doping concentration is lowered, the resistance increases, and the TiSix layer used as the ohmic layer is agglomerated to reduce the surface energy. The problem arises that the effective contact area of the bottom of the hole is reduced and the resistance increases. As or P doped in the n + impurity region does not react with Ti of the TiSix layer.

2A and 2B, when the contact size is A, for example, when the contact size is 0.3 µm or more in diameter, the contact resistance of the n-type impurity region is about 300 Ω / CNT or less, and the p-type impurity region is The contact resistance is about 800 Ω / CNT.

However, if the contact size is reduced to diameter A / 2 and the diameter is about 0.15 탆, as shown in FIGS. 2A and 2B, the increase in contact resistance in the p + impurity region 13 is increased in the n + impurity region 14. It can be seen that it is occurring rapidly compared to the increase in contact resistance.

If a technique for suppressing such a phenomenon is not realized, it is impossible without increasing the chip size unless the target design of the contact resistance in the p-type impurity region is set to 5000 mA / CNT or more. Do.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a semiconductor device and a manufacturing method thereof capable of reducing the resistance of a contact formed in a p-type impurity region without increasing the chip size. have.

1 is a cross-sectional view showing a contact electrode according to a conventional semiconductor device and a method of manufacturing the same;

2A and 2B are diagrams showing distribution of contact resistance according to the size of a contact hole of each conventional impurity region;

3A to 3C and 4A to 4D are flowcharts sequentially showing processes of a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100, 200: semiconductor substrate 101, 201: n-type well

102, 202: p-type well 103, 203: p + impurity region

104, 204: n + impurity regions 106, 206, 210: oxide film

108, 208, 212: mask 109, 207, 213: contact hole

207: plug 108, 212: contact electrode

(Configuration)

According to the present invention for achieving the above object, a method of manufacturing a semiconductor device comprises the steps of: forming a first conductive well and a second conductive well in a semiconductor substrate, respectively; Forming a first impurity region in the first conductivity type well; Forming a second impurity region in the second conductivity type well; Forming an insulating layer on the semiconductor substrate; A contact hole is formed by etching the insulating layer until a portion of the first impurity region and the second impurity region are exposed by using a contact hole forming mask, and the size of the contact hole formed in the first impurity region is formed. And forming a contact larger than a contact hole formed in the second impurity region.

According to the present invention for achieving the above object, a semiconductor device includes a semiconductor substrate; A first conductivity type well formed in the semiconductor substrate; A second conductivity type well formed in the semiconductor substrate adjacent to the first conductivity type well; A first impurity region formed in the first conductivity type well; A second impurity region formed in the second conductivity type well; An insulating film formed on the semiconductor substrate; Contact electrodes formed through the insulating layer and electrically connected to the first impurity region and the second impurity region, respectively, wherein a contact hole formed in the first impurity region has a relatively larger size than a contact hole formed in the second impurity region; Have

According to the present invention for achieving the above object, a method of manufacturing a semiconductor device comprises the steps of: forming a first conductive well and a second conductive well in a semiconductor substrate, respectively; Forming a first impurity region in the first conductivity type well; Forming a second impurity region in the second conductivity type well; Forming an insulating layer on the semiconductor substrate; Etching the insulating layer until a portion of the second impurity region is exposed using a contact hole forming mask to form a first contact hole; Filling the first contact hole with a metal material to form a plug electrically connected to the semiconductor substrate; Forming a second insulating layer on the first insulating layer including the plug; A second contact hole is formed by etching the second insulating layer until a portion of the plug and the first impurity region are exposed using a contact hole forming mask, respectively, and forming a second contact hole in the second impurity region. And forming a relatively larger size of the second contact hole formed in the first impurity region than the size of the hole.

According to the present invention for achieving the above object, a method of manufacturing a semiconductor device comprises the steps of: forming a first conductive well and a second conductive well in a semiconductor substrate, respectively; Forming a first impurity region in the first conductivity type well; Forming a second impurity region in the second conductivity type well; Forming an insulating layer on the semiconductor substrate; Etching the insulating layer until a part of the first impurity region is exposed using a contact hole forming mask to form a first contact hole; Filling the first contact hole with a metal material to form a plug electrically connected to the semiconductor substrate; Forming a second insulating layer on the first insulating layer including the plug; A second contact hole is formed by etching the second insulating layer until a portion of the plug and the second impurity region are exposed using a contact hole forming mask, respectively, and forming a second contact hole in the second impurity region And forming a size of the second contact hole of the first impurity region relatively larger than that of the hole.

According to the present invention for achieving the above object, a semiconductor device includes a semiconductor substrate; A first conductivity type well formed in the semiconductor substrate; A second conductivity type well formed in the semiconductor substrate; A first impurity region formed in the first conductivity type well; A second impurity region formed in the second conductivity type well; A first insulating film formed on the semiconductor substrate; A plug penetrating the first insulating film and electrically connected to the second impurity region; A second insulating film formed on the plug) and the first insulating film; Contact electrodes formed through the second insulating layer and electrically connected to the first impurity region and the plug, respectively, wherein the contact hole formed in the first impurity region has a relatively larger size than the contact hole formed in the second impurity region; .

(Action)

3B and 4D, a novel semiconductor device and a method of manufacturing the same according to an embodiment of the present invention use a mask for forming a contact hole to expose a part of a first impurity region and a second impurity region, respectively. The contact hole is formed by etching the insulating layer. In this case, the size of the contact hole formed in the first impurity region is relatively larger than that of the contact hole formed in the second impurity region. By the semiconductor device and the manufacturing method of the manufacturing method thereof, the size of the contact hole formed in the n-type impurity region is reduced, and the contact hole formed in the p-type impurity region is formed as large as the margin generated therein, thereby providing a chip. It is possible to reduce the contact resistance formed in the p-type impurity region without increasing the size.

(First embodiment)

Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3C.

3A to 3C are flowcharts sequentially illustrating processes of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 3A, in the semiconductor device of the present invention and a method of manufacturing the same, first, an n-type well 101 and a p-type well 102 are formed in the semiconductor substrate 100 using a mask for forming a well.

A p-type impurity region 103 is formed in the n-type well 101 using an impurity region forming mask, and an n + impurity region 104 is formed in the p-type well 102 using an impurity region forming mask. Is formed.

The impurity implanted into the p + impurity region 103 is boron (B), and the impurity implanted into the n + impurity region 104 is any one of an ashen (As) and a phosphorus (P).

Next, in FIG. 3B, an oxide film 106 is formed on the semiconductor substrate 100 as an insulating film. The contact hole 109 is formed by etching the oxide layer 106 until a portion of the n + impurity region 103 and the p + impurity region 104 are respectively exposed using the contact hole forming mask 108.

In this case, the width W1 between the mask 108 for forming the contact hole of the p + impurity region 103 is relatively larger than the width W2 between the mask 108 for forming the contact hole of the n + impurity region 104. (W1〉 W2)

The contact hole 109 has a shape of any one of a circular, elliptical, and other shapes.

Finally, the contact hole 109 is filled with a metal material to form a metal wiring 110 electrically connected to the semiconductor substrate 100 as shown in FIG. 3C. The metal material is any one of tungsten (W) and a TiN film.

Here, in the method for forming the metal wiring 110, a Ti film (not shown) is formed on both side walls and the bottom surface of the contact hole 109 and the oxide film 106 as a first method. Afterwards, the titanium is reacted with silicon (Si) of the semiconductor substrate 100 by a subsequent heat treatment to form a TiSix layer, that is, an ohmic layer. After removing the Ti layer on both sidewalls of the contact hole 109 and the oxide film 106 that do not react with the semiconductor substrate 100, the contact hole 109 is filled with TiN or TiN / W to form a metal wiring. There is a way.

Second, an ohmic layer is formed by sequentially depositing a Ti film and a TiN film on both side walls and the bottom surface of the contact hole 109, and on the oxide film 106. Next, the contact hole 109 is filled with W to form a metal wiring.

In the third method, a Ti film and a TiN film are sequentially deposited on both sidewalls and the bottom surface of the contact hole 109 and the oxide film 106, and then tungsten is immediately deposited to form a metal wiring. Then, in the subsequent heat treatment step, the Si and the Ti film of the semiconductor substrate 100 is reacted to form an ohmic layer.

The metal wiring 110 is formed by any one of the methods described above.

When the TiSix is used as an ohmic layer, a contact hole is formed in the n + impurity region as the size of the contact hole is reduced due to the aggregation action of the TiSix layer during the heat treatment applied in a subsequent process, thereby reducing the effective contact area at the bottom of the contact hole. The increase in resistance shows a gentle value, but the contact resistance formed in the p + impurity region rapidly increases.

Therefore, in order to prevent an increase in contact resistance due to the decrease in contact area as described above, the size of the contact hole 109 formed in the p + impurity region 103 is varied by changing the pattern width of the mask. ) May be formed to be relatively larger than the size W2 'of the contact hole 109 formed in the n + impurity region 104. (W1'> W2 ')

For example, when contact holes of various sizes are formed in the p + impurity region, and contact holes of various sizes are formed in the n + impurity region, or when contact holes of various sizes are formed in only one impurity region, The smallest of the contact holes formed in the p + impurity region is larger than the smallest of the contact holes formed in the n + impurity region.

The increase in chip size may be offset by reducing the contact hole size of the n + impurity region 104.

The size of the contact hole 109 formed in the n + impurity region 104 may be reduced within a range of about 10%. For example, when a contact hole formed in the p + impurity region 103 and the n + impurity region 104 is about 200 nm, the contact hole of the n + impurity region 104 formed according to the embodiment of the present invention is formed. When decreasing to about 170 nm, the contact hole of the p + impurity region 103 may increase to about 230 nm.

The size of the contact hole 109 of the p + impurity region 103 is larger than the size of the contact hole 109 of the n + impurity region 104 within a range of 10%.

Referring to FIG. 3C, the contact hole W1 ′ formed adjacent to the p + impurity region 103 has a larger size than the contact hole W2 ′ formed adjacent to the n + impurity region 104.

Therefore, it is possible to manufacture a semiconductor device capable of reducing the contact resistance of the p + impurity region without increasing the chip size of the semiconductor device.

(Second embodiment)

4A to 4D are cross-sectional views sequentially illustrating processes of a semiconductor device and a method of manufacturing the same according to the second embodiment of the present invention.

Referring to FIG. 4A, in the semiconductor device of the present invention and a method of manufacturing the same, first, n-type wells 201 and p-type wells 202 are formed in the semiconductor substrate 200 using a well-forming mask.

A p-type impurity region 203 is formed in the n-type well 201 using an impurity region forming mask, and an n + impurity region 204 is formed in the p-type well 202.

The impurity implanted into the p + impurity region 203 is boron (B), and the impurity implanted into the n + impurity region 204 is any one of an ashen (As) and a phosphorus (P).

Next, a first oxide film 206 is formed on the semiconductor substrate 200. The first contact hole 207 is etched by etching the first oxide film 206 until a portion of the n + impurity region 204 is exposed using the contact hole forming mask 208. Is formed.

Referring to FIG. 4C, when the first contact hole 207 is filled with a metal material, a plug 209 electrically connected to the semiconductor substrate 200 is formed. The metal material is any one of tungsten (W) and a TiN film.

A second oxide film 210 is formed on the first oxide film 206 including the plug 209 and has a flat upper surface as an insulating film. The second contact hole 213 is formed by etching the second oxide film 210 until the plug 209 and a part of the p + impurity region 203 are exposed using the contact hole forming mask 212. .

In this case, the width W1 between the masks 208 for forming the contact holes of the p + impurity region 103 is relatively larger than the width W2 between the masks 208 for forming the first contact holes.

Therefore, the size W1 ′ of the second contact hole 213 of the P + impurity region 203 is relatively larger than the size W2 ′ of the first contact hole 207 formed in the n + impurity region 204. Is formed larger (W1 '> W2').

Meanwhile, a first contact hole 207 'is formed in the p + impurity region 203 to form a plug 208', and a second contact hole 211 in the plug 208 'and the n + impurity region 204. ') Is also possible (not shown).

That is, the size W1 ′ of the first contact hole 207 ′ of the p + impurity region 203 is also larger than the size W2 ′ of the contact hole 213 ′ of the n + impurity region 204. (W1 '> W2')

As described in the first embodiment, the contact hole size of the n + impurity region 204 may be reduced to within 10%, and the contact hole size of the p + impurity region 203 may be increased by the margin. .

Finally, the second contact hole 211 ′ is filled with a metal material to form a contact electrode 212 as shown in FIG. 4D. The metal material is the same material as that of the plug 209 forming material.

Referring to FIG. 4D, the contact hole W1 ′ formed in the p + impurity region 203 has a larger size than the contact hole W2 ′ formed in the n + impurity region 204.

The present invention reduces the size of the contact hole formed in the n-type impurity region, and increases the contact hole formed in the p-type impurity region by the margin generated therein, thereby forming the p-type impurity region without increasing the chip size. There is an effect that can reduce the contact resistance.

Claims (9)

Forming first conductive wells (101) and second conductive wells (102) in the semiconductor substrate (100), respectively; Forming a first impurity region (103) in the first conductivity type well (101); Forming a second impurity region (104) in said second conductivity type well (102); Forming an insulating layer (106) on the semiconductor substrate (100); A contact hole 109 is formed by etching the insulating layer 106 until a portion of the first impurity region 103 and the second impurity region 104 are exposed using a contact hole forming mask, respectively. Forming the contact hole 109 formed in the first impurity region 103 to be larger than the size of the contact hole 109 formed in the second impurity region 104. Manufacturing method. The method of claim 1, The first conductive well (101) is an n-type well, and the second conductive well (102) is a p-type well. The method of claim 1, And the first impurity region (103) is p-type and the second impurity region (104) is n-type. The method of claim 1, The impurity doped in the first impurity region 103 is boron (B), and the impurity doped in the second impurity region 104 is any one of an ashen (As) and a phosphorus (P). Manufacturing method. The method of claim 1, And the first impurity region has a size larger than the second impurity region by 10% or more. A semiconductor substrate 100; A first conductivity type well (101) formed in the semiconductor substrate (100); A second conductivity type well (102) formed in the semiconductor substrate (100); A first impurity region (103) formed in the first conductivity type well (101); A second impurity region (104) formed in said second conductivity type well (102); An insulating film (106) formed on the semiconductor substrate (100); Contact electrodes 110 penetrating the insulating layer 106 and electrically connected to the first impurity region 103 and the second impurity region 104, respectively. And a contact hole (W1 ') formed in the first impurity region (103) is relatively larger than a contact hole (W2') formed in the second impurity region (104). Forming first conductive wells (101) and second conductive wells (102) in the semiconductor substrate (100), respectively; Forming a first impurity region (103) in the first conductivity type well (101); Forming a second impurity region (104) in said second conductivity type well (102); Forming an insulating layer (206) on the semiconductor substrate (200); Etching the insulating layer 206 to form a first contact hole 207 until a portion of the second impurity region 204 is exposed using a contact hole forming mask; Filling the first contact hole (207) with a metal material to form a plug (208) electrically connected to the semiconductor substrate (200); Forming a second insulating layer (210) on the first insulating layer (206) including the plug (208); A second contact hole 211 is formed by etching the second insulating layer 203 until a portion of the plug 208 and the first impurity region 203 are exposed using a contact hole forming mask, respectively. Forming a relatively larger size of the second contact hole 211 formed in the first impurity region 203 than the size of the first contact hole 207 formed in the second impurity region 204. Method for manufacturing a semiconductor device comprising a. Forming first conductive wells (101) and second conductive wells (102) in the semiconductor substrate (100), respectively; Forming a first impurity region (103) in the first conductivity type well (101); Forming a second impurity region (104) in said second conductivity type well (102); Forming an insulating layer (206) on the semiconductor substrate (200); Etching the insulating layer 206 to form a first contact hole 207 'until a portion of the first impurity region 203 is exposed using a contact hole forming mask; Filling the first contact hole (207 ') with a metal material to form a plug (208') electrically connected to the semiconductor substrate (200); Forming a second insulating layer (210) on the first insulating layer (206) including the plug (208 '); A second contact hole 211 'is etched by etching the second insulating layer 210 until a portion of the plug 208' and the second impurity region 204 are respectively exposed using a contact hole forming mask. Form a second contact hole 207 'of the first impurity region 203 to a size larger than that of the second contact hole 211' formed in the second impurity region 204. A manufacturing method of a semiconductor device comprising the step of. A semiconductor substrate 200; A first conductivity type well 201 formed in the semiconductor substrate 200; A second conductivity type well 202 formed in the semiconductor substrate 200; A first impurity region (203) formed in the first conductivity type well (201); A second impurity region (204) formed in the second conductivity type well (202); A first insulating film 206 formed on the semiconductor substrate 200; A plug 209 penetrating the first insulating film 206 and electrically connected to the second impurity region 204; A second insulating film 210 formed on the plug 209 and the first insulating film 206; Contact electrodes 214 that penetrate the second insulating film 210 and are electrically connected to the first impurity region 203 and the plug 209, respectively. And a contact hole (W1 ') formed in the first impurity region (203) is larger than a contact hole (W2') formed in the second impurity region (204).