JP3040960B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device incorporating an electrode comprising a polysilicon layer covered by a self-aligned metal silicide layer.

[0002]

2. Description of the Related Art In semiconductor devices, as line widths become narrower and geometries become smaller, the polysilicon electrodes forming the gates of MOS devices and the wiring lines within the semiconductor devices have an undesirably high resistance. Become. In order to obtain an electrode having a lower resistance than an electrode consisting of polysilicon only, multilayer electrodes are used in which the polysilicon layer is covered by one or more metal or metal silicide layers. The silicide electrode may be, for example, about 1000 to 3000 mm thick coated with titanium silicide to a thickness greater than 100 degrees.
Of the polysilicon layer.

A typical example of such a multilayer electrode is a so-called self-aligned silicide structure, which is shown in FIGS.
4 is shown in an idealized form. 1 to 4 show cross-sectional views of a MOS device in an initial manufacturing stage. M shown
The OS device is formed on a P-type substrate 10, has a thick field oxide region 12, and is adjacent to another MO device.
Separated from S devices. A gate oxide layer 14 formed by thermal oxidation covers the active device area of the device shown, on which a polysilicon gate electrode 16 is formed. The polysilicon gate electrode 16 is formed by depositing an undoped polysilicon layer on the substrate, for example, by low pressure chemical vapor deposition (LPC).
VD) by depositing and activating the polysilicon layer using a method, rendering the polysilicon layer conductive, and then patterning the polysilicon layer using photolithography. ,It is formed.
On the field oxide region 12, a polysilicon wiring line 18 is formed simultaneously with the gate electrode 16.

[0004] Doped source / drain regions 20 are formed on both sides of the polysilicon gate electrode and are shown in FIG.
Defining a channel region for the OS transistor. In general, lightly doped drain (LDD) structures are used for MOS transistors based on small design rules of the type primarily used in modern memory and logic devices. LDD source / drain regions 20 are typically formed in a two-step process, with a relatively low level of dopant implantation to self-align to polysilicon gate electrode 16 as shown in FIG.
Thereafter, a gate oxide 16 is deposited by first depositing a CVD oxide layer on the structure of FIG. 1 and then performing an anisotropic etchback on the oxide layer to expose the substrate over source / drain regions 20. Spacer oxide regions 2 on both sides of
2 (FIG. 2). Etching back the CVD oxide layer creates spacer oxide regions 22 on both sides of the polysilicon gate electrode 16. The method also creates spacer regions 24 on both sides of the polysilicon interconnect line 18 if the polysilicon interconnect line 18 is exposed during the oxide deposition and etchback process. After the spacer oxide regions 22 have been created on both sides of the polysilicon gate electrode 16, a second stronger ion implant is performed in the source / drain regions 20 to self-align with the spacer oxide regions 22 (not shown).

The structure shown in FIG. 2 has a polysilicon gate electrode 16 and a polysilicon wiring line 18. If the line width is narrower, the signal level decreases and RC
Because of the longer time constant, even highly doped polysilicon has a large enough resistance to degrade the performance of the MOS circuit. To reduce the resistance of these gate electrodes and wiring lines, the processing of the device of FIG. 2 is further continued using the self-aligned silicide (ie, salicide) technique to continue the gate electrode 1
6 and wiring lines 18 are converted to silicide structures.
It is known that a variety of different silicides can be used, the most commonly used silicide being titanium silicide, which will be described below. In FIG. 3, first, for example, 5
A silicide line is formed by sputtering a titanium layer to a thickness of 00 °. This titanium layer 26
At the exposed portions of the substrate, including the surfaces of the polysilicon layers 16 and 18 and the source / drain regions 20, they are converted to titanium silicide in a two step process.

In the first processing step, the device is
The device is subjected to a rapid thermal anneal (RTA) treatment by heating to a temperature of up to
Is converted to titanium silicide (nominal TiSi ₂ ) where the titanium layer is in contact with the surface of silicon (crystalline or polycrystalline silicon). The resulting device is then etched using a liquid etchant consisting of H ₂ O ₂ and NH ₄ OH diluted with water to remove unreacted titanium from the surface of the device and remove the oxide of the device. Expose the area. Polysilicon gate electrode 16
And the wiring lines 18 remain, respectively, with titanium silicide layers 30 and 32. If the source / drain region 20 is exposed during the silicidation process, a titanium silicide region 34 is also formed on the source / drain region 20.
Such a titanium silicide region 34 forms a low sheet resistance over the source / drain region 20 and provides a better contact to the source / drain region 20. Therefore, a titanium silicide contact is preferred on the source / drain region 20 unless the silicon consumption during the silicidation process alters the gate performance or the junction leakage in the source / drain region 20 is not unduly large.

After the unreacted titanium has been etched away from the resulting device, further processing must be performed to form a suitable self-aligned silicide (ie, salicide) structure on the gate electrodes and wiring lines of the device. The process described so far forms a titanium silicide phase with a relatively high resistivity on the silicon surface,
The silicide structures shown do not have the desired low resistivity. Therefore, the resulting device must be subjected to a second rapid thermal anneal at a temperature greater than 800 ° C. for at least 10 seconds to convert the titanium silicide to a low resistivity titanium silicide phase. The resulting device is then further processed to complete device fabrication.

Some of the processing steps required to form a silicide structure are rigorous. For example, if the temperature control is insufficient for the first RTA step to convert titanium in contact with silicon to titanium silicide, the device temperature can be increased laterally along the titanium layer (26 in FIG. 3). Can be brought to a high enough temperature to be transferred quickly, which can convert titanium to titanium silicide in undesirable areas. For example, if silicon is transported along the portion of the titanium layer that extends over the oxide spacers 22 on both sides of the gate electrode 16, a “stringer” that bridges between the gate electrode and the source / drain regions 20. (striner) "may be formed. Such a stringer 36 that bridges between the gate silicide layer 30 and the source / drain silicide regions 34 is shown in FIG. The formation of the structure of FIG. 5 is clearly undesirable because it shorts the gate region to the source / drain regions and renders the transistor inactive.

[0009]

If the device geometry is small, the gate electrodes and wiring lines will be narrow, so that the memory and logic devices may have
It is increasingly necessary to form gate electrodes and wiring lines with sufficiently low resistivity. On the other hand, the narrower the gate electrode and the wiring line, the more difficult it is to form a suitable salicide electrode structure. In particular, in the case of a gate electrode and a wiring line having a small line width, it is difficult to form a titanium silicide phase having a low specific resistance.
Therefore, it is desirable to develop better designs and more reliable processing techniques for forming low resistivity silicide structures.

[0010]

SUMMARY OF THE INVENTION The present invention provides, in a first aspect, a semiconductor circuit having a MOS device incorporating a wiring line and a gate electrode.
The MOS device is formed on a semiconductor substrate. Both the wiring line and the gate electrode have a silicide structure, wherein the silicide structure is located on the lower polysiloxane layer having a sidewall, and the lower polysiloxane layer. Have a metal silicide layer extending laterally beyond each of the sidewalls.

According to another aspect of the present invention, a semiconductor substrate, an insulating material layer on the semiconductor substrate, and two side walls extending above the semiconductor substrate are provided on the insulating material layer. A semiconductor circuit comprising a polysilicon structure formed in the semiconductor device. A conductive material layer is formed on the polysilicon structure so as to extend laterally beyond both side walls of the polysilicon structure.

The present invention provides, in a third aspect thereof, a semiconductor circuit comprising a semiconductor substrate and a layer of insulating material over the semiconductor substrate. A polysilicon structure is formed on the insulating material layer so as to have two side walls extending above the semiconductor substrate. A layer of conductive material extends laterally over the polysilicon structure beyond the sidewalls of the polysilicon structure. A first lightly doped region having a boundary adjacent to a lower edge of a first side wall of the side walls of the polysilicon structure, and a first edge of the conductive material layer in the semiconductor substrate; A first LDD source / drain region having a first heavily doped region having a boundary formed in self-aligned manner.

According to a fourth aspect of the present invention, a MOS
Provided is a method of manufacturing a semiconductor device comprising a transistor, the method comprising forming an insulator over a semiconductor substrate, and having a protrusion extending laterally above the semiconductor substrate. Forming the formed polysilicon electrode on the insulator. Further, the method uses the shaped polysilicon electrode protrusion as an ion implantation mask to define a dopant distribution in the LDD source / drain regions. Forming LDD source / drain regions in the semiconductor substrate by ion implantation, and forming a metal silicide layer on the shaped polysilicon electrode.

In a particularly preferred example of the fourth aspect of the present invention described above, the step of forming the shaped polysilicon structure comprises: depositing a first layer of mask material over the semiconductor device; Depositing a second mask material layer over the mask material layer; and forming an opening by removing a portion of the first and second mask material layers. The second mask material layer is laterally etched such that the openings in the second mask material layer are larger than the openings in the first mask material layer. Polysilicon is deposited in the opening and the first and second mask material layers are removed.

[0015] In a fifth aspect, the present invention provides a method of manufacturing a semiconductor device, the method comprising providing a semiconductor substrate, and then providing a layer of insulating material over at least a portion of the semiconductor substrate. A shaped polysilicon structure having a protrusion extending laterally above a surface of the semiconductor substrate is formed on the insulating material layer. A metal layer is deposited over the shaped polysilicon structure and the semiconductor device is annealed to produce a metal silicide layer over the shaped polysilicon structure.

In a preferred embodiment of the present invention, a semiconductor device incorporating a salicide (self-aligned silicide) structure is preferably fabricated in such a way that no oxide spacer structure is formed near the polysilicon gate electrode and the wiring line. Form. Form a shaped polysilicon gate electrode having an upper surface that can be converted to a silicide, such as titanium silicide. The shaped polysilicon electrode preferably has a protrusion extending in a direction away from the electrode body and extending above the silicon substrate. This polysilicon gate electrode can have, for example, a "t" -shaped cross section. First, low dopant level ion implantation is performed at an angle such that it reaches the substrate region that is shadowed by the protrusion from the gate electrode.
Light ion implantation suitable for the source / drain regions can be performed.

Next, high dopant level ion implantation is performed using an implantation direction perpendicular to the substrate surface such that the protrusion extending from the gate electrode acts as a mask for high dopant level ion implantation, This ion implantation completes the source / drain structure. In this way, the lightly doped drain (LD) is used for both source / drain regions without using a spacer oxide.
D) type structures can be formed. Gate electrodes and wiring lines having this structure are more reliably of high quality and generally have lower resistivity than gate electrodes and wiring lines formed using conventional salicide techniques.

We have observed that the observed improvement in salicide electrode and interconnect line formation and performance achieved by using the preferred embodiment of the present invention is that the silicide layer of the gate electrode has a low level of stress. It is considered to be related to the formation of a salicide structure so as to grow so as to have. When fabricating these structures using polysilicon lines less than 0.5 microns wide, it becomes increasingly difficult to form salicide electrodes and wiring lines having an acceptable low resistivity. In particular,
When the line width is less than 0.05 μm, the specific resistance of the gate electrode and the wiring line sharply increases. The increase in resistivity for narrower line widths can be attributed to the second resistivity conventionally used to produce low resistivity silicide layers.
The result is that the anneal step may be ineffective for such narrow line widths. To understand why this happens, it is useful to consider a more realistic model of what happens during the formation of a conventional salicide structure.

FIG. 6 illustrates that it is difficult to convert a silicide layer formed on a polysilicon layer having a small line width into a silicide layer having a low specific resistance. FIG. 4 described above shows a well-defined titanium silicide layer that extends uniformly across the polysilicon gate electrode. This idealizes what happens during a rapid thermal anneal that converts titanium in contact with the silicon layer to a titanium silicide layer. The present inventors have realized that the titanium silicide structure 3 shown in FIG.
It was observed that 8 was formed more typically. Near the edge of the polysilicon gate electrode, the gate oxide spacer 22 "clamps" the edge of the titanium silicide layer 38.
p) "and, in a typical example, appear to be constraining the growth of titanium silicide layers that need to be extended to a greater thickness than the silicon layer consumed during the growth process.

As described above, since titanium silicide grows most freely near the center of the gate electrode, the thickest portion of the titanium silicide layer 38 is formed above the center of the polysilicon gate electrode 16. The portion of titanium silicide along the edges of titanium silicide layer 38 has a high level of stress as formed, while the portion of titanium silicide near the center experiences a relatively low level of stress. Have. Titanium silicide layer 38
Is sufficiently narrow, there is considerable stress even at the center of the titanium silicide layer 38. If too high a level of stress is present in the entire titanium silicide layer as formed, the subsequent annealing step will not successfully convert the titanium silicide layer 38 to a low resistivity phase. Sometimes. Thus, a salicide structure in which the as-grown silicide phase has too high a level of stress can result in an undesirably high resistance salicide structure, such a salicide structure having a gate electrode or interconnect structure. Not very suitable for use as a line.

Accordingly, the present inventors believe that it is desirable to form a salicide structure using a low stress level silicide layer, at least when the line width is narrow.
Hereinafter, a salicide structure formed by incorporating a silicide layer having a low stress and a preferred method of manufacturing the structure will be described with reference to FIGS. 7-15 show particularly preferred embodiments of the present invention comprising MOS transistors and wiring lines in certain shaped semiconductor devices, these examples of the present invention being used in a wide variety of semiconductor devices. It can be used to form wiring lines.

Furthermore, although the following description of the present invention focuses on NMOS devices, the salicide structure according to the present invention can be used to advantage for PMOS devices as well. This is true whether the polysilicon of the PMOS gate is doped N-type or P-type. Although the salicide structure described here can be used only for the gate electrode of the device (or, conversely, only for the wiring lines), the salicide structure described here can be used for all first level polysilicon lines, Most desirably, it is used for devices where at least highly conductive electrodes and wiring lines are desired.

FIG. 7 shows the MO in the initial stage of the manufacturing method.
2 shows a cross section of a small portion of a semiconductor circuit incorporating an S device. A P-type substrate 10 is provided and, if necessary, device isolation regions such as field oxide regions 12. Pad oxide 40 is thermally grown or deposited by chemical vapor deposition (CVD) to a thickness of about 50-300 ° on the active device area of the device. Then, for example, using boron or boron fluoride for NMOS devices or arsenic or phosphorus ions for PMOS devices, for example, about 5 to 50 KeV
Energy of about 3 × 10 ¹¹ / cm ² to about 5 × 10 ¹³
Channel-limited adjustment implants are performed in a conventional manner up to a dose of ions / cm ² . Next, a series of material layers are deposited over at least the area of the device where the salicide gate structure and wiring lines are to be formed.

The series of material layers are patterned into a form or mask structure used in forming the shaped polysilicon lines, and the shaped polysilicon lines are subjected to further processing. Form a salicide structure. Thus, using various different combinations of layers,
A desired form, that is, a mask structure can be obtained. In a preferred embodiment, a silicon nitride Si ₃ N ₄ layer 42 is deposited first, followed by a silicon oxide SiO ₂ layer 44, followed by a second silicon nitride layer 46. Any of these layers can be deposited using one of the conventional CVD methods well known in the art, and each of these layers is about 1000-3000 thick.
Preferably, the total thickness of these layers is about 3000 °, but this total thickness can be easily varied to form various thicknesses of salicide structures.

After depositing the layers 42, 44, 46 formed in polysilicon form, photolithography is performed to form openings through these three layers in the region where the salicide structure is to be formed. Is provided. In this photolithography, a mask that is the reverse of the conventional first polysilicon mask pattern can be used, so that after exposing and removing the photoresist, the opening through the photoresist forms a salicide structure The layer 46 is left exposed over the area to be intended. Then, for example, the Si ₃ N ₄ layers 46 and 42
Of using the bra Zuma etching with SF ₆ and He in the case, when the SiO ₂ layer 44 is CHF ₃ and O
_{Using 2} , layers 42, 44 and 46 are substantially anisotropically etched. After removing the photoresist,
A device as shown in FIG. 8 results, having an opening 48 above the active device region and an opening 50 above the field oxide region 12. The device is then diluted with a dilute HF solution (eg, HF: H ₂ O = 1: 10).
Immersion for about 2 minutes to about 7 minutes to provide an intermediate S
The iO ₂ layer 44 is laterally etched.

As a result, in the opening 48, the silicon oxide layer 4
4, an undercut 52 is formed in the lateral direction, and an undercut 54 is formed in the silicon oxide layer 44 in the opening 50 in the lateral direction. Also, as a result of the undercut etching, the pad oxide 40 is removed at the portion exposed to the diluted HF solution, and a slight undercut is formed below the silicon nitride layer 42. The extent of undercut of the silicon oxide layer 44 determines the degree of protrusion of the polysilicon projection relative to this shaped polysilicon structure to be formed. Therefore, as described in detail below, the LDD of the device depends on the range of the undercut.
The position of the edge of the heavily doped portion of the source / drain region is determined. Thus, the range of the undercut can be desirably adjusted according to the particular structure desired for the source / drain regions. Undercut 5
A preferred range of 2,54 is from about 500 ° to about 2000 °.

After performing the undercut etching,
The substrate 10 is exposed in the opening 48. The gate oxide layer 56 (FIG. 10) is then thermally grown to a thickness of about 30 ° to about 300 ° in a conventional manner. Polysilicon is deposited by a CVD method to a depth sufficient to extend above first layer 42, more preferably above layer 44. The thickness of the polysilicon layer is typically the combined thickness of approximately three layers 42, 44 and 46. The polysilicon is formed in the undercut regions 52 and 54 by the CVD method.
It is easily deposited in (FIG. 9) to form shaped polysilicon structures 58, 60 as shown in FIG. CVD
Preferably, the polysilicon structure is doped in situ during deposition by adding appropriate dopants during processing, or the polysilicon structure is preferably doped later by ion implantation. Then, for the Si ₃ N ₄ layers 46 and 42, hot H ₃ PO
₄ and dilute HF (in H ₂ O) for the SiO ₂ layer 44
The stacked layers 42, 44 and 46 are removed using a conventional etchant such as a solution to obtain the structure shown in FIG.

Next, anti-punch through ion implantation is performed to form lightly doped portions of the source / drain regions. These ions are implanted during the ion implantation at an oblique angle, with the protrusions 6 extending from the polysilicon electrode 58.
2 is used as a mask, and the alignment is performed. The implantation angle is determined by the length of the protruding portion 62 extending above the surface of the substrate 10 and the ion implantation by the polysilicon electrode 58.
It is easily determined by the angle required to have a "line of sight" with respect to the base. In a typical example,
The injection angle is between about 15 ° and about 60 °. In a well-known manner, boron, boron fluoride, arsenic or phosphorus ions are converted to about 5 × 10 ¹² at an energy of about 5 to 80 KeV.
An anti-punch-through ion implant 64 and a lightly doped drain implant 66 are performed by implanting up to a dose of ions per cm ² to about 2 × 10 ¹⁴ ions / cm ² . FIG. 12 shows the generated structure.

Next, the protrusion 62 extending from the polysilicon electrode 58 is used as a mask for intensity injection, and is vertically (ie, not tilted) implanted into the substrate surface, so that the intensity of the source / drain region is increased. To form a doped portion. The heavily doped region is determined by the location where the "shadow" of the protrusion 62 falls on the substrate, so that the heavily doped region (6 in FIG. 13).
8) is formed to be self-aligned with the protrusion. In a typical example, boron, boron fluoride, arsenic, antimony or phosphorus ions are converted to an energy of about 5-200 KeV for about 1 hour.
A highly doped region is formed by implanting ions up to a dose of about 10 ¹⁴ ions / cm ² to about 1 × 10 ¹⁶ ions / cm ² . The resulting device is then heated to about 800 ° C.-1
10 seconds at a temperature of 100 ° C (RTA, relatively high temperature)
Heating for 60 minutes (relatively low temperature) activates the source / drain regions.

Next, a silicide portion of the salicide structure is formed. As is known in the art, several different base metals can be used to form an acceptable silicide layer, including titanium, cobalt, nickel, platinum and palladium. At this time, titanium silicide is the most widely used, but cobalt silicide and nickel silicide are believed to have desirable properties for narrow linewidth devices. The processing steps specific to each of these various silicides are well known and have been reported in the literature. Thus, although the following description is for titanium silicide, other silicides can be used in this process as is known in the art.

After thermal activation of the dopant, the device shown in FIG. 13 is obtained. Formed by this process (heat)
The oxide is removed using a dilute HF solution, and then a thin layer of the metal to be silicided is deposited over the device using a physical vapor deposition (eg, sputtering) method. In the example shown, titanium is deposited to a thickness of about 200-800 ° to create a thin layer 70 on the surface of the device, as shown in FIG. The thickness of the metal deposited depends on the need to deposit a sufficient amount of titanium to form a uniform layer, using a sufficient amount of metal to produce the desired conductive titanium silicide layer; The need to leave a sufficient amount of silicon under the silicified structure is determined by balancing. Excessive silicon consumption during silicidation can result, inter alia, in unacceptable junction leakage from the source / drain regions. As shown in FIG. 14, in a region where the substrate is shaded by the protruding portion 62 from the polysilicon electrode 58, the metal coating is insufficient.

The discontinuity in the metal layer 70 adjacent to the gate electrode ensures that no bridging (as shown in FIG. 5) occurs. Therefore, the initial silicidation can be performed at a high enough temperature to produce a titanium silicide phase with low resistivity. Thus, titanium silicide can be formed by rapid thermal annealing (RTA) of the device of FIG. 14 at a temperature of about 750 ° C. for about 20 seconds. Next, unreacted titanium is removed by etching. However, during this process, a significant amount of silicon was added to the titanium layer 70.
Along with the resulting undesirable formation of titanium silicide stringers extending over portions of the device. Thus, silicification may be preferably performed in a two-step process. Independently, the presence of discontinuities in the sputtered titanium layer reduces the importance of temperature and other control factors to the processing steps in a two-step process.

The structure of FIG. 14 includes a first RTA under a nitrogen atmosphere, preferably in the range of 600-750 ° C., more preferably at a temperature of about 700 ° C., preferably 10-12 ° C.
It is applied for 0 second, more preferably for 20 to 60 seconds. In the case of cobalt silicide, about 500-60
Preferably, a temperature of 0 ° C. is used. Next, from the surface of the device, titanium nitride, titanium-enriched titanium silicide, titanium oxide, and unreacted titanium were subjected to NH ₄ OH, H ₂ O ₂
And in a solution of H ₂ O (eg, in a ratio of 1: 1: 5), leaving a titanium silicide layer 72 over the heavily doped portion 68 of the source / drain regions. Also, the titanium silicide regions 74 and 76 remain on the polysilicon portion 58 of the gate electrode and on the polysilicon portion 60 of the wiring line. The remaining titanium silicide is then reduced to a temperature in the range of about 700C to 900C for about 10-6.
By performing RTA for 0 seconds, the phase is converted to a phase having a low specific resistance. The second RTA is about 20 minutes at a temperature of about 850 ° C.
Most preferably, it takes place for seconds.

In this example, the titanium silicide regions 74 and 76
Are less constrained than in the conventional salicide method. Ideally, titanium silicide is essentially unconstrained in the vertical direction because there is no spacer oxide to vertically compress the titanium silicide in areas where silicon is consumed. Therefore, the titanium silicide regions 74 and 76
It is formed at significantly lower stress levels than occurs with conventional silicidation methods (shown in FIGS. 1-4). Due to the mismatch between the titanium silicide layer and the underlying (unconsumed) silicon layer,
Although stress is introduced into the titanium silicide layer along the horizontal direction, the resulting structure has a significantly lower stress level after the initial silicidation than in a conventional salicide treatment.
Thus, the second RTA also significantly improves the possibility of converting titanium silicide to a preferred phase with low resistivity. The titanium silicide structures 74 and 76 have a width substantially equal to the width of the silicon protrusion 62 existing before the silicidation process (ie, about 500 mm).
{Approximately 2000}).

In the next process, the atmospheric pressure CV
DSiO ₂ or borophosphosil glass
An interpolysilicon layer such as icate glass (BPSG) or a pre-metal dielectric layer is deposited on the structure of FIG. Therefore, in a typical example, CV
DSiO ₂ or BPSG is a polysilicon electrode 58
(Between the protruding portion of the silicide layer 74 and the substrate 10) and adjacent to the lower layer.
0 (between the protrusion of the silicide 76 and the field oxide 12). If necessary,
CVD SiO ₂ or BPSG the through downward to form a passage (Via) extending to a silicide region, polysilicon or metal contact, and the wiring lines and interconnects of the first metal or the second polysilicon Form. The rest of the structure and processing are the same as in the prior art, and a description thereof will be omitted. The shape of the gate electrodes, wiring lines and silicified regions of the substrate may, in some cases, have an additional layer of conductive material such as a refractory metal or metal nitride formed on top of the salicide structure. May be.

The invention has been described with reference to certain preferred embodiments. However, the invention is not limited to the specific examples described herein,
It is intended to cover such modifications as fall within the scope of the claims.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a first stage of a processing step of manufacturing a salicide structure by a conventional method.

FIG. 2 is an explanatory view showing a second stage of a processing step of manufacturing a salicide structure by a conventional method.

FIG. 3 is an explanatory view showing a third stage of a processing step of manufacturing a salicide structure by a conventional method.

FIG. 4 is an explanatory view showing a fourth stage of a processing step of manufacturing a salicide structure by a conventional method.

FIG. 5 is an explanatory diagram showing a stringer formed on a transistor and short-circuiting a gate of the transistor to a drain.

FIG. 6 is an explanatory diagram showing difficult points in manufacturing an acceptable salicide structure.

FIG. 7 is an explanatory view showing a first stage of a manufacturing process for manufacturing a MOS device incorporating a salicide structure according to the method of the present invention.

FIG. 8 is an explanatory view showing a second stage of a manufacturing process for manufacturing a MOS device incorporating a salicide structure according to the method of the present invention.

FIG. 9 is an explanatory view showing a third stage of the manufacturing process for manufacturing a MOS device incorporating a salicide structure according to the method of the present invention.

FIG. 10 is an explanatory view showing a fourth step of the manufacturing process for manufacturing the MOS device incorporating the salicide structure according to the method of the present invention.

FIG. 11 is an explanatory view showing a fifth step of the manufacturing process for manufacturing the MOS device incorporating the salicide structure according to the method of the present invention.

FIG. 12 is an explanatory view showing a sixth step of the manufacturing process for manufacturing the MOS device incorporating the salicide structure according to the method of the present invention.

FIG. 13 is an explanatory view showing a seventh step in the manufacturing process for manufacturing the MOS device incorporating the salicide structure according to the method of the present invention.

FIG. 14 is an explanatory view showing an eighth step of the manufacturing process for manufacturing the MOS device incorporating the salicide structure according to the method of the present invention.

FIG. 15 is an explanatory view showing a ninth stage of the manufacturing process for manufacturing the MOS device incorporating the salicide structure according to the method of the present invention.

[Explanation of symbols]

10 P-type substrate 12 Field oxide region 14 Gate oxide layer 16 Polysilicon gate electrode 18 Polysilicon wiring line 20 Doped source / drain region (LDD source / drain region) 22 Spacer oxide region (Gate oxide spacer) 24 Spacer region 26 Titanium layer 30 Titanium silicide layer (gate silicide layer) 32 Titanium silicide layer 34 Titanium silicide region (source / drain silicide region) 36 Stringer 38 Titanium silicide structure 40 Pad oxide 42 Silicon nitride Si ₃ N ₄ layer (first layer) 44 Silicon oxide SiO ₂ layer 46 Second silicon nitride Si ₃ N ₄ layer 48 Opening 50 Opening 52 Undercut (undercut area) 54 Undercut (undercut area) 56 Gate oxide layer 58 , 60 Shaped polysilicon structure (polysilicon electrode, polysilicon part) 62 Protrusion 64 Anti-anti Ruion injected 66 doped drain implant 68 intensities lightly doped region (doped portion strength) 70 thin layer (metal layer, a titanium layer) 72 titanium silicide layer 74 titanium silicide region

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-26133 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/28 301 H01L 21 / 3205 H01L 21/336

Claims (7)

(57) [Claims] In manufacturing a semiconductor device including a MOS transistor, an insulator is formed on a semiconductor substrate; a first mask material layer is deposited on the insulator;
Depositing a second mask material layer over the mask material layer; forming an opening by removing a portion of the first and second mask material layers; laterally etching the second mask material layer Making the openings in the second mask material layer wider than the openings in the first mask material layer; depositing polysilicon in the openings; removing the first and second mask material layers to remove the semiconductor substrate. Forming a shaped polysilicon electrode with protrusions extending laterally above the insulator; as an ion implantation mask for defining dopant distribution in LDD source / drain regions Using the protrusions of the shaped polysilicon electrode, on both sides of the shaped polysilicon electrode, in the semiconductor substrate,
Forming a LDD source / drain region by ion implantation; and forming the MOS transistor by forming a metal silicide layer on the shaped polysilicon electrode. 2. The method of claim 1, wherein a third layer of mask material is deposited over the second layer of mask material prior to the step of forming the opening. 3. The method of claim 2, wherein said first and second mask material layers are formed from the same material. 4. The method of claim 3, wherein said second mask material layer contains silicon oxide. 5. The method according to claim 2, wherein the polysilicon is deposited by chemical vapor deposition and is doped in place. 6. The step of forming a metal silicide layer, comprising: depositing a metal layer on the resulting semiconductor device; annealing the semiconductor device to form a metal silicide on the shaped polysilicon electrode. The method of claim 1 wherein said forming comprises etching away unreacted metal from said semiconductor device. 7. The metal to be deposited is titanium, cobalt,
7. The method of claim 6, wherein the method is selected from the group consisting of nickel platinum and palladium.