JP2000030492A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which is not influenced by wiring delay, etc., in a semiconductor chip, and also permits to measure the characteristic of an access time measuring circuit of the memory from the outside of the semiconductor chip. SOLUTION: A data output DO of a memory circuit 1 is inputted to a flip-fop circuit 2. The output signal, TDO of the flip-flop circuit 2 is led to an signal output terminal outside of a semiconductor chip. The memory circuit 1 operates reading synchronizing with the memory clock signal CLK, while the memory clock signal CLK passes through a selection circuit 3 and a delay circuit 4 and controls signal holding operation of the flip-flop circuit 2 as a holding clock signal TCK for the flip-flop circuit 2. The delay circuit 4 can vary a delay time from the outside of the semiconductor chip. Further, the holding clock signal TCK of the flip-flop circuit 2 is inputted to another side of the selection circuit 3, and the selection circuit 3 and the delay circuit 4 operate as an oscillation circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to a semiconductor integrated circuit having a memory circuit and capable of measuring an access time of the memory circuit.

[0002]

2. Description of the Related Art With the recent increase in the scale of semiconductor integrated circuits, multifunctionality, and high performance, RAM, R
Devices with built-in memory functions such as OM have become common. Further, the operation delay time of a semiconductor integrated circuit may vary greatly due to process variations and the like.

[0003] Therefore, it is required to accurately test the variation of the operation delay amount of the built-in memory. However, as the speed of the built-in memory increases, it becomes difficult to measure the delay time. Traditionally, to perform this type of measurement,
For example, Japanese Patent Application Laid-Open No. 6-27205 describes a test technique in which a signal synchronized with an input signal to a memory is generated in a semiconductor chip, and a circuit for holding an output signal based on the signal is provided.

FIG. 6 is a block diagram showing an example of a conventional memory access time measuring circuit. The holding clock signal T of the flip-flop circuit 12 (hereinafter referred to as FF circuit) delayed with respect to the signal input of the storage circuit 9 which is the circuit under test.
CK is generated by the delay circuit 10. The held clock signal TCK of the FF circuit 12 is output from the data output DO of the storage circuit 9.
To control the holding operation of the FF circuit. The output signal of the delay circuit 10 is simultaneously drawn out of the semiconductor chip through a delay circuit 11 composed of delay elements of the same kind as the delay circuit 10.

Next, the operation will be described. When the signal indicated by the memory clock signal CLK is input to the storage circuit 9, it is output to the data output DO with a delay of the memory access time. The holding clock signal TCK of the FF circuit 12 is input with a delay of the delay circuit 10 with respect to the memory clock signal CLK.

The power supplied to the delay circuits 10 and 11 is separate from the power supply of the other circuits.
11 can be changed.

In order to measure the access time of the memory in the conventional test circuit, the minimum amount of data that can be expected as the output data of the storage circuit 9 by the FF circuit 12 is changed by changing the delay amount of the delay circuit 10. Find the condition that gives the delay amount. At this time, the amount of delay of the delay circuit 10 is the access time of the storage circuit 9.

[0008] The delay amount of the delay circuit 10 is obtained as follows. Under the above-mentioned delay condition, the memory clock signal C
LK, a memory clock signal CLK and a delay circuit 1
The phase difference of the signal at the output terminal CKO 1 is measured. Since the number of stages of the delay elements of the delay circuits 10 and 11 is known, the delay amount of the delay circuit 10 is determined from the ratio of the number of stages of the delay elements and the phase difference between the memory clock signal CLK and the signal of the output terminal CKO. Can be calculated.

[0009]

However, the prior art has the following problems. The first problem is that it is difficult to accurately determine the absolute value of the memory access time. The reason is that the characteristics of the delay elements used in the delay circuit 10 and the delay circuit 11 used in the circuit that generates the test signal vary, and that the delay elements exist outside the semiconductor chip from the delay circuit 10. It is difficult to accurately measure the delay amounts of the delay circuits 10 and 11 due to the influence of wiring delay and input / output buffers.

[0010] The second problem is that a high-performance measuring instrument is required to perform the measurement with high accuracy. The reason is,
Since the access time of the memory is as short as about several ns, and the phase difference between the memory clock signal CLK and the signal at the output terminal CKO of the delay circuit 11 does not become so large, unless measurement is performed using a very high-speed measuring instrument, This is because sufficient accuracy cannot be obtained. If the number of stages of the delay circuit 11 is increased in order to increase the phase difference between the memory clock signal CLK and the signal at the output terminal CKO of the delay circuit 11, the number of delay elements increases accordingly, and the influence of variations in their characteristics also increases. The area occupied by the circuit increases.

The present invention has been made in view of the above problems, and has as its object to measure a memory access time from outside a semiconductor chip without being affected by a wiring delay or the like in the semiconductor chip. An object of the present invention is to provide a semiconductor integrated circuit capable of measuring circuit characteristics.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit having a memory circuit and capable of measuring an access time of the memory circuit, wherein an operation of holding an input signal can be controlled. A holding circuit, a delay circuit for delaying a memory clock signal controlling the memory circuit,
Selection of inputting an output signal obtained by delaying the memory clock signal from the delay circuit and the memory clock signal, selecting one of the two input signals, and outputting the selected signal to the delay circuit And a semiconductor integrated circuit. The gist of the present invention according to claim 2 is that the holding circuit provided on the signal output side of the memory circuit and the holding clock signal for controlling the holding circuit, which is obtained by delaying the memory clock signal, 2. The semiconductor integrated circuit according to claim 1, further comprising: the delay circuit that outputs the signal; and the selection circuit that can switch selection between the memory clock signal and the holding clock signal by a selection signal. Exist. According to a third aspect of the present invention, there is provided the semiconductor integrated circuit according to the first or second aspect, further comprising an oscillation circuit oscillating by the selection circuit and the delay circuit. The gist of the present invention according to claim 4 is that, in order to externally control the signal selection of the selection circuit, a selection signal line drawn out of the semiconductor chip from the selection circuit and a signal output from the holding circuit are provided. 4. The semiconductor integrated circuit according to claim 1, further comprising a signal output terminal for observing, and a signal terminal for observing the held clock signal. The gist of the present invention as set forth in claim 5 is that the delay circuit supplies a power supply independently of an odd-numbered inverter circuit that can constitute a ring oscillator and a power supply supplied to another circuit in the semiconductor integrated circuit. And a delay circuit power supply line that can be supplied.
A semiconductor integrated circuit according to any one of claims 1 to 4. The gist of the present invention is that an output signal from the last stage of the inverter circuit row and an output signal from a middle stage of the inverter circuit row are input and any one of these two input signals is used. A second selection circuit for selecting and outputting one of the signals; and a second selection signal line drawn out of the semiconductor from the second selection circuit for externally controlling the signal selection of the second selection circuit. The semiconductor integrated circuit according to any one of claims 1 to 5, further comprising: The gist of the present invention according to claim 7 resides in a semiconductor integrated circuit according to any one of claims 1 to 6, wherein a flip-flop circuit is provided as the holding circuit. The gist of the present invention according to claim 8 resides in a semiconductor integrated circuit according to any one of claims 1 to 6, wherein a latch circuit is provided as the holding circuit. The gist of the present invention according to claim 9 is a method for measuring an access time of a memory circuit, wherein one memory clock signal input to the delay circuit from the selection circuit is output after being delayed from the delay circuit, and The holding circuit determines the timing at which the holding circuit holds data, and the signal input of the memory circuit becomes a data output delayed by the access time of the memory circuit when the memory clock signal is input to the memory circuit. A data output is input to the holding circuit, and by adjusting a delay amount of the delay circuit,
By changing the phase difference of the holding clock signal with respect to the memory clock signal to a minimum phase difference at which the holding circuit can hold the data output, switching the output selection of the selection circuit, and holding the output from the delay circuit The clock signal is fed back to the selection circuit and selected and output to the delay circuit, whereby the selection circuit and the delay circuit operate as an oscillation circuit, and the oscillation cycle of the oscillation circuit is By measuring the oscillation period from the signal terminal of the holding clock signal of the holding circuit, in which the oscillation period is drawn out of the semiconductor chip, and obtaining the delay amount of the delay circuit, An access time measurement method for a memory circuit, characterized in that the access time of the memory circuit can be measured. The gist of the present invention described in claim 10 resides in a storage medium storing a program capable of executing the memory circuit access time measuring method described in claim 9.

[0013]

(Embodiment 1) Next, Embodiment 1 of the present invention will be described in detail with reference to the drawings.
As shown in FIG. 1, the semiconductor integrated circuit according to the first embodiment of the present invention is schematically configured by a memory circuit 1, a flip-flop circuit 2, a selection circuit 3, and a delay circuit 4, and is provided in a semiconductor chip 6. ing. The flip-flop circuit 2 is used as a holding circuit.

The data output DO of the memory circuit 1 is input to the flip-flop circuit 2. The signal output TDO of the flip-flop circuit 2 is drawn to a signal output terminal outside the semiconductor chip. The memory circuit 1 performs a read operation in synchronization with the memory clock signal CLK.
The memory clock signal CLK is supplied to the selection circuit 3 and the delay circuit 4
Clock signal T of the flip-flop circuit 2
As CK, the signal holding operation of the flip-flop circuit 2 is controlled. The delay circuit 4 can change the delay amount from outside the semiconductor chip. Further, the holding clock signal TCK of the flip-flop circuit 2 is input to the other one of the selection circuits 3, and the selection circuit 3 and the delay circuit 4 operate as the oscillation circuit 5.

The operation mode of the selection circuit 3 is selected by an operation mode control signal SEL from a selection signal line drawn out of the semiconductor chip, so that the operation mode of the selection circuit 3 can be controlled from outside the semiconductor chip. It is possible. When the mode of outputting the signal of the memory clock signal CLK to the output of the selection circuit 3 is set, the selection circuit 3 and the delay circuit 4 operate as a normal delay circuit 4, and the output of the selection circuit 3 holds the flip-flop circuit 2. When the mode of outputting the clock signal TCK is set, the selection circuit 3 and the delay circuit 4
As a result, the circuit operates as an oscillating circuit and performs an oscillating operation at an oscillating cycle corresponding to the delay amount. FIG. 3 and FIG.
FIG. 3 is a block diagram showing the configuration of FIG.

The above configuration will be described using a specific example. An example of the oscillation circuit 4 including the selection circuit 3 and the delay circuit 4 in FIG. 1 will be described with reference to FIG.

The delay circuit 4 is a circuit in which inverter circuits 7 are connected in series. The number of connection stages of these inverter circuits 7 is set to be an odd number so that a ring oscillator can be configured to obtain the delay amount of the delay circuit 4.
The delay circuit power supply VD supplied to the inverter circuit 7
The DX has a different system from a power supply line supplied to other circuits of the semiconductor chip, and is drawn out of the semiconductor chip as a delay circuit power supply line.

An input signal from the input terminal A of the selection circuit 3 'is input to the delay circuit 4 composed of a column of the inverter circuits 7 through the selection circuit 3'. The signal from the output terminal B of the delay circuit 4 is input to the other signal input of the selection circuit 3 ', and either of the two signals is output according to the operation mode control signal SEL. Inverter circuit 7
Is set to be an odd number, the logic of the operation mode control signal SEL is set, and the signal at the output terminal B of the delay circuit 4 appears at the output of the selection circuit. A ring oscillator is constituted by the rows, and starts oscillating at an oscillation cycle proportional to the amount of delay by the inverter row 7 and the selection circuit.

Next, the operation will be described with reference to the drawings. Since the memory circuit 1 of FIG. 1 operates in synchronization with the memory clock signal CLK, the data output DO is delayed by an access time taa of the memory circuit 1 after the input of the memory clock signal CLK.

In advance, a signal obtained by delaying the memory clock signal CLK is output to the output of the delay circuit 4 by the logic setting of the control signal SEL in the operation mode of the selection circuit 3. One memory clock signal CLK is input to the memory circuit 1 and the other memory clock signal CLK
Is delayed by the delay circuit 4, and determines the timing at which the flip-flop circuit 2 holds data as the holding clock signal TCK of the flip-flop circuit 2. The signal held by the flip-flop circuit 2 is output outside the semiconductor chip and is observed at a signal output terminal.

Next, the phase difference of the held clock signal TCK of the flip-flop circuit 2 with respect to the memory clock signal CLK is changed by adjusting the delay amount of the delay circuit 4, and the output data of the memory circuit 1 is changed by the flip-flop circuit 2. Adjust the delay conditions so that the minimum phase difference that can be held is obtained.

At this time, the phase difference between the memory clock signal CLK and the clock signal TCK held by the flip-flop circuit 2 becomes the access time taa of the memory circuit 1. The delay amount of the delay circuit 4 can be controlled from outside the semiconductor chip.

FIG. 2 is a waveform chart showing the above operation. The signal input ADD of the memory circuit is the memory clock signal CL
The signal is input to the memory circuit 1 with an appropriate setup time with respect to the rising timing of the K signal. When memory clock signal CLK is input to memory circuit 1, data output DO changes with a delay of access time taa of memory circuit 1.

After the change of the data output DO, when the holding clock signal TCK of the flip-flop circuit 2 is input, the signal input to the flip-flop circuit 2 is held and output as the signal output TDO of the flip-flop circuit 2. You. The phase of the holding clock signal TCK of the flip-flop circuit 2 is delayed from the memory clock signal CLK by the delay amount tdly of the delay circuit 4 in FIG.

That is, the rising signal of the memory clock signal CLK is input to the memory circuit 1 and the access time t
Data output DO is performed after aa. Since the flip-flop circuit 2 to which the data output DO is input holds and outputs the input signal at the time of the rising of the holding clock signal TCK, the data output DO at the moment when the holding clock signal TCK rises becomes the signal output TDO. .

Therefore, the delay amount tdly <access time t
Under the condition aa, the correct output signal of the memory circuit 1 has not yet been input to the input of the flip-flop circuit 2, so that no correct output signal is output to the signal output TDO.

As described above, whether or not a known signal is output as an output signal of the memory circuit 1 to the signal output TDO depends on whether the delay amount tdly <access time taa or the delay amount tdly> access time taa. Since it can be determined whether or not the delay condition is satisfied, the delay amount tdly is changed so that the delay amount tdly <the access time taa and the delay amount t
dly> the state where the delay condition is at the boundary of the access time taa, that is, the delay amount tdly = the access time ta
access time t by finding the delay condition that is a
aa can be measured.

Next, the logic of the operation mode control signal SEL is switched while the delay condition of the delay circuit 4 is maintained in the same state as described above, and the selection circuit 3 selects the output signal of the delay circuit 4 and 3 so that the output signal of the delay circuit 4 appears at the output. At this time, the selection circuit 3 and the delay circuit 4 operate as an oscillation circuit. The oscillation cycle is proportional to the delay amount tdly of the delay circuit 4 (oscillates at a cycle twice as long as the delay time). This oscillation cycle can be observed from the signal terminal of the holding clock signal TCK of the flip-flop circuit 2 drawn out of the semiconductor chip. By measuring the oscillation period, the delay amount of the delay circuit 4 can be specifically obtained, and the access time of the memory can be measured.

FIG. 5 shows a flowchart of the operation of the semiconductor integrated circuit according to the embodiment of the present invention.

A specific example of the above operation will be described with reference to the drawings. The delay circuit power supply VDDX shown in FIG. 3 supplies power to the inverter circuit 7 constituting the delay circuit. The delay circuit power supply VDDX is drawn out of the semiconductor chip as a delay circuit power supply, and can set a power supply voltage to be applied independently of the power supply voltages of other circuits in the semiconductor chip.

When the voltage applied to the delay circuit power supply VDDX is changed, the amount of delay of the inverter circuit 7 changes, so that the amount of delay of the delay circuit composed of the columns of the inverter circuits 7 also changes. That is, the delay amount of the delay circuit can be controlled by the voltage of the delay circuit power supply VDDX. The input signal A is selectively output to the output of the selection circuit 3 ',
Operation mode control signal SEL to be input to the delay circuit
, This circuit operates as a normal delay circuit. By switching the logic of the control signal SEL in the operation mode,
When the output signal B of the delay circuit is output to the output of the selection circuit 3 ', the row of the selection circuit 3' and the inverter circuit 7 forms a ring oscillator, and oscillates at a period proportional to the delay amount.

The semiconductor integrated circuit according to the first embodiment has the following effects because it is configured as described above. All circuits necessary for measuring the access time, such as the delay circuit and flip-flop circuit, are built in the same semiconductor chip as the memory circuit of the circuit under test, and the wiring By minimizing the wiring length etc., the influence of wiring delay etc. can be reduced, and since the delay value of the delay circuit related to the accuracy of access time measurement is converted to frequency and measured, wiring delay etc. Since it is not affected, the access time of the memory can be measured with high accuracy. Further, since the measurement of the delay amount in the integrated circuit can be performed by replacing the measurement with the frequency, a high-performance test apparatus is not required for performing the above measurement.

(Second Embodiment) Next, a second embodiment of the present invention will be described in detail with reference to the drawings. An example of the oscillation circuit 4 configured by the selection circuit 3 and the delay circuit 4 in FIG. 1 will be described with reference to FIG.

In the second embodiment, the delay circuit has a configuration in which inverter circuits 7 'are connected in series, and inputs an input from A' and a delayed output signal B 'to a selection circuit 3''.
Switching between the operation as the delay circuit and the mode as the ring oscillator in accordance with the control signal SEL of the operation mode is the same as in the first embodiment, but the last stage and two stages before the last stage in the column of the inverter circuit 7 '. The signal from the second
One of the signals from the signal lines C and D input to the selection circuit 8 is selected by the second selection circuit 8 and output to B ′.

The switching signal SELD of the second selection circuit 8 for adjusting the number of delay stages, which controls the selection operation of the selection circuit, is supplied from the outside of the semiconductor chip to the second selection signal line via a second selection signal line drawn out of the semiconductor chip. The circuit can be controlled, the number of stages of the inverter circuit 7 'is changed, and the delay amount of the delay circuit is made variable.

FIG. 4 shows an example in which signal lines are taken out from one place in the inverter train and from the last stage. However, by taking out signal lines from a plurality of places in the inverter train, the delay amount is reduced. It is also possible to widen the range of change.

The semiconductor integrated circuit according to the second embodiment, which can measure the access time of the memory circuit, has the following effects in addition to the effects of the first embodiment because it is configured as described above. By taking out the signal line from the middle of the inverter row, it is possible to widen the range in which the delay amount is changed.

In the first and second embodiments of the present invention, the data output of the memory circuit 1 is held by the flip-flop circuit. However, this can be replaced by a latch circuit.

[0039]

Since the present invention is configured as described above, the following effects can be obtained. The first effect is that the access time of the memory can be measured with high accuracy. The reason is that all the circuits necessary for the measurement such as the delay circuit and the flip-flop circuit 2 necessary for the measurement of the access time are built in the same semiconductor chip as the memory circuit 1 of the circuit under test, and the accuracy of the measurement decreases. This is because the influence of wiring delay and the like can be reduced by minimizing the wiring length and the like of the wiring that causes the wiring. In addition, because the delay value of the delay circuit relating to the accuracy of the access time measurement is converted into a frequency and measured, there is no influence of wiring delay or the like.

A second advantage is that a high-performance test apparatus is not required for performing the above measurement. The reason is,
This is because the measurement of the delay amount in the integrated circuit can be measured by replacing it with the frequency.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of the oscillation circuit of FIG. 1;

FIG. 4 is a block diagram illustrating an example of the oscillation circuit of FIG. 1;

FIG. 5 is a flowchart showing an operation of the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 6 is a block diagram of a circuit showing an example of the related art.

[Explanation of symbols]

 A, A 'input signal ADD signal of memory circuit B, B' output signal of delay circuit C signal line CKO output terminal CLK memory clock signal D signal line DO data output SEL operation mode control signal SELD switching signal of second selection circuit TCK holding clock signal TDO signal output taa Access time of memory circuit tdly Delay amount of delay circuit VDDX Delay circuit power supply 1 Memory circuit 2 Flip-flop circuit 3, 3 ', 3' 'selection circuit 4 Delay circuit 5 Oscillation circuit 6 Semiconductor chip 7 , 7 'Inverter circuit 8 Second selection circuit 9 Storage circuit 10, 11 Delay circuit 12 FF circuit

Claims (10)

[Claims] 1. A semiconductor integrated circuit having a memory circuit and capable of measuring an access time of the memory circuit, comprising: a holding circuit capable of controlling a holding operation of holding an input signal; A delay circuit for delaying the memory clock signal and the memory clock signal from the delay circuit, and selecting one of the two input signals; A semiconductor integrated circuit, comprising: a selection circuit that outputs to a circuit. 2. A storage circuit provided on a signal output side of the memory circuit, and obtained by delaying the memory clock signal.
The delay circuit that outputs a holding clock signal that controls the holding circuit, and the selection circuit that can switch selection between the memory clock signal and the holding clock signal by a selection signal. The semiconductor integrated circuit according to claim 1, wherein 3. The semiconductor device according to claim 1, further comprising: an oscillating circuit that performs an oscillating operation by said selecting circuit and said delay circuit.
Or the semiconductor integrated circuit according to 2. 4. A selection signal line drawn from the selection circuit to the outside of the semiconductor chip for externally controlling signal selection of the selection circuit, and a signal output for observing a signal output from the holding circuit. 4. The semiconductor integrated circuit according to claim 1, further comprising: a terminal; and a signal terminal for observing the held clock signal. 5. The delay circuit includes: an odd-numbered inverter circuit that can form a ring oscillator; and a delay circuit power supply line that can supply power independently of power supplied to other circuits in the semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1, further comprising: 6. An output signal from the last stage of the inverter circuit row and an output signal from a middle stage of the inverter circuit row are input, and one of the two input signals is selected. And a second selection circuit for outputting a signal, and a second selection signal line led out of the semiconductor from the second selection circuit for externally controlling the signal selection of the second selection circuit. Claims 1 to 5
A semiconductor integrated circuit according to any one of the above. 7. The semiconductor integrated circuit according to claim 1, wherein a flip-flop circuit is provided as said holding circuit. 8. The semiconductor integrated circuit according to claim 1, further comprising a latch circuit as said holding circuit. 9. A method for measuring an access time of a memory circuit, wherein one memory clock signal input to the delay circuit from the selection circuit is output after being delayed from the delay circuit, and The holding circuit determines the timing for holding data, and the signal input of the memory circuit becomes a data output delayed by an access time of the memory circuit when a memory clock signal is input to the memory circuit, and the data output is stored in the holding circuit. And adjusting the delay amount of the delay circuit to change the phase difference of the holding clock signal with respect to the memory clock signal so that the holding circuit has a minimum phase difference capable of holding the data output. The output selection is switched, and the held clock signal output from the delay circuit is feedback-input to the selection circuit. By selecting and outputting to the delay circuit, the selection circuit and the delay circuit operate as an oscillation circuit, and the oscillation cycle of the oscillation circuit is proportional to the delay amount of the delay circuit. Measuring the oscillation period from the signal terminal of the holding clock signal of the holding circuit drawn out of the semiconductor chip, and measuring the access time of the memory circuit by calculating the delay amount of the delay circuit. To measure the access time of a memory circuit. 10. A storage medium storing a program capable of executing the method for measuring access time of a memory circuit according to claim 9.