JP2000025074A - Apparatus and method for molding, method for cutting molded semiconductor apparatus, and manufacture of semiconductor apparatus - Google Patents
Apparatus and method for molding, method for cutting molded semiconductor apparatus, and manufacture of semiconductor apparatusInfo
- Publication number
- JP2000025074A JP2000025074A JP10198201A JP19820198A JP2000025074A JP 2000025074 A JP2000025074 A JP 2000025074A JP 10198201 A JP10198201 A JP 10198201A JP 19820198 A JP19820198 A JP 19820198A JP 2000025074 A JP2000025074 A JP 2000025074A
- Authority
- JP
- Japan
- Prior art keywords
- molding
- cutting
- molded
- semiconductor
- cutting blade
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonmetal Cutting Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数の半導体素子
を一括してモールドするモールド装置、モールド方法及
び一括してモールドされた半導体装置の切断方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a molding apparatus for molding a plurality of semiconductor elements at once, a molding method, and a method for cutting semiconductor devices at once.
【０００２】[0002]
【従来の技術】パッケージ裏面に外部接続用端子を設け
た半導体装置を製造する場合、ＩＣなどの半導体素子を
載せる基板としてテープ、ガラスエポキシ基板、リード
フレームなどが用いられる。そして前記基板にダイシン
グされた半導体素子を載せ、半導体素子上に設けられた
電極と基板上の電極とをワイヤボンディングまたはフリ
ップチップボンディングを行い、樹脂などのモールド材
にて各パッケージ毎に成形し、モールド後に前記外部接
続端子にはんだバンプ又ははんだボールを形成し、その
後各半導体装置に切断していた。2. Description of the Related Art When manufacturing a semiconductor device having a terminal for external connection provided on the back surface of a package, a tape, a glass epoxy substrate, a lead frame or the like is used as a substrate on which a semiconductor element such as an IC is mounted. Then, the diced semiconductor element is placed on the substrate, and the electrodes provided on the semiconductor element and the electrodes on the substrate are subjected to wire bonding or flip chip bonding, and are molded for each package with a molding material such as a resin, After molding, solder bumps or solder balls are formed on the external connection terminals, and then cut into individual semiconductor devices.
【０００３】半導体装置のモールド方法として、トラン
スファモールド法が広く知られている。このモールド法
は予めリードフレームなどにＩＣチップなどの半導体素
子をワイヤボンディングにより組み込んでおき、これを
モールド金型に入れて、粉末状またはタブレット状のエ
ポキシ樹脂などを温度と圧力をかけて溶融させ、粘度の
低い状態にして前記金型内に注入し、硬化させてモール
ドするものである。As a method for molding a semiconductor device, a transfer molding method is widely known. In this molding method, a semiconductor element such as an IC chip is incorporated in a lead frame or the like in advance by wire bonding, and this is put into a molding die, and a powdery or tablet-like epoxy resin is melted by applying temperature and pressure. Then, the mixture is poured into the mold in a state of low viscosity, cured, and molded.
【０００４】図８は、従来のモールド法にて複数の半導
体素子をモールドした分離前の半導体装置を示してお
り、図８（Ａ）は金型から取り出した状態の斜視図、図
８（Ｂ）は図８（Ａ）のＡーＡ’断面図である。従来、
複数の半導体素子をモールドするために、半導体素子１
を絶縁フィルム等の絶縁基板２上に複数個マトリクス状
に固定して配置し、半導体素子１を個別に収容できるキ
ャビティ及びキャビティ間を樹脂の通路として繋ぐラン
ナーで構成された金型を備えたトラスファーモールド装
置にてモールドされる。モールドが終了すると、図９に
示すように、モールド樹脂３でモールドされた個別の半
導体装置１ａにそれぞれ切断分離されて一個の製品とさ
れる。FIG. 8 shows a semiconductor device before separation in which a plurality of semiconductor elements are molded by a conventional molding method. FIG. 8 (A) is a perspective view of the semiconductor device taken out of a mold, and FIG. 9) is a sectional view taken along the line AA ′ of FIG. Conventionally,
To mold a plurality of semiconductor elements, the semiconductor element 1
Truss provided with a plurality of cavities fixedly arranged in a matrix on an insulating substrate 2 such as an insulating film or the like, and a mold formed of cavities capable of individually accommodating the semiconductor elements 1 and runners connecting the cavities as resin passages It is molded by a fur molding device. When the molding is completed, as shown in FIG. 9, the individual semiconductor devices 1a molded with the molding resin 3 are cut and separated into one product.
【０００５】前記半導体素子１のモールドが完了すると
各半導体素子のはんだボール接続端子にはんだボール４
が形成され、その後切断分離されて個別の半導体装置１
ａが得られるまでの状態を見ると、図８に示すように、
基板２には、半導体素子１を載せる領域５、ワイヤ６で
ワイヤボンディングを行う領域７、及びモールド金型の
領域８が必要となる。When the molding of the semiconductor element 1 is completed, the solder balls 4 are connected to the solder ball connection terminals of each semiconductor element.
Is formed and then cut and separated to obtain individual semiconductor devices 1.
Looking at the state until a is obtained, as shown in FIG.
The substrate 2 needs an area 5 on which the semiconductor element 1 is mounted, an area 7 for performing wire bonding with the wire 6, and an area 8 of a mold.
【０００６】さらに、切断される前の状態では、切断時
の基板の半導体装置保持用押え領域９、基板の切断代１
０、樹脂注入領域１１、搬送孔１２ａが形成された搬送
部分１２、更にキャビティ間を繋ぐランナー領域１３で
占められている。なお、樹脂注入領域１１は実際には複
数存在するが、ここでは１つだけ図示している。Further, in the state before the cutting, the semiconductor device holding press region 9 of the substrate at the time of cutting and the cutting allowance of the substrate 1
0, a resin injection region 11, a transport portion 12 in which a transport hole 12a is formed, and a runner region 13 connecting the cavities. Although there are actually a plurality of resin injection regions 11, only one is shown here.
【０００７】ところで、モールド終了後、図９に示すよ
うな樹脂３でモールドされた各半導体装置１ａに切断し
て一個の製品とする必要があるが、各半導体装置に切断
するために、従来はダイとパンチを利用していた。By the way, after the molding is completed, it is necessary to cut each semiconductor device 1a molded with the resin 3 as shown in FIG. 9 into one product. He used dies and punches.
【０００８】[0008]
【発明が解決しようとする課題】このように、従来のよ
うに半導体素子を個別に収容する複数のキャビティと各
キャビティ間を繋ぐランナーを備えるトランスファーモ
ールド装置で半導体素子をモールドすると、半導体素子
をモールドすべき必要な部分以外に、製品（半導体装
置）には不必要であるが、トランスファーモールド装置
の構造上ランナーや樹脂注入部分に樹脂が残ることにな
る。As described above, when a semiconductor element is molded by a transfer molding apparatus having a plurality of cavities for individually accommodating semiconductor elements and a runner connecting the cavities as in the prior art, the semiconductor element is molded. Although it is unnecessary for a product (semiconductor device) other than the necessary part to be performed, the resin remains on the runner and the resin injection part due to the structure of the transfer molding apparatus.
【０００９】樹脂モールドした際にランナー部分で連結
された半導体装置を個々の半導体装置に切断した際に、
製品として半導体装置に必要不可欠な部分は、基板の半
導体素子を載せる領域、ワイヤボンディングする領域、
筐体となるモールド金型の領域及び切断時の半導体装置
保持用押え領域の部分であり、他の部分は前記したよう
に製造上必要であるが製品とはならない無駄な部分であ
る。したがってこれら無駄な部分の取り除き、廃棄処分
などに手間を要することになる。When a semiconductor device connected by a runner portion is cut into individual semiconductor devices at the time of resin molding,
The indispensable parts of the semiconductor device as a product are the area where the semiconductor element of the substrate is mounted, the area where wire bonding is performed,
This is the area of the mold die serving as the housing and the holding area for holding the semiconductor device at the time of cutting, and the other parts are useless parts that are necessary for manufacturing as described above but do not become products. Therefore, it takes time to remove these useless parts and to dispose them.
【００１０】また、製品取れ個数を多くしようとする
と、キャビティ間のランナーも多くなり、これによって
時間的に早く注入される部分と遅く注入される部分が存
在し、半導体装置を収容したキャビティ内に注入される
樹脂の状態に差が発生し、品質的に均等なものができに
くくなる。さらに、モールドされた半導体装置を個々の
半導体装置に切断分離するのに従来はダイとパンチを使
用していたが、このような切断装置では、大掛かりな構
造とならざるをえない。さらに半導体装置を個々に切断
する時に、個々のサイズに合わせたダイやパンチが必要
となり、切断効率も悪くそれだけ費用負担も増加する。In order to increase the number of products to be obtained, the number of runners between cavities also increases. As a result, there are a portion that is injected earlier and a portion that is injected later. A difference occurs in the state of the injected resin, and it becomes difficult to obtain a resin having a uniform quality. Further, conventionally, a die and a punch have been used to cut and separate a molded semiconductor device into individual semiconductor devices. However, such a cutting device has to be a large-scale structure. Furthermore, when individual semiconductor devices are cut, dies and punches are required that match the individual sizes, resulting in poor cutting efficiency and an increase in cost.
【００１１】本発明は、前記問題点に鑑み、モールド時
に無駄な部分が発生しないモールド装置、モールド方
法、モールドされた複数の半導体装置を個々の半導体装
置に切断する切断方法及び半導体装置の作製方法を提案
するものである。In view of the above problems, the present invention provides a molding apparatus, a molding method, a cutting method of cutting a plurality of molded semiconductor devices into individual semiconductor devices, and a method of manufacturing a semiconductor device in which useless portions are not generated during molding. Is proposed.
【００１２】[0012]
【課題を解決するための手段】本発明のモールド装置
は、モールドされる複数の半導体素子を切断刃で切断し
て分離できる間隔をおいて配設した絶縁基板を収容し、
一括してモールドするキャビティを備える。そして、一
括してモールドされた半導体装置を切断刃で個々の半導
体装置に切断して分離する。According to the present invention, there is provided a molding apparatus for accommodating an insulating substrate provided at an interval capable of cutting and separating a plurality of semiconductor elements to be molded by a cutting blade,
It has a cavity for molding all at once. Then, the semiconductor devices molded collectively are cut into individual semiconductor devices by a cutting blade and separated.
【００１３】[0013]
【発明の実施の形態】以下、本発明について、モールド
装置、モールド方法及び切断方法の順に説明する。図７
において、図７（Ａ）は後述する本発明のモールド装置
にて複数の半導体素子が一括してモールドされた一体構
造のモールド体２５の斜視図、図７（Ｂ）は、図７
（Ａ）のＡーＡ’断面図であって、モールド後に基板の
裏側にはんだボール２６が形成された状態を示してい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in the order of a molding apparatus, a molding method and a cutting method. FIG.
7A is a perspective view of a molded body 25 having an integral structure in which a plurality of semiconductor elements are collectively molded by a molding apparatus of the present invention described later, and FIG. 7B is a perspective view of FIG.
FIG. 3A is a cross-sectional view taken along the line AA ′ of FIG. 3A, showing a state where solder balls 26 are formed on the back side of the substrate after molding.
【００１４】図７（Ａ）及び図７（Ｂ）に示すように、
基板２１に後述する切断刃で切断して分離できる間隔を
おいて配設された複数の半導体素子２０は点線で示す枠
内に位置して一括して樹脂２２にてモールドされ、この
モールド体２５には従来のトランスファーモールドのよ
うにランナーによるモールド樹脂残存部は存在しない。
またモールド体２５の四辺には切断時の切り捨て代２４
が設けられている。As shown in FIGS. 7A and 7B,
A plurality of semiconductor elements 20 arranged at intervals that can be cut and separated on a substrate 21 by a cutting blade described later are positioned in a frame indicated by a dotted line and are collectively molded with a resin 22. Does not have a mold resin remaining portion due to a runner unlike the conventional transfer mold.
Further, the four sides of the mold body 25 have a cut-off allowance 24 for cutting.
Is provided.
【００１５】以下、前記複数の半導体素子を一括してモ
ールドするモールド装置について説明する。図６に、モ
ールドされる複数の半導体素子をマトリクス状に配設す
るガラスエポキシ材からなる基板やポリイミド樹脂など
の耐熱性の可撓性絶縁材料からなる基板２１（以下、基
板２１という）を示している。図６に示すように、基板
２１上にマトリクス状に連なって半導体素子搭載部２１
ａが設けられており、各半導体素子搭載部２１ａには半
導体素子とワイヤボンディングされるボンディングパッ
ド３０と、該ボンディングパッド３０の一端にモールド
後に半導体素子の外部接続用端子にはんだボールを接続
するための裏面導通端子３１が形成されており、基板２
１には該裏面導通端子３１と対応する位置に、基板裏面
からはんだボールを接続するためのスルーホール（図示
せず）が形成されている。Hereinafter, a molding apparatus for molding the plurality of semiconductor elements at once will be described. FIG. 6 shows a substrate made of a glass epoxy material in which a plurality of semiconductor elements to be molded are arranged in a matrix or a substrate 21 made of a heat-resistant flexible insulating material such as a polyimide resin (hereinafter, referred to as a substrate 21). ing. As shown in FIG. 6, the semiconductor element mounting portion 21 is formed on the substrate 21 in a matrix.
The semiconductor device mounting portion 21a is provided with a bonding pad 30 to be wire-bonded to the semiconductor device, and a solder ball connected to an external connection terminal of the semiconductor device after molding at one end of the bonding pad 30. Is formed on the back surface of the substrate 2.
1 has a through hole (not shown) for connecting a solder ball from the back surface of the substrate at a position corresponding to the back surface conduction terminal 31.
【００１６】そして、これら半導体素子搭載部２１ａに
は、半導体素子２０が仮止めされ、半導体素子２０上に
設けられたボンディングパッド３２と前記基板２１に設
けられたボンディングパッド３０とが金ワイヤ３３でワ
イヤボンディングされている。The semiconductor element 20 is temporarily fixed to these semiconductor element mounting portions 21a, and the bonding pads 32 provided on the semiconductor element 20 and the bonding pads 30 provided on the substrate 21 are connected by gold wires 33. Wire bonded.
【００１７】後述するように、複数の半導体素子を一括
モールドした後のモールド体２５（図７）を個々の半導
体装置に回転刃で切断できるように、隣接する半導体素
子のボンディングパッド３０の間隔を例えば０．１ｍｍ
以上としている。As will be described later, the spacing between the bonding pads 30 of the adjacent semiconductor elements is set so that the molded body 25 (FIG. 7) after a plurality of semiconductor elements are collectively molded can be cut into individual semiconductor devices with a rotary blade. For example, 0.1mm
That is all.
【００１８】次に、前記基板２１に配設された半導体素
子２０を一括モールドするモールド装置を構成する金型
について図２及び図３を参照しながら説明する。図２に
示すように、上金型４０は、前記基板２１を一枚収容す
る一個のキャビティ４０ａ、該キャビティ４０ａ内にモ
ールド用樹脂を注入する複数の樹脂注入口４０ｂを備え
ている。また、前記キャビティ４０ａの周壁全体に、一
括モールドされたモールド体をキャビティ４０ａ内から
容易に抜き出せるように、抜き勾配の傾斜部４０ｃが設
けられている。Next, a mold constituting a molding apparatus for collectively molding the semiconductor elements 20 disposed on the substrate 21 will be described with reference to FIGS. As shown in FIG. 2, the upper mold 40 has one cavity 40a for accommodating one substrate 21 and a plurality of resin injection ports 40b for injecting a molding resin into the cavity 40a. Further, an inclined portion 40c having a draft angle is provided on the entire peripheral wall of the cavity 40a so that the molded body which is collectively molded can be easily extracted from the inside of the cavity 40a.
【００１９】さらに、前記キャビティ４０ａの左右上下
端部にエジェクターピン挿入穴４０ｄがそれぞれ設けら
れており、モールド終了後にこれらの挿入穴からエジェ
クターピンを挿入してモールド体を押して上金型から取
り出すようになっている。また図示しないが、前記抜き
勾配の傾斜部４０ｃの任意の位置に樹脂注入時に発生し
たガスを外部に放出するためのエアーベントが設けられ
ている。Further, ejector pin insertion holes 40d are provided at the left, right, upper and lower ends of the cavity 40a, respectively. After completion of molding, ejector pins are inserted from these insertion holes, and the molded body is pushed out of the upper mold. It has become. Although not shown, an air vent for releasing gas generated during resin injection to the outside is provided at an arbitrary position of the draft inclined portion 40c.
【００２０】一方、図３及び図４に示すように下金型４
１は、前記基板２１を受ける座ぐり穴からなる底が平ら
な基板受け穴４１ａが形成されており、該基板受け穴４
１ａの周囲には前記上金型４０の当接面４０ｅと当接す
る当接面４１ｂを備えている。また基板受け穴４１ａの
複数箇所に前記基板の位置決め穴に嵌る基板位置決めピ
ン４１ｃが設けられている。他の実施の形態として、複
数枚の基板をそれぞれ一括モールドする場合は、それぞ
れの基板を収容する複数のキャビティを上金型に設け、
下金型には複数のキャビティにそれぞれ対応する基板受
け穴を設けてモールド装置を構成する。On the other hand, as shown in FIGS.
Reference numeral 1 denotes a substrate receiving hole 41a having a flat bottom formed of a counterbore for receiving the substrate 21.
A contact surface 41b that comes into contact with the contact surface 40e of the upper mold 40 is provided around 1a. In addition, board positioning pins 41c that fit into the positioning holes of the board are provided at a plurality of locations of the board receiving holes 41a. As another embodiment, when collectively molding a plurality of substrates, a plurality of cavities for accommodating the respective substrates are provided in the upper mold,
The lower die has a substrate receiving hole corresponding to each of the plurality of cavities to constitute a molding apparatus.
【００２１】以下、前記上金型４０及び下金型４１を備
えたモールド装置により一括モールドを行い、モールド
体を個々の半導体装置に切断して個々の半導体装置を得
るプロセスを説明する。まず、図６に示すようにな、一
括モールド後に回転刃で切断できる間隔で半導体素子が
それぞれ配設された基板を用意する。Hereinafter, a description will be given of a process in which collective molding is performed by a molding apparatus having the upper mold 40 and the lower mold 41, and the molded body is cut into individual semiconductor devices to obtain individual semiconductor devices. First, as shown in FIG. 6, a substrate on which semiconductor elements are arranged at intervals that can be cut by a rotary blade after batch molding is prepared.
【００２２】次に、図４に示すように、前記下金型４１
の基板受け面４１ａにモールドされる側を上にして位置
決めピンが位置決め孔に嵌るように基板２１を載せ、そ
の後前記上金型４０を下金型４１に当接させて両者を固
定する。Next, as shown in FIG.
The substrate 21 is placed so that the positioning pins are fitted into the positioning holes with the side to be molded on the substrate receiving surface 41a facing up, and then the upper mold 40 is brought into contact with the lower mold 41 to fix them.
【００２３】次に、上金型４０の複数の樹脂注入穴４０
ｂからキャビティ４０ａ内に加熱加圧されたモールド樹
脂材を注入して複数の半導体素子を一括モールドする。
次に、一括モールドが終了すると、下金型４１と上金型
４０との固着を解き、上金型４０のエジェクターピン挿
入穴４０ｄにエジェクターピンを押し込みながら下金型
４１から上金型４０を分離する。ここで、上金型４０に
は抜き勾配の傾斜部４０ｃが設けられているので、上金
型４０の分離時にモールド体は上金型４０から容易に抜
けて下金型上４１上にそのまま載った状態になってい
る。Next, a plurality of resin injection holes 40 of the upper mold 40 are formed.
A plurality of semiconductor elements are collectively molded by injecting a heated and pressurized mold resin material into the cavity 40a from b.
Next, when the collective molding is completed, the lower mold 41 and the upper mold 40 are released, and the upper mold 40 is removed from the lower mold 41 while pushing the ejector pins into the ejector pin insertion holes 40d of the upper mold 40. To separate. Here, since the upper mold 40 is provided with the draft inclined portion 40 c, the mold body easily comes off from the upper mold 40 and separates on the lower mold upper 41 as it is when the upper mold 40 is separated. It is in a state of being left.
【００２４】次に、前記モールド体２５（図７）を下金
型４１から外し、該モールド体２５の基板２１の前記裏
面導通端子３１（図６）を介してはんだボールを各半導
体素子のはんだパッドに接続する。Next, the mold body 25 (FIG. 7) is removed from the lower mold 41, and solder balls are applied to the solder of each semiconductor element through the back surface conduction terminals 31 (FIG. 6) of the substrate 21 of the mold body 25. Connect to pad.
【００２５】次に、図１に示すように、回転切断刃５０
を用いて前記モールド体２５を図５に示すように、モー
ルド樹脂２２ａでモールドされた個々の半導体装置６０
に切断する。ここで、図５（Ａ）は切断分離後の半導体
装置の斜視図、図５（Ｂ）は図５（Ａ）のＡーＡ’断面
図である。切断された半導体装置６０のモールド部２２
ａの側面には、従来のように各キャビティ周壁に設けら
れていた抜き勾配の傾斜による傾斜部が存在せず、それ
だけ樹脂の節約を図ることができる。Next, as shown in FIG.
As shown in FIG. 5, the individual semiconductor devices 60 molded with the molding resin 22a by using
Cut into pieces. Here, FIG. 5A is a perspective view of the semiconductor device after cutting and separation, and FIG. 5B is a cross-sectional view along AA ′ of FIG. 5A. Mold part 22 of semiconductor device 60 cut
On the side surface of “a”, there is no inclined portion due to the inclination of the draft provided in the peripheral wall of each cavity as in the related art, and the resin can be saved accordingly.
【００２６】以下、回転切断刃による切断の際に用いる
切断装置及び切断方法を図１を参照しながら説明する。
図１（Ａ）の斜視図及び及び図１（Ｂ）の側面図に示す
ように、半導体素子が一括モールドされたモールド体２
５は、ステンレス製のリング５１の下面に貼られたＰＶ
Ｃ製の接着テープ５２にモールド面を接着側、つまりは
んだボール側を表側として接着されている。Hereinafter, a cutting apparatus and a cutting method used for cutting with a rotary cutting blade will be described with reference to FIG.
As shown in the perspective view of FIG. 1A and the side view of FIG. 1B, a molded body 2 in which semiconductor elements are collectively molded.
5 is a PV affixed to the lower surface of the stainless steel ring 51.
The mold surface is adhered to an adhesive tape 52 made of C, with the solder ball side facing upward.
【００２７】そして、前記モールド体２５が接着された
接着テープ５２を図１（Ｂ）に示すように、多孔質セラ
ミックスで構成された吸着ステージ５３に載せて吸着固
定し、回転切断刃５０でモールド体２５を縦横に切断し
て個々の半導体装置に分離する。Then, as shown in FIG. 1B, the adhesive tape 52 to which the mold body 25 is adhered is placed on a suction stage 53 made of porous ceramics and fixed by suction. The body 25 is cut vertically and horizontally to separate into individual semiconductor devices.
【００２８】前記回転切断刃５０による切断は、例えば
隣接する半導体素子のはんだボールのピッチを認識しな
がらはんだボール間の中央部において切断を行う。この
ように切断を行っても前記基板に形成された隣接する半
導体素子のボンディングパッド間の中央部に沿って切断
することが可能となる。実際の切断は、前記接着テープ
５２の厚みが１２０μｍ程度あるので、５〜１０μｍほ
ど接着テープ５２をも切り込むことで個々の半導体装置
に完全に切断することができる。図１（Ａ）において、
符号５４は切断時の接着テープ５２の切断跡である。The cutting by the rotary cutting blade 50 is performed, for example, at the center between the solder balls while recognizing the pitch of the solder balls of adjacent semiconductor elements. Even if the cutting is performed in this manner, the cutting can be performed along the central portion between the bonding pads of the adjacent semiconductor elements formed on the substrate. In actual cutting, since the thickness of the adhesive tape 52 is about 120 μm, individual semiconductor devices can be completely cut by cutting the adhesive tape 52 by about 5 to 10 μm. In FIG. 1A,
Reference numeral 54 denotes a cut mark of the adhesive tape 52 at the time of cutting.
【００２９】回転切断刃による切断位置は、前記はんだ
ボールのピッチを認識するか、基板上に予め設けた切断
マークを認識して制御装置にデータを取り込み、該制御
装置に取り込まれたデータに基づいて回転切断刃の位置
を制御することにより、個々の半導体装置に切断分離す
ることができる。また、切断中は、個々の半導体装置を
纏めたまま純水を噴射して洗浄を行い、洗浄後は空気を
噴射して乾燥を行う。この場合、一個のスピンナーを切
断装置に付属させておくことにより、洗浄及び乾燥を同
時に行うことができる。The cutting position by the rotary cutting blade is determined by recognizing the pitch of the solder balls or recognizing a cutting mark provided in advance on the substrate and taking in data to the control device, based on the data taken into the control device. By controlling the position of the rotary cutting blade, the semiconductor device can be cut and separated into individual semiconductor devices. Further, during cutting, cleaning is performed by jetting pure water while the individual semiconductor devices are kept together, and after cleaning, air is jetted to dry. In this case, washing and drying can be performed simultaneously by attaching one spinner to the cutting device.
【００３０】本発明の方法でモールド体を切断すると、
４辺を切断することでその形状が左右対称になり、切断
後の半導体装置の外形から１ピンの位置が判明できなく
なるので、個々の半導体装置に切断した後、前記回転切
断刃を用いて１つのコーナを斜めにカットするか、１辺
をベベルカットするか、一辺の内側上面にハーフカット
を施す。これによって実装時の方向判定が容易になる。
さらに、エッジが直角だと欠けが発生し易くなるので、
切断ラインに沿ってベベルカットした後、切断するのが
好適である。この場合は１ピンの位置マークとしてモー
ルド面の所定箇所ににマークを付すると良い。When the mold body is cut by the method of the present invention,
By cutting the four sides, the shape becomes bilaterally symmetric, and the position of pin 1 cannot be determined from the outer shape of the cut semiconductor device. One corner is cut diagonally, one side is bevel cut, or a half cut is made on the inner upper surface of one side. This facilitates direction determination during mounting.
Furthermore, if the edge is at a right angle, chipping tends to occur,
It is preferable to cut after bevel cutting along the cutting line. In this case, a mark may be attached to a predetermined position on the mold surface as a position mark of one pin.
【００３１】[0031]
【発明の効果】このように、本発明の切断方法は、一括
してモールドされた半導体装置を切断刃を用いて個々の
半導体装置に切断するので、従来のようにダイとパンチ
のような大掛かりな装置を必要とせず、切断の効率が向
上する。また、モールド装置の金型は、１個のキャビテ
ィと該キャビティに通じる樹脂注入穴を備えるだけであ
るから、従来のようにランナーなどは存在しないため、
樹脂を迅速且つ均一に注入することが可能となり、また
構造も簡単になる。さらに、一個のキャビティを有する
金型を備えたモールド装置で複数の半導体素子を一括モ
ールドし、このモールド体を切断刃で切断するので、モ
ールド装置及び切断装置の構造が簡単になり、半導体装
置の製造工程を簡素化できる。As described above, according to the cutting method of the present invention, a semiconductor device which has been collectively molded is cut into individual semiconductor devices by using a cutting blade. This eliminates the need for a simple device and improves cutting efficiency. In addition, since the mold of the molding apparatus only has one cavity and a resin injection hole communicating with the cavity, there is no runner or the like as in the related art.
The resin can be quickly and uniformly injected, and the structure is simplified. Furthermore, since a plurality of semiconductor elements are collectively molded by a molding apparatus having a mold having one cavity and the molded body is cut by a cutting blade, the structure of the molding apparatus and the cutting apparatus is simplified, and The manufacturing process can be simplified.
【図１】本発明の切断装置の要部斜視図及び要部側面図
である。FIG. 1 is a perspective view of a main part and a side view of a main part of a cutting device of the present invention.
【図２】本発明のモールド装置の上金型の要部平面図で
ある。FIG. 2 is a plan view of a main part of an upper mold of a molding apparatus according to the present invention.
【図３】本発明のモールド装置の下金型の要部斜視図で
ある。FIG. 3 is a perspective view of a main part of a lower mold of the molding apparatus according to the present invention.
【図４】本発明のモールド装置の下金型にモールドする
複数の半導体素子を載せた際の要部側面図である。FIG. 4 is a side view of a main part when a plurality of semiconductor elements to be molded are mounted on a lower mold of the molding apparatus of the present invention.
【図５】本発明の切断装置にて切断分離された半導体装
置の斜視図及び断面図である。FIG. 5 is a perspective view and a cross-sectional view of a semiconductor device cut and separated by the cutting device of the present invention.
【図６】本発明のモールド装置でモールドされる半導体
素子を絶縁基板に配設した要部平面図である。FIG. 6 is a plan view of a main part in which a semiconductor element to be molded by the molding apparatus of the present invention is disposed on an insulating substrate.
【図７】本発明モールド装置にて一括モールドされた半
導体素子のモールド体の要部斜視図及び断面図である。FIGS. 7A and 7B are a perspective view and a cross-sectional view of a main part of a molded body of a semiconductor element which is collectively molded by the molding apparatus of the present invention.
【図８】従来のモールド装置にて一括モールドされた半
導体素子のモールド体の要部斜視図及び断面図である。8A and 8B are a perspective view and a cross-sectional view of a main part of a molded body of a semiconductor element which is collectively molded by a conventional molding apparatus.
【図９】従来の切断装置にて切断分離された半導体装置
の斜視図及び断面図である。FIG. 9 is a perspective view and a cross-sectional view of a semiconductor device cut and separated by a conventional cutting device.
２０・・半導体素子 ２１・・絶縁基板 ２５・・複数
の半導体素子が一括モールドされたモールド体 ４０・
・上金型 ４０ａ・・上金型のキャビティ ４１・・下金型 ５０・・回転切断刃 ５３・・多孔
質セラミックスからなる吸着ステージ ６０・・半導体
装置20 semiconductor element 21 insulating substrate 25 molded body 40 in which a plurality of semiconductor elements are collectively molded
-Upper mold 40a-Upper mold cavity 41-Lower mold 50-Rotary cutting blade 53-Adsorption stage 60 made of porous ceramics-Semiconductor device
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/301 Ｈ０１Ｌ 21/78 Ｆ 21/78 21/80 // Ｂ２９Ｌ 31:54 Ｆターム(参考） 3C027 QQ00 4F202 AH33 CA12 CB17 CK11 CK89 CS10 4F206 AH33 JA02 JB17 JF01 JF23 JQ81 JW23 5F061 AA01 BA03 CA21 CB13 DA01 DA06 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/301 H01L 21/78 F 21/78 21/80 // B29L 31:54 F term (Reference) 3C027 QQ00 4F202 AH33 CA12 CB17 CK11 CK89 CS10 4F206 AH33 JA02 JB17 JF01 JF23 JQ81 JW23 5F061 AA01 BA03 CA21 CB13 DA01 DA06
Claims (7)
刃で切断して分離できる間隔をおいて配設した絶縁基板
を収容し、一括してモールドするキャビティを備えるこ
とを特徴とするモールド装置。1. A molding apparatus comprising: a cavity for accommodating an insulating substrate disposed at an interval capable of cutting and separating a plurality of semiconductor elements to be molded by a cutting blade, and molding them collectively.
刃で切断して分離できる間隔をおいて配設した絶縁基板
を収容し、モールド材注入孔及び該モールド材注入孔に
連なる１つのキャビティを備える金型と、前記絶縁基板
を装填する金型とを備えることを特徴とするモールド装
置。2. An insulating substrate provided at an interval capable of cutting and separating a plurality of semiconductor elements to be molded by a cutting blade, accommodating a molding material injection hole and one cavity connected to the molding material injection hole. A mold apparatus comprising: a mold provided with the mold; and a mold for loading the insulating substrate.
刃で切断して分離できる間隔をおいて配設した絶縁基板
を一つのキャビティ内に収容し、該キャビティ内にモー
ルド材を加熱圧入し、一括してモールドすることを特徴
とするモールド方法。3. A plurality of semiconductor elements to be molded are cut by a cutting blade, and an insulating substrate provided at an interval capable of being separated is housed in one cavity, and a molding material is heated and pressed into the cavity. A molding method characterized by performing molding all at once.
刃で切断して分離できる間隔をおいて配設した絶縁基板
を一つのキャビティ内に収容し、該キャビティ内にモー
ルド材を加熱圧入し、一括してモールドされた複数の半
導体装置を切断刃にて個々の半導体装置に切断すること
を特徴とするモールドされた複数の半導体装置の切断方
法。4. An insulating substrate provided at an interval capable of cutting and separating a plurality of semiconductor elements to be molded by a cutting blade is accommodated in one cavity, and a molding material is heated and pressed into the cavity. A method for cutting a plurality of molded semiconductor devices, wherein the plurality of molded semiconductor devices are cut into individual semiconductor devices with a cutting blade.
特徴とする請求項４のモールドされた複数の半導体装置
の切断方法。5. The method for cutting a plurality of molded semiconductor devices according to claim 4, wherein the cutting blade is a rotary cutting blade.
刃で切断して分離できる間隔をおいて配設した絶縁基板
を一つのキャビティ内に収容し、該キャビティ内にモー
ルド材を加熱圧入し、一括してモールドする工程と、 前記一括してモールドされた複数の半導体装置を切断刃
にて個々の半導体装置に切断する工程とを備えることを
特徴とする半導体装置の作製方法。6. An insulating substrate provided at an interval capable of cutting and separating a plurality of semiconductor elements to be molded by a cutting blade is accommodated in one cavity, and a molding material is heated and pressed into the cavity. A method of manufacturing a semiconductor device, comprising: a step of collectively molding; and a step of cutting the plurality of semiconductor devices molded together into individual semiconductor devices with a cutting blade.
特徴とする請求項６の半導体装置に作製方法。7. The method according to claim 6, wherein the cutting blade is a rotary cutting blade.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10198201A JP2000025074A (en) | 1998-07-14 | 1998-07-14 | Apparatus and method for molding, method for cutting molded semiconductor apparatus, and manufacture of semiconductor apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10198201A JP2000025074A (en) | 1998-07-14 | 1998-07-14 | Apparatus and method for molding, method for cutting molded semiconductor apparatus, and manufacture of semiconductor apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000025074A true JP2000025074A (en) | 2000-01-25 |
Family
ID=16387170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10198201A Pending JP2000025074A (en) | 1998-07-14 | 1998-07-14 | Apparatus and method for molding, method for cutting molded semiconductor apparatus, and manufacture of semiconductor apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000025074A (en) |
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