JP2000022694A - Cell exchange device, address managing method and cell information managing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a multicast function and to operate it at high speed by providing a managing means for holding the address information discriminated that is not held by any storage means and that has been outputted from any storage means as address information capable of being assigned to a new input cell. SOLUTION: The address managing device is provided with port address managing device 1100-1 to 1100-4 for managing an address pointer for each port, idle address managing device 1200 for managing an idle address pointer, and queue control unit 1300 for controlling these managing devices. A port address memory 1110 of each managing device 1100 holds the address pointer for each port in the order of arrival and an address comparator 1120 compares the address pointer held in a port queue with the address pointer outputted from the port queue of the other port address managing device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to digital communication,
In particular, in ATM communication, a cell switching apparatus for exchanging cells based on exchange information attached to a cell, exchange information attached to a cell, and address information indicating a storage position of the cell in a cell storage means in the cell exchange apparatus. The present invention relates to an address management device and a cell information management method for managing the information in association with each other.

[0002]

2. Description of the Related Art In an ATM switching system for exchanging packets called fixed-length cells, a common buffer type switch has a higher buffer use efficiency than other types of switches such as an input buffer type switch and an output buffer type switch. It is said to be expensive. However, it has been difficult for the common buffer type switch to realize the multicast function.

FIG. 56 shows an example of a basic configuration of a cell switching apparatus for realizing a multicast function. FIG. 57 shows an example of a conventional address management device used for this cell switching device (Japanese Patent Laid-Open No. 7-235932).

[0004] Basically, the cell switching device is composed of an address management device 10000, an output information processing device 200, a cell storage device 300, input processing devices 400-1 to 400-m, and output processing devices 500-1 to 500-n. , Multiplexing device 600,
It is composed of a separation device 700.

[0005] The input processing devices 400-1 to 400-m are:
The destination information attached to the cell is extracted from the input cell and transferred to the output information processing device 200. Also, the input cell is transferred to the multiplexer 600.

[0006] The output information processing device 200 processes the destination information transferred from the input processing device 400 and transfers it to the address management device 10000.

[0007] The address management device 10000, according to the destination information transferred from the output information processing device 200,
A write address of the input cell is generated and transferred to the cell storage device 300.

[0008] The cell storage device 300 writes the cell transferred from the multiplexing device 600 to the address generated by the address management device 10000. Also, the address management device 1
The cell of the read address generated in 0000 is read and transferred to the separation device 700.

The output processing devices 500-1 to 500-n are:
The cell transferred from the separation device 700 is output.

[0010] The multiplexing device 600 multiplexes the cells transferred from the input processing device 400 and transfers the multiplexed cells to the cell storage device 300.

The separating device 700 separates the cells transferred from the cell storage device 300 and transfers the cells to the output processing device 500.

As shown in FIG. 57, a conventional address management device 10000 includes destination information registers 11100-1 to 11100- for storing destination information added to a cell.
k, address pointer registers 11300-1 to 11300-k for storing addresses at which cells are stored, and unit control devices 11200-1 to 11200-k for controlling a destination information register and an address pointer register, respectively. Address management units 11
000-1 to 11000-k, a search circuit 12000, an address pointer output circuit 13000, and a destination information input circuit 14000.

This conventional address management device 10000
Controls the address of the cell switching device illustrated in FIG. 56 by performing three operations of an input operation, an output operation, and a shift operation.

The input operation, output operation, and shift operation will be described below.

(Input operation) In the input operation, the "empty" address management unit is moved downward (11000 in FIG. 57).
-1 (that is, the address management unit corresponding to the oldest cell), and the value of the address pointer of the address management unit that first matches the condition is output as the write address of the input cell. The destination information of the cell input to the destination information register of the address management unit is written.

FIG. 58 shows an example of the input operation. FIG.
It has four output ports (# 1, # 2, # 3, # 4)
An example is shown in an address management device used for a switch having a cell buffer capable of storing eight cells.

In the example of FIG. 58, one bit is assigned to each destination (Destination) in the destination information register. That is, here, when the bit corresponding to the destination i of each address management unit is 1, it indicates that the cell corresponding to the address management unit is going to i. For example, the contents of the column indicated by output port # 1 in FIG. 58 indicate whether each address management unit is destined for output port # 1. For example, in the address management unit # 4, the bit corresponding to the output is “0001”.
However, this means that the data is output to the output port # 4.

The address management unit indicated as "empty" means "empty". In the example of FIG. 58A, since the four address management units # 1 to # 4 are not “empty”, this address management device
Holds information about one cell.

"Address Pointer"
It means the address where the cell is written. The value of the address has a one-to-one correspondence with the address of the cell storage device 300. For example, the cell corresponding to the address management unit # 4 is stored at the address “3”. Fig. 58
In the example of (a), cells are held at addresses corresponding to the address management units # 1, # 2, # 3, and # 4.

The order of arrival of each cell is given by the location in the address management unit of the address management unit to which the cell corresponds. In the example of FIG. 58, the one below is old. Therefore, the cell corresponding to the address management unit # 1 is the oldest.

FIG. 58A shows a state before the input operation. Before the input operation is performed, the address management units that are not “empty” need to be packed in the lower part.

In the input operation, an "empty" address management unit is searched from the bottom (that is, the oldest one). First, the address management unit # 5 having “4” as the address pointer is searched. The input destination information (“1010” in this example) of the cell is stored in the address management unit. This state is shown in FIG.
Shown in

At this time, the address pointer "4" is output, and the input cell is stored at the address indicated by the address pointer "4".

With the above operation, the address management unit corresponding to the newly input cell can be placed on the address management unit corresponding to the old cell, and the arrival order can be maintained.

(Output Operation) In the output operation, an address management unit having a destination destined for the port to be output is set to 1 from the bottom.
Search one by one, and first output the address pointer value of the address management unit that matches the search condition,
The corresponding destination information is deleted (here, it is set to 0).

FIG. 59 shows an example of the output operation. In the output operation, first, an address management unit having destination information for the corresponding output port is searched from below. In the example of FIG. 59 (a), the output port # 1 has an address pointer "0" for the address management unit # 1, and the output port # 2 has an address pointer "1" for the output port # 2. For the output port # 3, the address management unit # 1 having the address pointer "0", and for the output port # 4, the address management unit # 3 having the address pointer "2". Are respectively searched.

Then, the value of each address pointer is transferred to the cell buffer, and the corresponding cell is output. Also, the destination information for the read cell is reset to 0, and changes as shown in FIG.

(Shift Operation) In the shift operation, in order to reduce the number of address management units which have become "empty" by the output operation, an "empty" address management unit is searched for, and the address management after the searched address management unit is performed. Unit (including the searched address management unit)
And input the value of the searched address pointer of the address management unit to the uppermost address pointer register.

FIG. 60 shows an example of the shift operation. In the shift operation, an "empty" address management unit is searched from below. In the example of FIG. 60A, the address management unit # 3 having the address pointer “2” is searched. The contents after the searched address management unit are shifted, and the value “2” of the address pointer of the searched address management unit is input to the uppermost (in this example, # 8) address management unit. As a result, the internal state of the address management device changes as shown in FIG.

The multicast function is realized by using the above address management device.

However, such a conventional address management device has the following problems.

That is, in the output operation, a procedure for searching for an address management unit satisfying the search condition and outputting an address pointer held corresponding to the address management unit is performed. However, it is necessary to sequentially search all address management units until the oldest cell is searched. If this search processing is not completed, the corresponding address pointer cannot be output, which speeds up the processing. I was blocking.

Further, a shift operation which does not directly affect the input of the cell or the output of the cell is necessarily required, and this shift operation causes a time for waiting for the input / output operation of the cell switching apparatus. There is also a problem that the operation speed of the cell switching device is reduced.

[0034]

As described above, in the conventional address management device for realizing the multicast function,
There is a problem that it is difficult to perform a high-speed operation.

The present invention has been made in view of the above circumstances, and has as its object to provide an address management device which can realize a multicast function and can operate at high speed.

[0036]

Means for Solving the Problems The present invention (claim 1) provides:
Cell storage means shared by a plurality of output destinations for temporarily storing input cells, and cells stored in the cell storage means to one or more output destinations determined based on the header information A cell exchange comprising: means for exchanging; and address management means for managing correspondence between address information (for example, an address pointer) indicating a storage location in the cell storage means for each cell and one or a plurality of output destinations of the cell. The device, wherein the address management means is storage means provided for each output destination, and holds address information assigned to an input cell having an output destination corresponding to itself, and holds the address information according to an instruction. Storage means for outputting the address information stored in the storage means, and address means output from storage means other than the storage means corresponding to the storage means provided for each output destination. Detecting means for detecting whether or not the same information as the information is stored in the storing means corresponding to the information processing apparatus; and any one of the storage means based on the detection result of the detecting means provided for each output destination. The address information output from the means, which is found not to be held in any of the storage means (that is, address information indicating an empty storage position where no cell is stored in the cell storage means) And management means for holding as address information that can be assigned to a new input cell.

According to the present invention (claim 2), the inputted cell is
For a cell switching device that temporarily stores in a cell storage unit shared by a plurality of output destinations and then switches to one or more output destinations determined based on the header information, the cell storage unit stores the cell storage for each cell. An address management device for managing a correspondence between address information (for example, an address pointer) indicating a storage position in the means and one or a plurality of output destinations of the cell, wherein the storage means is provided for each output destination; Storage means for holding the address information assigned to the input cell having the output destination corresponding to itself and outputting the held address information in accordance with the instruction; and detecting means provided for each output destination. To detect whether or not the same address information output from the storage means other than the storage means corresponding to itself is stored in the storage means corresponding to itself. It is determined that the address information is output from any one of the storage units and is not stored in any one of the storage units based on the detection result of the detection unit provided for each output destination. Management means for storing the address information as address information that can be assigned to a new input cell.

[0038] Preferably, means for holding address information that can be assigned to a new input cell, and assigning selected address information from the held address information to the input cell, Means for holding the obtained address information in the storage means corresponding to one or a plurality of output destinations determined based on the header information of the input cell.

Preferably, the storage means outputs the stored address information in the order of input, and the means for allocating selects the stored address information in the order of input. .

Preferably, there is provided means for performing at least one of inputting address information to the storage means for each output destination and outputting address information from the storage means for each output destination in parallel for each output destination. It may be further provided.

According to the present invention (claim 6), the inputted cell is
For a cell switching device that temporarily stores in a cell storage unit shared by a plurality of output destinations and then switches to one or more output destinations determined based on the header information, the cell storage unit stores the cell storage for each cell. Address information (for example, an address pointer) indicating a storage location in the means, one or more output destinations of the cell (for example, an output port number, and when there are a plurality of output destinations in the same output port, the output destination); A cell information management method for managing the correspondence of the input cell, wherein the address information assigned to the input cell has a one-to-one correspondence with one or a plurality of output destinations determined based on header information of the input cell. The address information is output from the storage means corresponding to the designated output destination, and the same output address information is still stored in the other storage means. Detecting whether it is held Te,
When it is determined that the input information is not stored in any of the storage units, the address information is stored as address information that can be assigned to a new input cell.

The output destination is, for example, an output port. In the present invention, the output port is further added to a virtual channel (V
C) It is also applicable to those managed for each class or each class.

The present invention can be applied not only to ATM cells but also to those which handle, for example, packets of variable length such as IP packets.

The present invention is not limited to the switching device, but can be applied to other devices such as a separation device (demultiplexer).

The invention relating to each apparatus described above is also valid as an invention relating to a method, and the invention relating to a method is also valid as an invention relating to an apparatus.

According to the present invention, the address information of the cell waiting for output is managed separately for each output destination, and another (corresponding to the output destination) is stored for each storage means used for the management. Since it is detected whether or not the same address information output from the means is held (the same address information output from itself is not stored in itself), the multicast function is used. Can be realized, the input operation and the output operation of the address information can be sped up, the shift operation can be absorbed in the output operation, and the search for the empty address information can be sped up. Notification processing can be sped up).

Further, according to the present invention, it is possible to operate the multicast function in parallel, thereby realizing higher-speed operation.

[0048]

Embodiments of the present invention will be described below with reference to the drawings.

In the following, when there are a plurality of devices having the same configuration, when distinguishing each of them, for example, one device is used.
It is assumed that a common reference number, such as 100-1, 1100-2,..., Is followed by a “-(hyphen) number”. In addition, when there are a plurality of devices having the same configuration and the like, and there is no distinction between them, there is a case where only a common reference number is shown without adding a “−number”.

(First Embodiment) First, a cell switching device and its address management device according to a first embodiment of the present invention will be described.

The description will be made assuming that the cell switching apparatus according to the present embodiment uses the one illustrated in FIG. 56 (of course, another cell having the same function as this may be used). That is, the address management device according to the present embodiment can be used for the cell switching device illustrated in FIG. 56 or a device having the same function as this.

FIG. 1 shows a configuration example of an address management device 100 according to the present embodiment. Although FIG. 1 illustrates one corresponding to four output ports, the same configuration can be applied to a case where the number of output ports is three or less or five or more.

This address management device 1100 manages an address pointer for each port.
-1 to 1100-4, a vacant address management device 1200 for managing a vacant address pointer, each port address management device (1100-1 to 1100-4), and a queue control device 130 for controlling the vacant address management device 1200
0 is provided.

The address pointer is information capable of specifying an address in the cell storage device to which the cell is written, and is an actual address value in the cell storage device or a value associated one-to-one with the actual address. is there.

Each port address management device 1100 has a port address memory 111 comprising a logical queue (port queue) provided for each port for holding an address pointer for each port in the order of arrival.
0, an address comparison device 1120 for comparing an address pointer held in this port queue with an address pointer output from a port queue of another port address management device.

The operation of the address management device shown in FIG. 1 will be described.

In this embodiment, a queue of address pointers is prepared for each output port in order to realize multicasting. For a multicast cell, an address pointer is input to a queue of address pointers for each of a plurality of output ports. Therefore, the cell written to one address pointer at the time of reading is read from a plurality of output ports, so that multicast can be realized.

In this embodiment, since one address pointer is transferred to a plurality of queues, it is necessary to identify an address pointer that does not hold a cell, that is, is “empty”. For this purpose, the address management device searches the queue for each output port to determine whether the address pointer read by the output is held in the queue of another address pointer, and holds it in the other address pointer. If not, it identifies that it is available as a free address pointer.

First, the operation of writing the address pointer into the port address management device at the time of cell input will be described.

In the write operation, the control circuit (the output information processing device 200 in the example of FIG. 56) of the cell switching device sends the cell buffer (cell storage device) in the cell switching device to the queue control device 1300 of the address management device. ), Output port information obtained from the destination information of the cell to be written and a write instruction signal are sent. The queue control device 1300 receiving these transfers a read instruction signal to the free address management device 1200. Free address management device 12
00 transfers the free address pointer to each port address management device 1100. At the same time, the queue control device 130
0 sends a write instruction signal to the corresponding port management device 1100 according to the output port information of the cell to be written. Upon receiving the write instruction signal, the port address management device 1100 stores the address pointer transferred from the free address management device 1200 in the port address memory 1.
Write to 110.

Next, the read operation will be described.

In the read operation, the control circuit of the cell switching device (the output information processing device 200 in the example of FIG. 56) sends the information of the output port to be read and the read instruction signal to the queue control device 1300 of the address management device. Is sent. The queue control device 1300 instructs the port address management device 1100 corresponding to the specified output port to output an address. The port address management device 1100 outputs an address pointer corresponding to the oldest cell to the other port address management device 1100, the free address management device 1200, and the cell storage device (the cell storage device 300 in the example of FIG. 56). Address comparison device 112
At 0, the contents of the port address memory 1110 are compared with the value of the transferred address pointer, and the result is transferred to the queue control device 1300. Queue control device 130
If 0 indicates that none of the address comparison devices 1120 of the port address management device 1100 has a matching address pointer, a write instruction is issued to the free address management device 1200.

Next, an example of the operation in this embodiment will be described in detail with reference to FIGS.

In the examples shown in FIGS. 2 to 10, it is assumed that the cell buffer size is 8. Therefore, the number of entries of the port address memory of each port address management device 1100 and the number of entries of the address pointer of the free address management device 1200 are both “8”. 2 to 8, there are four output ports, the port address management device 1100-1 is assigned to the output port # 1, the port address management device 1100-2 is assigned to the output port # 2, and the port address management is performed. The device 1100-3 corresponds to the output port # 3, and the port address management device 1100-4 corresponds to the output port # 4 (# 1, # 2, # 3, and # 3 described in FIG. 2).
The correspondence is shown in # 4). In this example, the memory is a port address memory 1 to represent the FIFO operation.
110 is expressed such that the old one is at the bottom, and the free address management device 1200 is expressed so that the old one is at the top.

FIG. 2 shows an initial state of the address management device. In the initial state, all the address pointers of the cell buffer are held in the empty address management device 1200. Nothing is held in the port address memory 1110 of the port address management device 1100.

First, an example of the write operation will be described. FIG. 3 shows a change from the state shown in FIG. 2 in the case where cells directed to output port # 1 and output port # 3 are input. At this time, a read request is issued from the queue control device 1300 to the free address management device 1200, and the address pointer “0” is read. The port address management device 1100-1 corresponding to the output port # 1
Address management device 1 corresponding to and output port # 3
A write request is issued to the port address management device 100-3, and the address pointer “0” read from the free address management device 1200 is written to the port address management device 1100-1 and the port address management device 1100-3.

Similarly, FIG. 4 shows the operation when cells to output port # 1 and output port # 2 are input.
Shows an operation when a cell destined for output port # 4 is input, and FIG. 6 shows an operation when a cell destined for output port # 4 is input.

Next, an example of the read operation will be described.

FIG. 7 shows a change when the output port # 1 is read from the state shown in FIG. In this case, a read request is issued from the queue control device 1300 to the port address management device 1100-1 corresponding to the output port # 1. Port address management device 11
Upon receiving the read request, 00-1 reads the oldest address pointer. In this case, "0" is read. Then, the address pointer is transferred to the other port address management devices 1100-2 to 1100-4 and the free address management device 1200. Port address management device 1100-2 to port address management device 110
0-4 respectively compare the transferred address pointer with the contents in the port address memory, and transfer the comparison result to the queue control device 1300.

In the example of FIG. 7, the port address management device 1
100-2 and the port address management device 1100-4
Since it does not have the address pointer "0", the fact that it does not have the address pointer 0 is transferred to the queue control device 1300, and the port address management device 1100-3 queues that it has the address pointer "0" because it has the address pointer 0. Transfer to control device 1300. Since the address pointer “0” is still being used by the port address management device 1300 and cannot be reused as a free address pointer, the queue control device 1300 does not issue a write request to the free address management device 1200.

Similarly, FIG. 8 shows a change when the output port # 2 is further read. In this case, the address pointer “1” is output, and since the port address management device 1100-1 is using the address pointer “1”, it is not written to the free address management device 1200.

FIG. 9 shows a change when the output port # 3 is further read. In this case, the address pointer “0” is output. Address pointer "0"
Are the other port address management devices 1100-1 and 110
Since it is not used in 0-2 and 1100-4, it can be used as a free address pointer. Therefore, the queue control device 1300 issues a write request to the free address management device 1200, and the free address management device 1200 writes the address pointer “0”.

FIG. 10 shows a change when the output port # 4 is further read. In this case, the address pointer “2” is output. Since the address pointer “2” is not used by another port address management device 1100, the free address management device 1200
Write the address pointer "2".

In this way, multicast can be realized.

Next, the configuration of the port address management device 1100 will be described.

The function of the port address management device 1100 is to hold an address pointer as a FIFO,
That is, the contents of the stored address pointer are compared.

Here, the port address management device 110
As an example of the configuration of 0, a port address management device 1100 configured using a shift register will be described.

FIG. 11 shows a port address management device 1100.
An example of the configuration will be described.

The port address management device 1 shown in FIG.
Reference numeral 100 denotes a plurality of memory units 2110 for holding address pointers, a plurality of unit controllers 2120 for controlling the memory units 2110, and a plurality of address comparison units 2130 for comparing address pointers.
And the output of the address comparison unit 2130 (comparison result)
And a comparison result totaling device 2140 that performs totaling.

The memory unit 2110 holds an address pointer and a valid bit. The valid bit indicates whether the memory unit 2110 holds a valid address pointer. At the time of writing, under the control of the unit control device 2120, the address pointer transferred from the free address management device 1200 is fetched.
At the time of reading, a shift operation is performed under the control of the unit control device 2120.

The unit control unit 2120 controls the memory unit 2110 according to the control information transferred from the queue control unit 1300. That is, at the time of writing, an instruction is given to write the contents of the address pointer to the empty memory unit 2110, and at the time of reading, the shift operation is performed. To detect vacancies, two adjacent
The valid bits of one memory unit 2110 are used.
When “H” means valid and “L” means invalid,
When the lower unit is “H” and the upper unit is “L”, writing is instructed to the upper unit. By controlling in this way, it is possible to hold the address pointer at the bottom and operate as a FIFO.

The address comparison unit 2130 compares the contents of the address pointer held in the corresponding memory unit with the address pointer read from another port address management device 1100 and detects whether or not they match. I do.

The comparison result totaling device 2140 totalizes the output of the address comparing unit 2130, and instructs the queue control device 1300 whether or not the same address pointer as the address pointer read from the other port address management device 1100 is held. Notice.

FIG. 12 shows a port address management device 110.
0 shows a detailed configuration example. This configuration example is an example that can hold one valid bit and four four-bit address pointers. FIG. 13 is an enlarged view of a portion corresponding to one memory unit in FIG.

Although the clock and the reset are not shown in FIG. 12, the flip-flop operates in synchronization with the clock, and the content is reset by the reset.

Each memory unit 2110 is composed of a set of a plurality of flip-flops 2111 and a selector 2113. The flip-flop 2111 fetches an output signal from the selector 2113 according to a control signal WE of the unit control device 2120. The selector 2113 is connected to the output from the upper memory unit and the free address management device 1.
The input of the address pointer output from 200 is switched by a control signal transferred from the queue control device 1300. That is, when writing, the address pointer output from the free address management device 1200 is
In the case of reading, an output from the memory unit in the upper stage is output to the flip-flop 2111. In FIG. 12, a flip-flop 2111-0 and a selector 2113-0 are used for valid bits, and the flip-flops 2111-1 to 2111-4 and the selector 2113 are used.
-1 to 2113-4 are used as address pointers.

Each unit controller 2120 has a three-input AND gate 2121 and a two-input OR gate (O / O).
R) gate 2123. Queue control device 1
The write enable signal from 300, the inverted signal of the output from the effective bit of the lower memory unit 2110, and the signal from the effective bit of the memory unit 2110 that performs control are connected to the input of the AND gate 2121. The output of the AND gate 2121 is connected to the OR gate 2123. A read control signal from the queue control device 1300 is input to the other input of the OR gate 2123. The output (WE) of the OR gate is input to the control input of the flip-flop 2111 of the memory unit 2110.

Each address comparing unit 2130 has two input XNOR gates 2131-1 to 2131-4 of the same number as the number of bits of the address pointer and an AND of their outputs.
And an AND gate 2133 that performs D. XNO
The output signal of the address pointer of the memory unit 2110 and the address pointer transferred from the other port address management device 1100 or free address management device 1200 are input to the R gate 2131, and the AND gate 2133 determines whether or not they match. Output to The output of the AND gate 2133 is output to the comparison result totaling device 214.
0 is transferred.

The comparison result totaling device 2140 comprises OR gates 2141-1, 2141-2, and 2142-1. In the example shown in FIG. 12, since there are four inputs, 2
The input OR gates are connected in two stages to form a hierarchical structure.

Next, another configuration of the port address management device 1100 will be described.

Here, the port address management device 110
As another example of the configuration of the port address management device 1100, a port address management device 1100 configured using a memory will be described.

FIG. 14 shows a configuration example of a port address management device 1100 using a memory.

The port address management device 1 shown in FIG.
100 includes a memory control device 3100 and a memory 3200.

The memory 3200 includes a memory controller 320
0, and one of a read operation and a write operation is executed by “R / W”. At the time of the write operation, the data given to the terminal "D" is stored at the address given to the terminal "A". At the time of the read operation, the content held at the address given to the terminal “A” is output to the terminal “D”.

The memory control device 3100 stores the control information transferred from the queue control device 1300 and the other port address management device 1100 or the free address management device 1
200 using the address pointer information sent from
The memory 3200 is controlled.

The memory control device 3100 includes a memory 320
In order to control 0 as a FIFO, the memory 3200 is controlled as a ring buffer. In addition, it has a function of reading the contents of the memory 3200 and comparing it with the transferred address pointer to compare the address pointer.

Next, an example of the operation of the memory control device 3100 will be described with reference to FIGS.

In the example of FIGS. 15 to 22, the memory 3200
Has eight entries from address “0” to address “7”. “WP” is the value of the write pointer, “R”
“P” is the value of the read pointer, “NUM” is the memory 32
00 represents the number of address pointers stored in 00.

FIG. 15 shows an initial state of the memory control device 3100 and the memory 3200. In an initial state, valid information is not stored in the memory 3200. Further, WP and RP both indicate the address “0” and the number of address pointers is 0, so NUM is 0.

FIG. 16 shows a state in which the address pointer “Address Pointer 1” is written from FIG. The address pointer is written to the address “0” indicated by the WP, and the WP is incremented by one to “1”. NUM indicating the number of address pointers is incremented by 1 to "1".

Similarly, “Address Pointe”
r 2 ”to“ Address Pointer 4 ”
Is written as shown in FIG.

When reading is performed from this state, FIG.
It changes like 8. That is, the value of the address pointer “Address” held at the address indicated by the RP
Pointer 1 ”is output, the value RP of the read pointer is incremented by one to“ 1 ”, and the value of NUM indicating the number of address pointers is decremented by one to“ 3 ”.

Similarly, when reading is performed, the state changes as shown in FIG. 19, and the number of the stored address pointers becomes zero. If further reading is performed in this state, an invalid value will be read, so the number of address pointers NUM is 0.
In such a case, it is necessary to limit the reading.

When writing is performed from the state of FIG. 19, FIG.
It will be like 0. That is, the WP is stored in the memory 320
It is the same as the maximum address of 0. If further writing is performed in this state, the state changes as shown in FIG. That is, the write address pointer WP changes to 0.
As described above, the transition of the write address pointer to the minimum value of the address after the maximum value of the address has been made can constitute a ring buffer.

When writing is further performed, as shown in FIG.
The address pointer is held up to the capacity of the memory 3200. If further writing is performed from this state, the valid address pointer (“Address Pointer 5” in this example) held before that is destroyed. Therefore, when the number of address pointers held in the memory 3200 becomes equal to the capacity of the memory 3200, it is necessary to limit writing so that writing is not performed.

Next, the operation for comparing addresses will be described. When comparing addresses, the memory 32
All valid address pointer values held in 00 are read, and the read address pointer is compared with the value of the address pointer output from another port address management device 1100. For example, when comparing addresses in the state of FIG. 20, when the address pointer (Address) held at the address indicated by the RP is
Pointer 5), the address pointer (Address) held at the address obtained by subtracting 1 from WP.
The comparison is performed up to Pointer 7).

FIG. 23 shows a configuration example of the memory control device 3100 that realizes such an operation.

Memory control device 3100 shown in FIG.
Is a counter 3101 for indicating a write address,
Counter 3105 for indicating the read address, counter 310 for indicating the number of address pointers in the memory
3. Counter 310 used when comparing addresses
7. Comparator 3141 for checking whether the number of address pointers is equal to the number of entries in the memory, and comparator 314 for checking whether the number of address pointers is 0
3. A comparator 3145 for comparing the size of the counter 3107 when comparing the address with the write pointer 3101, and comparing the address pointer sent from the other port management device 1100 with the address pointer read from the memory 3200. 3147, a subtractor 3149 for reducing the value of the write pointer by 1, a three-state buffer 3131 for outputting the output of the write pointer 3101 to the address of the memory 3200, and the output of the read pointer 3105 to the address of the memory 3200. A three-state buffer 3133 for outputting, a three-state buffer 3135 for outputting the output of the address comparison counter 3107 to the address of the memory 3200, and a three-state buffer 3135 for outputting the output of the address pointer to the data of the memory 3200.
State buffer 3137, 2-input AND gate 3111 for generating control signal for write pointer 3101, 2-input AND gate 3113 for generating control signal for read pointer 3105, counter 3107 for address comparison
Is held by the flip-flop 3151 which holds the state of.

In FIG. 23, “Write” is a write control signal transferred from the queue control device 1300, “Read” is a read control signal transferred from the queue control device 1300, and “Compare” is a signal from the queue control device 1300. Address comparison start signal to be transferred,
“Address Pointer” is an input / output signal of an address pointer, “R / W” is a read / write control signal of the memory 3200, and “Address” is a memory 3
The address signal “Data” of the memory 3200
Is a signal indicating the result of the address comparison to the queue control device 1300. Note that, in FIG. 23, the clock and the reset signal are omitted.

The counter 3101 has INC as a control input terminal, and performs an increment operation by this control input. The output of the AND gate 3111 is connected to the INC terminal. The output Q is a three-state buffer 31.
31 and a subtractor 3149.

The counter 3103 has INC and DEC as control input terminals, and performs an increment operation when the INC terminal is activated, and performs a decrement operation when the DEC terminal is activated. I
The output of the AND gate 3111 is connected to the NC terminal, and the output of the AND gate 3113 is connected to the DEC terminal. The output Q of the counter 3103 is output to the comparator 314
1 and the comparator 3143.

The counter 3105 has INC as a control input terminal, and performs an increment operation when the INC terminal becomes active. The output of the AND gate 3113 is connected to the INC terminal. Counter 310
The output Q of 5 is a 3-state buffer 3133 and a counter 31
07.

The counter 3107 has START and STOP as control input terminals, and has DATA as a data input terminal. When a pulse signal is input to the START terminal, the value input to the DATA terminal is loaded, and an increment operation is started from the value. When a pulse signal is input to the STOP terminal, the increment operation ends. The control signal Compare from the queue control device 1300 is connected to the START terminal, the output signal of the comparator 3145 is connected to the STOP terminal, and the output signal of the counter 3105 is connected to the DATA terminal. The output of counter 3107 is connected to comparator 3145 and tri-state buffer 3135.

The comparator 3141 compares the input value with a predetermined value. The comparison value of the comparator 3141 is given the capacity of the memory. The output from the counter 3103 is input to the comparator 3141. The output of the comparator 3141 is connected to the AND gate 3111.

The comparator 3143 compares the input value with a predetermined value. The comparison value of the comparator 3143 is 0. The output from the counter 3103 is input to the comparator 3143. The output of the comparator 3143 is connected to the AND gate 3113.

The comparator 3145 compares two inputs. The output of the counter 3107 and the output of the subtractor 3149 are input to the comparator 3145. The comparison result is connected to the STOP terminal of the counter 3107 and the reset terminal of the flip-flop 3151.

The comparator 3147 compares two inputs. The value of the address pointer output from the other port address management device 1100 and the data output from the memory 3200 are input to the comparator 3147, and the comparison result is transferred to the queue control device 1300.

The subtractor 3149 performs a process of reducing the input value by one. The subtractor 3149 has a counter 3101
Is input and the result of the subtraction is output to the comparator 31
45.

The three-state buffer 3131 has a control input, a data input, and a data output. When the control input becomes active, the value of the data input is output to the data output. When the control input is not active, it goes into a high impedance state. An output from the counter 3101 is input to a data input of the 3-state buffer 3131, and a control input is
The output of the AND gate 3111 is input, and the data output is connected to the address input of the memory 3200.

The output from the counter 3105 is input to the data input of the 3-state buffer 3133, and the control signal Read from the queue control device 1300 is input to the control input.
And the data output is connected to the address input of the memory 3200.

The output from the counter 3107 is input to the data input of the 3-state buffer 3135, and the control signal Comp from the queue control device 1300 is input to the control input.
are input and the data output is connected to the address input of the memory 3200.

The address input from the other port address management device 1100 is input to the data input of the 3-state buffer 3137, the control signal Write from the queue control device 1300 is input to the control input, and the data output is Connected to data input of memory 3200.

The AND gate 3111 has two inputs, one of which is an inverted input. And Gate 3
The output from the comparator 3141 is connected to the inverting input of 111, and the queue control device 1300 is connected to the other input.
Control signal Write is input from AND gate 3
The output of 111 is connected to the INC terminal of counter 3101, the INC terminal of counter 3103, and the control input of tri-state buffer 3131.

The AND gate 3113 has two inputs, one of which is an inverted input. And Gate 3
The output from the comparator 3143 is connected to the inverting input of 113, and the queue control device 1300 is connected to the other input.
Is input from the AND gate 31
The output of 13 is connected to the INC terminal of the counter 3105 and the DEC terminal of the counter 3103.

The flip-flop 3151 has a set terminal and a reset terminal as control inputs. The flip-flop 3151 operates in synchronization with a clock (not shown), and makes the output active when the set terminal becomes active, and makes the output negative when the reset terminal becomes active. The set terminal has a queue control device 1300
, And the output from the comparator 3145 is input to the reset terminal.

The memory control device 3100 having such a configuration is described.
And the memory 3200, the port address management device 1100 can be configured.

Next, still another configuration of the port address management device 1100 will be described.

FIG. 24 shows a port address management device 1100.
Is shown.

Port address management device 1 shown in FIG.
100 denotes a plurality of memory cells 4100 and memory cells 4100
A plurality of comparison circuits 4200 for comparing the content of the address 100 with an address pointer output from another port address management device 1100, a word line control unit 4300 for controlling a memory address, and counting outputs from the comparison circuits. And an aggregation circuit 4400.

Each memory cell 4100 holds an address pointer output from free address management device 1200 and information indicating whether the held address pointer is valid or invalid.

Each comparison circuit 4200 includes a memory cell 410
It compares the content of 0 with the address pointer output from the other port address management device 1100 and outputs a signal indicating that they match.

Memory cell 4100 and comparison circuit 420
0 is CAM (Content Addressable)
e Memory) may be used.

The word line controller 4300 controls writing to the memory cell 4100 and reading from the memory cell 4100 in accordance with a control signal transferred from the queue controller 1300. The control of the address is performed to realize a FIFO operation.

The summing circuit 4400 sums up the signals output from the comparing circuit 4200 and checks with the queue control device 1300 whether an address pointer that matches the address pointer output from the other port address management device 1100 is held. Forward.

When the memory cell 4100 and the comparison circuit 4200 are integrally formed, a known CAM technique may be used. FIGS. 25 to 27 show configuration examples using the CAM. FIG. 25 is an example of a memory cell of the CAM disclosed in Japanese Patent Application Laid-Open No. 7-220483 (registered patent number 2636159). FIG. 26 is a diagram of a CAM shown in "Super LSI Comprehensive Dictionary", Science Forum Co., Ltd. FIG. 27 shows an example of a memory cell, “Design of CMOS VLSI”, Baifukan,
2 is an example of the memory cell of the CAM shown in FIG.

The memory cell integrated with the comparison circuit shown in FIG. 25 has inverters 4111, 4113 and n-channel MOS transistors 4115, 4117, 4119,
4121, 4123, and 4125.

The operation of the memory cell shown in FIG. 25 will be described.

At the time of writing, the data to be written to BL is:
The inverted data of the data to be written is input to BL-bar (BL overscore in the figure), WL goes to “H” level, and n-channel transistor 411
5, 4117 are turned on, the signals input to BL and BL-bar are input, and the data is held in the latch. At the time of reading, BL and BL-bar are precharged and set to “H” level, and then, by setting WL to “H” level, transistors 4115 and 4117 are turned on, and data is stored in BL and BL-bar. Is read.

When searching for data, ML is precharged, and thereafter, an inverted signal of data, BL-
Data is given to bar. If the search data and the held data do not match, the transistors 4119 and 4119
121, or both of the transistors 4123 and 4125 are turned on, the charged charge is extracted from the ML, and changes to the “L” level. For example,
When searching for “H” level data, an “L” level signal is applied to BL and an “H” level signal is applied to BL-bar. When the memory cell holds the “H” level, the wiring A indicates the “L” level and the wiring B indicates the “H” level. At this time, transistor 4
Although the transistor 119 and the transistor 4125 are turned on, the transistor 4121 and the transistor 4123 are turned off. Therefore, ML is kept at the “H” level, and it is detected that they match. If there are a plurality of bits in the data and all the bits match, the ML is kept at "H" level, and it is detected that there is a match.

The memory cell integrated with the comparison circuit shown in FIG. 26 has inverters 4131, 4133 and n-channel MOS transistors 4135, 4137, 4139,
4141, 4143, and 4145.

Writing and reading are the same as those of the memory cell shown in FIG.

At the time of retrieval, after precharging ML, data is applied to BL, an inverted signal of data is applied to BL-bar, and ME is set to "H" level. If the data on the BL does not match the held data, the transistor 4
143 and 4145 or both the transistors 4139 and 4141 are turned on, and charge is extracted from the ML,
ML becomes “L” level.

The memory cell integrated with the comparison circuit shown in FIG. 27 has inverters 4151 and 4153 and n-channel MOS transistors 4155, 4157, 4159,
4161.

Writing and reading are the same as those of the memory cell shown in FIG.

At the time of retrieval, after precharging the ML, data is given to TG, and an inverted signal of data is given to TG-bar (TG overscore in the figure), and if the data on TG does not match the held data , ML are pulled out, and ML attains the “L” level.

The port address management device 1100 can be configured using the memory cells used for these CAMs. FIG. 28 shows a configuration example of a port address management device 1100 using CAM cells.

Port address management device 1 shown in FIG.
Reference numeral 100 denotes a plurality of memory cells (one in which a comparison circuit is integrated) 4100 arranged on an array,
An input / output control circuit 41 for controlling input / output of 100 data
01, a word line control circuit 4300, and a counting circuit 440.
0. In FIG. 28, a predetermined number of components indicated by reference numeral 4102 are provided.

The configuration example of FIG. 28 uses the CAM cell shown in FIG. 26 as a memory cell 4100 as an example. The memory cell 4100 includes bit lines BL, BL
-Bar, and the bit line is connected to the input / output control circuit 41.
01 is connected. The word line WL and the search permission line ME, which are control inputs of the memory cell 4100, are output from the word line control device 4300. The search line ML which is an output signal of the memory cell 4100 is connected to the counting circuit 4400.

The input / output control circuit 4101 stores an address pointer and valid / invalid information in the memory cell 41 at the time of writing.
00, the information is output to the bit line to write the data, and at the time of reading, the information from the bit line to which the address pointer is output is processed, the read address pointer is output, and the valid / invalid information is stored in the memory cell Write. At the time of information retrieval, information is output to the bit line.
At this time, a value indicating validity is output to the bit line corresponding to the valid / invalid information.

Port address management device 1 shown in FIG.
FIG. 29 shows a configuration example of the word line control circuit 4300 used for the H.100.

First, an example of the operation of the word line control circuit shown in FIG. 29 will be described with reference to FIGS. 30 and 31 (the configuration and the like of this word line control circuit will be described later).

Referring to FIGS. 30 and 31, "Memory"
“y” is the content stored in the memory, “WP” is the value of the write pointer, “RP” is the value of the read pointer,
“F” indicates the state of the empty flag. When "F" indicates "1", the address pointer is not held. When “F” indicates “0”, at least 1
One address pointer is held. Memory
“Null” indicates invalid. In the illustrated example, the memory can hold eight address pointers.

FIG. 30A shows an initial state.
In the initial state, the write pointer and the read pointer indicate the same address 0, and since there is no address pointer held, the empty flag holds "1" indicating "empty".

The address pointer is written at the address indicated by the write pointer. When the address pointer is written in the state of FIG. 30A, it is written to the address 0 indicated by the write pointer. At the same time, the value of the write pointer is incremented by one, and since the write is no longer in the "empty" state, "0" is written in the empty flag. As a result, the state changes to the state shown in FIG.

Similarly, when the writing of the address pointer is performed, the state changes as shown in FIGS. 30 (c) and 30 (d).

In the state shown in FIG. 30D, valid address pointers have been written in all entries, and cannot be written any more. The non-writable state can be known from the states of the write pointer, the read pointer, and the empty flag. That is, when the empty flag is “0” and the write pointer and the read pointer match, writing cannot be performed.

The address indicated by the read pointer is read from the address pointer. In the state of FIG.
When reading is performed, the address pointer written at address 0 indicated by the read pointer is read. At the same time, the value of the read pointer increases by one. As a result, it changes as shown in FIG.

When reading is performed in the same manner, the state changes as shown in FIG. The state shown in FIG. 31B is a state in which only one address pointer is held. If further reading is performed from this state, the address pointer disappears and the empty flag is set to "1" indicating "empty". Is done. That is, the empty flag is set to “1” when reading is performed when the remaining address pointer is one. The state where one address pointer remains is a state where the value obtained by adding one to the read pointer matches the value of the write pointer. FIG.
When reading is performed from the state of (b), FIG.
It changes like

Now, the word line control device 4 shown in FIG.
Reference numeral 300 denotes counters 4311 and 4315, flip-flops 4313, comparators 4321 and 4323, and an adder 43.
25, selector 4341, AND gates 4331, 43
35, 4339, a NAND gate 4333,
4337, buffer 4361, and gate 4351-
4358.

In FIG. 29, the clock and the reset are not shown. Further, the word line control device shown in FIG. 29 shows an example having eight addresses.

The counter 4311 is a counter for counting write addresses, and has a control input inc and an output out. When inc becomes active, the held count value is increased by one. Also, the counter 4311
Counts the same number as the number of words, and transitions to the minimum value when the maximum value is reached. For example, when the number of words is 8, for example, it changes as 0 → 1 → 2 → 3 → 4 → 5 → 6 → 7 → 0 → 1 → 2. The output of the AND gate 4331 is connected to the inc input of the counter 4311. The out output of the counter 4311 is output to the comparators 4321 and 4323.
And the selector 4341.

The counter 4315 is a counter for counting read addresses, and operates in the same manner as the counter 4311 in the same manner. Inc of counter 4315
The output of the AND gate 4339 is connected to the input.
The out output of the counter 4315 is output to the comparator 4321,
Connected to adder 4325 and selector 4341.

The flip-flop 4313 is used to indicate whether the number of valid address pointers is zero. The flip-flop 4313 has s as a control input.
et, reset, and out as an output. s
It is set to 1 when et becomes active, and reset to 0 when reset becomes active.

The comparator 4321 compares the values of the counter 4311 and the counter 4315. Activates the output when the values match. The comparator 4321 is
The output of the counter 4311 and the output of the counter 4315 are input, and the output of the comparator 4321 is output to the NAND gate 433.
3 and transferred to the NAND gate 4337.

The comparator 4323 is a comparator for comparing the value of the counter 4311 with the value of the adder 4325. Activates the output when the values match. The output of the counter 4311 and the output of the adder 4325 are input to the comparator 4321, and the output of the comparator 4323 is transferred to the AND gate 4335.

An adder 4325 is an adder that increases the value by one. Outputs a value obtained by adding one to the input value. The output of the counter 4315 is input to the adder 4325,
The output is transferred to the comparator 4323.

The selector 4341 selects and outputs one of the two data according to the control signal. Selector 4341
, The output of the counter 4311 and the output of the counter 4315 are input as data inputs, and the write control signal (W
write) is input. The output of the selector 4341 is
Input to AND gates 4351 to 4358 forming a decoder.

The AND gate 4331 has a counter 431.
1 control signal is generated. It has two inputs, one of which is a write signal (Wr
item), and an output signal of the NAND gate 4333 is input to the other input. The output signal is the reset of the counter 4311 and the flip-flop 4313.
Forwarded to input.

The AND gate 4335 generates a control signal for the flip-flop 4313. It has two inputs, one to which the output signal of the AND gate 4339 is input, and the other to which the output from the comparator 4323 is input. The output signal is input to the set input of the flip-flop 4313.

The AND gate 4339 has a counter 431.
5 control signals are generated. It has two inputs, one of which is a read signal (Re) transferred from the queue control device 1300.
ad) is input and the output signal of the NAND gate 4337 is input to the other input. The output signal is transferred to the counter 4315 and the AND gate 4335.

The NAND gate 4333 has two inputs. One is an inverting input. The output signal of the flip-flop 4313 is input to the inverting input. The output of the comparator 4321 is input to the other input. The output signal is transferred to AND gate 4331.

The NAND gate 4337 has two inputs. The output signal of the flip-flop 4313 is input to one, and the output of the comparator 4321 is input to the other input. The output signal is transferred to AND gate 4339.

The AND gates 4351 to 4358 operate as decoders for producing a word line output to the memory cell 4100. The signal transferred from the selector 4341 is decoded and transferred to a memory cell. For example, the AND gate 4351 becomes active when the data input is “111”.

At the time of retrieval, the Match signal goes to "H" level, and this is supplied to each memory cell 4100 as ME0-ME7 via the buffer 4361.

Next, another configuration example of the word line control circuit 4300 used in the port address management device 1100 shown in FIG. 28 is shown in FIG.

First, an operation example of the word line control device shown in FIG. 32 will be described with reference to FIGS. 33 to 35 (the configuration and the like of this word line control circuit will be described later).

FIGS. 33 to 35 show examples in the case of controlling eight word lines. W0 to W7 correspond to writing, and R0 to R7 correspond to reading. WL0
To WL7 represent word lines.

FIG. 33A shows the initial state.
In the shift register for writing and the shift register for reading, only one bit corresponding to the same word line is active. In the example shown in FIG. 33A, W0 and R0 are active.

When writing the address pointer, the selector is controlled to output the contents of the shift register corresponding to the write, and thereafter, the shift register corresponding to the write is shifted. After the write operation, FIG.
It changes as shown in FIG. When writing is performed similarly, FIG.
4 (a).

When reading the address pointer, the selector controls the selector to output the contents of the shift register corresponding to the reading, and then shifts the shift register corresponding to the reading. After the read operation, FIG.
It changes as shown in FIG. When reading is performed in the same manner, FIG.
It changes like 5.

Now, the word line control device 4 shown in FIG.
Reference numeral 300 denotes flip-flops 4391-1 to 4391-8 forming a shift register for writing and flip-flops 439 forming a shift register for reading
3-1 to 4393-8 and selectors 4395-1 to 4395-8 for selecting an output signal to the word line.

Flip-flops 439-1 to 4391
-8 is connected on the ring and the queue control device 1300
Is shifted by the control signal Write transferred from the controller. The flip-flops 4393-1 to 4393-8 also
It is connected on the ring and shifted by a control signal Read transferred from the queue control device 1300. Flip-flop 4391-i and flip-flop 4393-i
Are input to separate inputs of the same selector 4395-i, and one of them is output according to the control signal Write input to the selector.

In FIG. 32, the search permission signal (Mat
ch, MEi) are the same as those shown in FIG.

By using the port address management device as described above, a high-speed address management device having a multicast function can be realized. That is, a queue of address pointers is provided for each output port,
For a multicast cell, a multicast function can be realized by inputting to a plurality of queues. Then, by searching for an address pointer held in each queue, it is possible to identify a free address.

(Second Embodiment) Next, a cell switching device and an address management device thereof according to a second embodiment of the present invention will be described.

The description will be made assuming that the cell switching apparatus according to the present embodiment uses the one illustrated in FIG. 56 (of course, another cell having the same function as this may be used). That is, the address management device according to the present embodiment can be used for the cell switching device illustrated in FIG. 56 or a device having the same function as this.

The address generating apparatus according to the present embodiment is generally obtained by speeding up the processing which has been sequentially performed for each output port in the first embodiment by performing parallel processing.

FIG. 36 shows a configuration example of the address management device 100 according to the present embodiment. Although FIG. 36 illustrates an example corresponding to four output ports, a configuration in which the number of output ports is three or less or five or more can be similarly configured.

This address management device is a port address management device 1102 that manages an address pointer for each port.
-1 to 1102-4, a free address management device 1202 holding a free address pointer, and an address filter 1402-1 to 1402- filtering the address pointer transferred from the free address management device 1202.
4. Each port address management device (1102-1 to 110-2)
2-4), an empty address queue 1202, and a queue control device 1302 for controlling each of the address filters 1402-1 to 1402-4.

Each port address management device 1102 performs FIFO management of the address pointer transferred from the free address management device 1202. At the time of a write operation, a plurality of valid address pointers transferred from the address filter 1402 are simultaneously written, and at the time of a read operation,
Output the oldest address pointer. At the same time, it searches whether the address pointer transferred from the other port address management device 1102 is held, and transfers the result to the queue control device 1302. In the example shown in FIG. 36, the port address management device 1102 includes a port address memory 1112 for holding an address pointer,
It comprises comparators 1114, 1115 and 1116 for comparing the held address pointer with the address pointer transferred from the other port address management device 1102.

The free address management device 1202 holds an unused address pointer, and outputs the held address pointer in accordance with an instruction from the queue management device 1300. Further, the address pointer transferred from the port address management device 1102 is filtered according to the instruction of the queue management device 1300,
Hold. The filtering is performed based on the search result transferred from each port address management device 1102 to the queue management device 1302. That is, writing is performed when the address pointer transferred from a certain port address management device 1102 is not held in another port address management device 1102. Further, when the address pointers having the same value are output from the plurality of port address management apparatuses 1102, only one is written. In the example shown in FIG. 36, the free address management device 1202 includes a free address memory 121 for holding an address pointer.
2, 1213, 1214, 1215 and an empty address filter 1216.

The address filter 1402 filters the address pointer transferred from the free address management device 1202 according to the instruction of the queue control device 1302. The address pointer to the cell to be multicast is stored in a plurality of port address management devices 110.
2 Therefore, each port address management device 1102 must hold a plurality of address pointers corresponding to a plurality of cells. Since the vacant address management device 1202 outputs a plurality of address pointers at the same time, only the necessary address pointers are extracted and transferred to each port address management device 1102.

For example, when cell A going to port # 1 and port # 2, cell B going to port # 2 and port # 3, and cell C going to port # 1 and port # 3 are input,
The empty address management device 1202 outputs the same number of address pointers as the input cell number. Assuming that the address pointers corresponding to the cells A, B, and C are an address pointer A, an address pointer B, and an address pointer C, respectively, the port address management device 1102 corresponding to the port # 1 has the address pointer corresponding to the cell A. A, two address pointers C corresponding to cell C
Port address management device 1102 corresponding to port # 2
Is the address pointer A corresponding to the cell A and the address pointer B corresponding to the cell B, and the port address management device 1102 corresponding to the port # 3 is corresponding to the address pointer B and the cell C corresponding to the cell B. The two address pointers C that have been used must be held.

Therefore, in this case, the address filter 140 corresponding to the port # 1 is selected from the three address pointers transferred from the free address management device 1202.
2 corresponds to two address pointers A and C corresponding to the cell A, and the address filter 1202 corresponding to the port # 2 corresponds to the address pointers A and B corresponding to the cell A. The address filter 1402 corresponding to two address pointers B and the port # 3 selects two address pointers B corresponding to the cell B and two address pointers C corresponding to the cell C, and the respective port address management devices. Transfer to 1102.

Next, the operation of the parallel processing will be described with reference to FIGS.

FIG. 37 shows an initial state. In the initial state, all valid address pointers are held in the free address management device 1200, and no valid address pointers are held in the memory of the port address management device 1102.

FIG. 38 shows an example of the write operation. FIG. 38 shows that the cell A going to the output port # 1 has the address pointer “0”, the cell B going to the output port # 1 and the output port # 2 has the address pointer “1”,
1 shows an example in which the cell C going to the output port # 2 is written to the address pointer "2", and the cell D going to the output port # 3 and the output port # 4 is written to the address pointer "3". From the free address management device 1202, address pointers “0” corresponding to the four cells,
“1”, “2”, and “3” are output. All of these address pointers are input to the address filter 1402 corresponding to each port. The address filter corresponding to each output port transfers only a valid address pointer from the input address pointers to the corresponding port address management device 1102 according to the control signal transferred from the queue control device 1302.

For example, since the address filter 1402-1 corresponding to the output port # 1 has three cells A, B, and C going to the output port # 1, the address filter 1402-1 has only an address pointer corresponding to these cells. The pointers “0”, “1”, and “2” are output, and the address pointer “3” is not output. Similarly, the address filter 1402-2 corresponding to the output port # 2 outputs only the address pointers "1" and "2", and the address filter 1402-3 corresponding to the output port # 3 outputs the address pointer "3". And the address filter 1402-4 corresponding to the output port # 4 outputs only the address pointer "3".

The port address management device 1102 holds a valid address pointer output from the address filter 1402. Since the address pointers “0”, “1”, and “2” are input to the port address management device 1102-1 corresponding to the output port # 1, these address pointers are held. Similarly, the port address management device 1102-2 corresponding to the output port # 2 receives the address pointers “0” and “1”, holds these address pointers, and manages the port address corresponding to the output port # 3. The device 1102-3 receives the address pointer "3", holds the address pointer, and sets the port address management device 110 corresponding to the output port # 4.
In 2-4, the address pointer "3" is input, and this address pointer is held.

The port address management device 1102 may use, for example, one bit to identify whether it is a valid address pointer. When the validity of the address pointer is indicated by using one bit, the address filter 1402 sets this bit to 0 for an invalid address pointer, and sets 1 for a valid address pointer. A filtering operation can be realized.

FIG. 39 shows an example of a read operation from the state of FIG.

Each port address management device 1102 outputs the address pointer written first. In FIG. 38, since the old address pointer is drawn downward, the port address management device 1102-1 for the output port # 1 is "0", and the port address management device 1102-2 for the output port # 2 is "0". 1 ″, port address management device 1102 for output port # 3
-3, "3" is output from the port address management device 1102-4 for the output port # 4. The output address pointer is transferred to another port address management device 1102. The transferred address pointer is compared with the address pointer held in each port address management device 1102 by the comparator 111.
4, 1115, 1116.

In the example of FIG. 39, the port address management device 1102-1 for the output port # 1 includes the port address management device 1102-2 for the output port # 2, and the port address management device 1102 for the output port # 3.
-3, the address pointers "1", "3",
"3" is transferred, and it is compared whether these address pointers are held. Since the port address management device 1102-1 for the output port # 1 holds the address pointers "1" and "2", it indicates that the address pointer "1" is held for the transferred address pointer "1". The signal is transferred to the queue controller 1302. In FIG. 39, this signal is displayed as “hit”.

On the other hand, the address pointer transferred from each port address management device 1102 is input to the free address management device 1202. Further, a signal indicating whether or not these address pointers are held in another port address management device 1102 is transferred from the queue control device 1302. In FIG. 39, a signal indicated as “write” indicates that the signal is not held in the port address management device 1102, and is therefore usable as a free address, so that the signal is written to the free address management device 1202.

As shown in FIG. 39, there are cases where the same address pointer is input to the empty register management device a plurality of times. The duplicate address pointers are deleted by the empty address filter 1216. In addition, a plurality of free address memories 1212, 1213, 1214, 121
5 are transferred after being rearranged so that the number of address pointers held in 5 becomes uniform. In the case of the example of FIG. 39, “0” and “3” are the free address memories 12 respectively.
12 and the free address memory 1213 to be written.

With such an operation, address management can be processed in parallel, and high-speed operation can be performed.

Next, a more detailed configuration of the present embodiment will be described.

First, a configuration example of the port address management device 1102 will be described.

FIG. 40 shows a port address management device 1102.
An example of the configuration will be described. The configuration example shown in FIG. 40 differs from the configuration example shown in FIG. 36 in that a comparison circuit is provided for each of the storage elements. The port address management device 1102 illustrated in FIG. 40 includes a plurality of sets of a first memory element 5100 and a plurality of second memory elements 5200, and one or a plurality of aggregation circuits 5300. The first memory element 5100 holds information indicating whether it is a valid address pointer. In addition, a plurality of second memory elements 5
At 200, the address pointer is held.

In the configuration example shown in FIG. 40, the oldest address pointer is held at the lower part. During a write operation, the empty memory elements 5100, 520
0, the data is written to the lowermost memory elements 5100 and 5200. During a read operation, the contents of the lowermost memory elements 5100 and 5200 are read, and the contents held in the other memory elements 5100 and 5200 are shifted to the next lower memory elements 5100 and 5200. .

FIG. 41 shows a detailed configuration example of the memory element 5100. The memory element 5100 includes the flip-flop 5
111 and n-channel transistors 5121, 5122, 5123, 5124, 5125,
5126 and a three-state buffer 515 constituting a selector
1, 5153, an AND gate 5131, an OR gate 5133, and four three-state buffers 5141, 5143, 5145, and 5147 forming a selector.

Note that VLD0 to VLD3 in FIG. 40 and FIG.
41, four signals indicated by E in FIG. 40 and EI2 / EO2, EI1 / EO1, EI0 / EO in FIG.
0, AI / AO, VLD in FIG. 40 and SO / S in FIG.
I, TAGv0, TAGv1, TAGv2 in FIG. 40 and TG0 / TG0B, TG1 / TG1B, TG2 /
TG2B respectively correspond.

The flip-flop 5111 has a data input D, an enable input E, a data output Q, and an inverted output Q of the data output Q.
-Has a bar (Q overscore in the figure). However,
It also has a clock and reset input, not shown.
The data input includes a three-state buffer 5 constituting a selector.
The outputs of 151 and 5153 are input. The output of the OR gate 5133 is input to the enable input. The data output Q is an n-channel transistor 5 constituting a comparator.
121, 5123, 5125 and the upper memory element 5100
(AO) and the lower memory element 5100 (SO). The data inverted output Q-bar is n
Channel transistors 5122, 5124, 5126 and AND gate 5131 are connected.

Three-State Buffer 515 Constituting Selector
1 and 5153 are output by the write instruction signal “WRITE” transferred from the queue control device 1302, and the output (SI) from the upper memory element 5100 and the three-state buffers 5141, 5143, 5145, 5
147 is switched. When "WRITE" is active, the three-state buffer 514 constituting the selector
1, 5143, 5145, and 5147. Otherwise, a signal (SI) from the upper memory element 5100 is output.

(3) Constituting Address Selector 3
Status buffers 5141, 5143, 5145, 5147
Selects the address pointer transferred from the address filter 1402. In the example of FIG. 41, there are four address pointer inputs, and the three-state buffers 5141 and 511,
Reference numerals 43, 5145, and 5147 constitute a 4-input / 1-output selector. The output is transferred to a three-state buffer 5153 forming a selector.

The AND gate 5131 stores the held data (AI) transferred from the lower memory element 5100,
Inverted data output of flip-flop 5111 (Q-ba
r and a write enable signal “WRITE” transferred from the queue control device 1302 are input. When the data held in the flip-flop 5111 is “L”,
When a valid address pointer is not held and a write instruction signal is input while data held in the lower memory element 5100 is valid, the memory element becomes active (“H”). When the output of the AND gate 5131 is active, the memory element 5100 is the lowest empty memory element.
The address pointer transferred from 402 is fetched. The output of the AND gate 5131 is an OR gate 5133 and a three-state buffer 514 for selecting the address pointer AP0.
3 and transferred to another memory element 5200. The signal transferred to the horizontal memory element is used to select a corresponding address pointer. Upper memory element 51
The signal EO0 transferred to 00 is used to select another address pointer. That is, when AP0 is taken into this memory element 5100, the memory element 5100 above takes AP1 and the memory element 5100 above it takes AP2, and the memory element 5100 above three.
100 is used to capture AP3.

The OR gate 5133 generates a write enable signal for the flip-flop 5111. Writing to the flip-flop occurs at the time of a write operation and a read operation. At the time of a write operation, when the memory element 5100 is the lowest empty memory element 5100 or the memory element 5100 one to three below is the lowest empty memory element 5100, Writing is performed on the memory element 5100. In the case of a read operation, writing is performed so that all the memory elements 5100 perform a shift operation. Therefore, the output of the AND gate 5131 that determines whether the memory element is the lowest free memory element 5100 and the outputs EI0 and EI2 that are the outputs from the AND gate 5131 of the next lower stage are provided to the OR gate 5133.
EI which is the output from the AND gate 5131 at the next lower stage
EI2, which is an output from the AND gate 5131 at one and three stages below, and a read enable signal “READ” transferred from the queue control circuit 1302 are input.

The n-channel transistors forming the comparison circuit have the same function as the n-channel transistors 4159 and 4161 used in the memory cell shown in FIG. The n-channel transistors 5121 and 5122, the n-channel transistors 5123 and 5124, and the n-channel transistors 5125 and 5126 form a pair, and the contents held in the flip-flop 5111 and the wiring TG0,
The contents transferred to TG1 and TG2 are compared, and if they do not match, the charge is extracted from the wirings ML0, ML1 and ML2.

FIG. 42 shows a detailed configuration example of the memory element 5200.

The memory element 5200 is the same except that there is no AND gate 5131 for detecting the lowest empty memory element of the memory element 5100, and the other parts are the same.

Note that AP00 to AP03 in FIG. 40 and FIG.
41, APO0 in FIG. 40 and SO in FIG.
/ SI, TAGi0, TAGi1, TAGi2 in FIG.
And TG0 / TG0B, TG1 / TG1B, TG in FIG.
2 / TG2B respectively correspond.

Next, the configuration of the counting circuit 5300 will be described.

FIG. 43 shows a configuration example of the counting circuit 5300. The counting circuit 5300 illustrated in FIG. 43 includes m-1 OR gates 5310-1 to 5310- (m-1) and m precharge p-channel transistors 5320-1 to 5320-1.
5320-m.

The number of inputs to the counting circuit 5300 is m while the number of memory elements 5100 and 5200 is (m + 1) from 0 to m. This is the bottom memory element 510
This is because there is no need to perform coincidence detection since 0,5200 disappears during reading.

M-1 OR gates 5310-1 to 5310-53
When any one of the inputs 10- (m-1) becomes active, the output "HIT" signal becomes active, indicating that there is an address pointer that matches the search condition. The m precharge p-channel transistors 5320-1 to 5320-m set the search wirings ML0 to MLm to “H” by the control signal PC before performing the search.
Precharge to. When PC becomes "L", all the p-channel transistors are turned on, and the search lines ML0 to ML
m becomes equal to the power supply potential. After that, PC becomes “H”, the p-channel transistor turns off, and the search lines ML0 to ML0
The MLm is separated from the power supply, a search is performed, and if there is no match, the charge is extracted and becomes “L”.

FIG. 44 shows another configuration example of the counting circuit 5300. The aggregation circuit shown in FIG. 44 connects OR gates in a tree shape. In the configuration shown in FIG. 44, the number of gates is increased as compared with FIG. 43, but the delay time is reduced.

Next, address filter 1 will be described with reference to FIG.
The configuration of 402 will be described.

In FIG. 45, VDI0, VDI1, VDI
DI2 and VDI3 are signals indicating valid cell inputs transferred from the queue control device 1302, API0, API
1, API2 and API3 are free address management devices 12
02, VDO0, VD
O1, VDO2, and VDO3 are address filters 140
A indicating the validity of the address pointer output from the address A
PI0, API1, API2, and API3 are address pointer outputs from the address filter 1402.

Address filter 1402 shown in FIG.
Is realized by a batcher sorting network composed of two-input two-output switch elements 6100. The information used for sorting is only valid information. Therefore, valid address pointers are collected above the output in FIG.

Next, FIG. 46 shows a configuration example of the switch element 6100.

The switch element 6100 shown in FIG.
Selectors 6111-1 to 6111-n, 613-1 to 1
6113-n and an inverter 6115. FIG.
6, VLDA and VLDB are valid bit inputs, AP0A to APnA are address pointer inputs corresponding to VLDA, AP0B to APnB are address pointer inputs corresponding to VLDB, and VLDX and VLDY are
With valid bit output, AP0X to APnX are address pointer outputs corresponding to VLDX, AP0Y to APnY
Is an address pointer output corresponding to VLDY.

This switching element 6100 performs an exchange operation using only valid bits. Of the two inputs, those having "1" as a valid bit are output to X, and those that do not are output to Y. However, when both have the same value,
both are fine. Therefore, when VLDA is "1", a set corresponding to VLDA is output to X, and VLDA
The set corresponding to B is output to Y. When VLDA is “0”, a set corresponding to VLDA is output to Y, and a set corresponding to VLDB is output to X.

As the switch element 6100, an element using a running adder circuit can be realized.

Next, a detailed configuration example of the free address management device 1202 will be described.

The vacant address management device 1202 inputs and outputs a plurality of vacant addresses for one operation. First
However, here, a configuration using a plurality of memories in parallel as shown in FIG. 36 will be described.

First, the configuration of the free address filter 1216 will be described.

The free address filter 1216 removes the duplicated address pointers from the address pointers output from the port address management device 1102, and writes data evenly in a plurality of free address memories.

FIG. 47 shows a configuration example of the free address filter 1216. Empty address filter 1 shown in FIG.
Reference numeral 216 uses a batcher sorting network 7100 and a unique circuit 7200 to eliminate duplication of address pointers, and uses a batcher sorting network 7300 and a shift network 7400 for uniform writing.

The batcher network 7100 performs sorting according to the size of the address pointer. As a result, the outputs are arranged in a descending order. Those with the same value are lined up next to each other. Therefore, when the values of adjacent address pointers are the same, one of them is invalidated because it is duplicated. By doing so, the duplicated address pointer can be deleted. After that, by sorting by the value of the valid bit, only valid address pointers can be collected on one side. Then, uniform writing can be realized by selecting the memory to be written from the information of the previously written memory by the shifter.

Next, an operation example of the empty address filter 1216 will be described with reference to FIG.

FIG. 48A shows an example in which "0", "2", "2", and "1" are input as address pointers. The input address pointer is sorted by the value of the address pointer in the batcher network 7100 and is output as “2”, “2”, “1”, “0”. If the values of adjacent address pointers are the same in the unique circuit 7200, the lower one is invalidated. In this example, since the address pointer "2" is adjacent, the lower one is invalidated. Then, sorting is performed using the valid bits in the batcher network 7200, and only valid address pointers are originally collected on the upper side. And shift network 7
The data is rearranged by 400 and written to the free address memory. Here, the shift network 7400
Since no address pointer is held in the vacant address, the data is packed upward and written in order from the top.

FIG. 48B shows an example in which "4", "4", "3", and "4" are further input as address pointers. Batcher Network 7100
Is sorted by the value of the address pointer,
"4", "4", "4", "3", and the unique circuit 7
200, the duplicated “4” is invalidated. Further, the data is sorted by the batcher network 7300 and input to the shift network 7400. FIG.
In FIG. 8 (a), since data has been written to the top three free address memories, writing is performed from the fourth free address memory next. That is, the data is written to the fourth and first free address memories.

Similarly, when "5", "6", "7", and "8" are input, finally, writing starts from the fourth free address memory, and "4" is stored in the fourth free address memory. 8 "," 7 ", 2 in the first free address memory
"6" is written to the third free address memory, and "5" is written to the third free address memory. This situation is shown in FIG.

Next, FIG. 49 shows the batcher network 7.
100 shows a configuration example. The batcher network 7100 shown in FIG. 49 includes a plurality of switching elements 7110 shown in FIG.

The switching element 7110 shown in FIG. 50 includes a comparator 7115 for comparing a valid bit with a value of an address pointer (the valid bit is set to the most significant bit), and a selector 71.
11-1 to 7111-n, 7113-1 to 7113-
n, and an inverter 7117.

Comparator 7115 compares the two address pointers A and B with each other with the valid bit as the most significant bit. When A (VLDA, AP0A to APnA) is large, the output is activated. The output of the comparator is output from selectors 7111-1 to 7111 -n and
17 is connected.

The selectors 7111-1 to 7111-n are
It has A and B data input terminals and a control terminal, and outputs data of the A terminal when the input of the control terminal, that is, the output of the comparator 7115 is active.

The selectors 7113-1 to 7113-n are
It has A and B data input terminals and a control terminal, and outputs data of the A terminal when the input of the control terminal, that is, the output of the inverter 7117 is active.

The switching element 7110 having such a structure is shown in FIG.
9, the input address pointers can be rearranged in descending order.

Next, the configuration of unique circuit 7200 will be described. The unique circuit 7200 realizes a function of invalidating one of two adjacent values when the two values are equal.

FIG. 51 shows an example of the structure of the unique circuit 7200. FIG. 51 shows an example for four inputs. This unique circuit 7200 includes comparators 7213-1 and 721
3-2, 7213-3 and AND gate 7211-1, 7
211-2 and 7211-3. Comparator 72
13 is an adjacent address pointer (including a valid bit)
Is compared. Activate the output when the two values match. The AND gate 7211 performs an operation of rewriting the valid bit to invalid when the values of the adjacent address pointers match.

Since the address pointers rearranged in the descending order by the batcher network 7100 are input to the uniqueness circuit 7200, the duplicated address pointers are invalidated by using the uniqueness circuit 7200 having such a configuration. It is possible to do.

Since the batcher network 7300 has the same function as the batcher network 7100, it can be realized with the same configuration as that described above, for example, the configuration shown in FIG.

Next, the configuration of shift network 7400 will be described.

FIG. 52 shows a configuration example of the shift network 7400. Shift network 7400 includes a plurality of shift circuits 7420-1 to 7420- (n + 2) and shift control circuit 7410. First, FIG. 53 shows a configuration example of shift circuit 7420. The shift circuit 7420
of n ² transfer gate 7421-1-1～742
1-4-4.

In FIG. 53, IN0 to IN3 indicate data inputs, OUT0 to OUT3 indicate data outputs, and S0 to S3.
3 is a control input.

The control inputs S0 to S3 are controlled so that only one of them becomes active. OUT0, OU
When S0 is active, data of IN0, IN1, IN2, and IN3 are output to T1, OUT2, and OUT3, respectively, and when S1 is active, I1 and IN2 are output, respectively.
The data of N3, IN0, IN1, and IN2 are output, and S
2 is active, IN2, IN3, I
When the data of N0 and IN1 is output and S3 is active, the data of IN1, IN2, IN3, and IN0 are output, respectively.

Next, FIG. 54 shows a configuration example of the shift control circuit 7410. The shift control circuit 7410 includes AND gates 7421-1 to 7421-4 and an OR gate 742.
3-1 to 7423-4, flip-flop 7425-1
To 7425-4.

In FIG. 54, V0 to V3 are valid bit inputs, and S0 to S3 are control outputs.

The shift control circuit 7410 transfers the data transferred from the batcher network 7300 to the shift circuit 7420.
Is input. Therefore, the place where the valid bit changes to the invalid bit is limited to one place.

Flip-flops 7425-1 to 7425
-4 holds the shift amount of the previous shift operation.
It has a set input S and a reset input R. When the set input becomes active, the active state (“H”) is maintained.
When the reset input becomes active, reset is performed,
“L” is held. Flip-flops 7425-1 to 7425-7
425-4, only one of them becomes active.

AND gates 7421-1 to 7421-4
Performs a change point detection. AND gate 7421-1-
The output of 7421-4 is the flip-flop 7425-1
７４ 7425-4.

OR gates 7423-1 to 7423-4
Are used to generate reset signals for the flip-flops 7425-1 to 7425-4. When any one flip-flop 7425 is set, a reset signal can be generated by ORing the set input of the other flip-flop 7425 such that the other flip-flop 7425 is reset. The output is flip-flop 7
425-1 to 7425-4.

Next, the operation of shift network 7400 will be described with reference to FIG. In FIG. 55, S0 to S3 represent states of the flip-flop 7425 of the shift control circuit 7410.

FIGS. 55A to 55D show a shift operation depending on the state of the flip-flop 7425 of the shift control circuit 7410. FIG. V0 to V3 represent valid bits to be input and output. The arrow in FIG. 55 indicates the amount of movement by the shift circuit. For example, FIG.
Then, it shifts right by one bit.

FIG. 55E shows a continuous operation example. In the initial state, the flip-flop 7425 corresponding to S0 is set, and the input valid bit is shifted (with a shift amount of 0) as indicated by an arrow. Since only three valid bits are valid,
S2 becomes 1 and S3 becomes 0, and the flip-flop 7 of S3
425 is set and another flip-flop 7425 is set.
Are reset to the state of “0001”. When a valid bit of “1100” is further input from this state, the bit is shifted as “1001”. Thus, the shift operation is realized.

Free address memory 1212, 1213,
1214 and 1215 are simple FIFOs. Since a general-purpose FIFO or a device in which the content comparison function of the port address management device 1100 shown in FIGS. 11 to 24 is removed can be used, detailed description is omitted here.

By using the address device having the configuration described above, the multicast function can be operated in parallel, and higher-speed operation can be realized.

In this embodiment, both the input phase of the address pointer to the port address management device for each output port and the output phase of the address pointer (including the detection of an empty address pointer) are processed in parallel. However, it is also possible to perform parallel processing on only one of the input phase and the output phase of the address pointer.

In the above description, an address management device for managing an address pointer for each output port has been described. However, the present invention provides, for example, an address management device for managing an output port for each virtual channel (VC) or for each class. It is also possible to apply to a management device.

In addition, not limited to ATM cells, for example, IP
It is also possible to apply to a variable length packet such as a packet.

Further, the present invention can be applied not only to switches but also to demultiplexers (demultiplexers).

The present invention is not limited to the above-described embodiments, but can be implemented with various modifications within the technical scope thereof.

[0274]

According to the present invention, the address information of the cells waiting to be output is managed separately for each output destination, and output from another storage means for each storage means used for the management. Since it is detected whether or not the same address information is held, the multicast function can be realized, the input operation and the output operation of the address information can be accelerated, and the shift operation can be performed in the output operation. It can be absorbed, and the search for free address information can be speeded up.

Further, according to the present invention, it is possible to operate the multicast function in parallel, so that a higher speed operation can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of an address management device according to a first embodiment of the present invention;

FIG. 2 is a diagram for explaining an operation example (initial state) of the address management device;

FIG. 3 is a diagram for explaining an operation example (input operation 1) of the address management device;

FIG. 4 is a diagram for explaining an operation example (input operation 2) of the address management device;

FIG. 5 is a diagram for explaining an operation example (input operation 3) of the address management device;

FIG. 6 is a diagram for explaining an operation example (input operation 4) of the address management device;

FIG. 7 is a diagram for explaining an operation example (output operation 1) of the address management device;

FIG. 8 is a diagram for explaining an operation example (output operation 2) of the address management device;

FIG. 9 is a diagram for explaining an operation example (output operation 3) of the address management device;

FIG. 10 is a diagram for explaining an operation example (output operation 4) of the address management device;

FIG. 11 is a diagram illustrating a configuration example of a port address management device;

FIG. 12 is a diagram showing a more detailed configuration example of a port address management device;

FIG. 13 is a diagram showing a portion corresponding to one memory unit in FIG. 12;

FIG. 14 is a diagram showing another configuration example of the port address management device.

FIG. 15 is a diagram for explaining an operation example of the port address management device;

FIG. 16 is a diagram for explaining an operation example of the port address management device;

FIG. 17 is a diagram for explaining an operation example of the port address management device;

FIG. 18 is a diagram illustrating an operation example of the port address management device.

FIG. 19 is a diagram illustrating an operation example of the port address management device.

FIG. 20 is a diagram illustrating an operation example of the port address management device.

FIG. 21 is a diagram illustrating an operation example of the port address management device.

FIG. 22 is a view for explaining an operation example of the port address management device;

FIG. 23 illustrates a configuration example of a memory control device.

FIG. 24 is a diagram showing still another configuration example of the port address management device.

FIG. 25 illustrates a configuration example of a memory cell.

FIG. 26 is a diagram showing another configuration example of a memory cell;

FIG. 27 is a diagram showing still another configuration example of the memory cell;

FIG. 28 is a diagram showing a more detailed configuration example of a port address management device.

FIG. 29 illustrates a configuration example of a word line control circuit.

FIG. 30 illustrates an operation example of a word line control circuit.

FIG. 31 is a diagram illustrating an operation example of a word line control circuit.

FIG. 32 is a diagram showing another configuration example of the word line control circuit.

FIG. 33 is a diagram illustrating an operation example of a word line control circuit.

FIG. 34 is a diagram illustrating an operation example of a word line control circuit.

FIG. 35 is a diagram illustrating an operation example of a word line control circuit.

FIG. 36 is a diagram illustrating a configuration example of an address management device according to a second embodiment of the present invention;

FIG. 37 is a view for explaining an operation example of the address management device;

FIG. 38 is a view for explaining an operation example of the address management device;

FIG. 39 is a view for explaining an operation example of the address management device;

FIG. 40 is a diagram showing a more detailed configuration example of a port address management device.

FIG. 41 illustrates a configuration example of a first memory element.

FIG. 42 illustrates a configuration example of a second memory element.

FIG. 43 is a diagram illustrating a configuration example of a counting circuit;

FIG. 44 is a diagram illustrating another configuration example of the counting circuit;

FIG. 45 is a diagram showing a configuration example of an address filter.

FIG. 46 illustrates a configuration example of a switch element.

FIG. 47 is a diagram showing a configuration example of a free address filter;

FIG. 48 is a view for explaining an operation example of an empty address filter;

FIG. 49 is a diagram illustrating a configuration example of a batcher network.

FIG. 50 is a diagram showing a configuration example of an exchange element.

FIG. 51 is a diagram showing a configuration example of a unique circuit;

FIG. 52 is a diagram illustrating a configuration example of a shift network.

FIG. 53 illustrates a configuration example of a first shift circuit.

FIG. 54 illustrates a configuration example of a second shift circuit.

FIG. 55 is a diagram illustrating an operation example of a shift network.

FIG. 56 is a diagram showing an example of a basic configuration of a cell switching device.

FIG. 57 is a diagram showing a configuration example of a conventional address management device.

And FIG. 58 is a diagram showing an operation example (input operation) of the conventional address management device.

FIG. 59 is a diagram showing an operation example (output operation) of the conventional address management device.

FIG. 60 is a diagram showing an operation example (shift operation) of the conventional address management device.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 address management device 200 output information processing device 300 cell storage device 400 input processing device 500 output processing device 600 multiplexing device 700 separating device 1100 port address management device 1102 port address management device (parallel processing) 1110, 1112 Port address memory 1114 to 1116 Comparator 1120 Address comparator 1200 Free address management device 1202 Free address management device (parallel processing) 1212 to 1216 Free address memory 1300 Queue control device 1302 Queue control Device (parallel processing) 1402 ... address filter 2110 ... memory unit 2111, 3151, 4313, 4391, 4393,
5111, 7425... Flip-flops 2113, 4341, 4395, 6111, 6113,
7111, 7113... Selector 2120... Unit control devices 2121, 133, 3111, 3113, 4335,
4339, 4351-4358, 5131, 7211,
7421 ... AND gates 2123, 2141, 142, 5310, 5133,
7423: OR gate 2130: Address comparison unit 2131: XNOR gate 2140: Comparison result totaling device 3100: Memory control device 3101, 3103, 3105, 3107, 4311,
4315, 4331 ... counters 3131, 3133, 3135, 3137, 5141,
5143, 5145, 5147, 5151, 5153 ...
3-state buffer 3141, 3143, 3145, 3147, 4321,
4323, 7115, 7213 ... Comparator 3149 ... Subtractor 3200 ... Memory 4100 ... Memory cell 4101 ... Input / output control circuit 4111, 4113, 4131, 4133, 4151
4153, 6115, 7117 ... inverters 4115, 4117, 4119, 4121, 4123,
4125, 4135, 4137, 4139, 4141,
4143, 4145, 4155, 4157, 4159,
4161 n channel MOS transistor 4200 comparison circuit 4300 word line control unit 4325 adder 4333, 4337 NAND gate 4361 buffer 4400, 5300 aggregation circuit 5100, 5200 memory element 5121-5126 n channel transistor 5320 p-channel transistor 6100 switch element 7100 batcher network 7110 exchange element 7200 unique circuit 7300 batcher network 7400 shift network 7410 shift control circuit 7420 shift circuit 11000 address management unit 11100 destination information register 11200 ... Unit control device 11300 ... Address pointer register 12000 ... Search circuit 13000 ... Address pointer output Circuit 14000 ... destination information input circuit

Claims (6)

[Claims] 1. A cell storage means shared by a plurality of output destinations for temporarily storing input cells, and a cell stored in the cell storage means which is determined based on header information of the cell storage means. A cell switching apparatus comprising: means for switching to a plurality of output destinations; and address management means for managing correspondence between address information indicating a storage location in the cell storage means for each cell and one or more output destinations of the cell. The address management unit is a storage unit provided for each output destination, and holds address information assigned to an input cell having an output destination corresponding to the storage unit, and stores it according to an instruction. Storage means for outputting the address information stored therein, and detection means provided for each output destination, the same as the address information output from the storage means other than the storage means corresponding to itself. Output from one of the storage units based on the detection result of the detection unit provided for each output destination, and a detection unit for detecting whether or not is stored in the storage unit corresponding to itself. Management means for holding, as address information, which is found to be not held in any of the storage means, as address information that can be assigned to a new input cell. Cell switching equipment. 2. A cell switching apparatus for temporarily storing input cells in cell storage means shared by a plurality of output destinations, and then exchanging the input cells with one or more output destinations determined based on the header information. An address management device that manages, for each cell, a correspondence between address information indicating a storage position in the cell storage means and one or more output destinations of the cell, wherein the storage means is provided for each output destination. Storage means for holding the address information assigned to the input cell having the output destination corresponding to itself and outputting the held address information in accordance with the instruction, and provided for each output destination. Detecting means for detecting whether or not the same address information output from the storing means other than the storing means corresponding to the detecting means is stored in the storing means corresponding to the detecting means. Means, based on the detection result of the detection means provided for each output destination, it is determined that the address information is output from any one of the storage means and is not held in any of the storage means Address management device for holding the information as address information that can be assigned to a new input cell. 3. A means for holding address information that can be assigned to a new input cell, and allocating a selected one of the held address information to the input cell; Address information
3. The address management device according to claim 2, further comprising: means for holding the storage means corresponding to one or a plurality of output destinations determined based on header information of the input cell. 4. The storage means outputs the stored address information in the order of input, and the assigning means selects the stored address information in the order of input. The address management device according to claim 3, wherein: And means for performing at least one of inputting address information to the storage means for each output destination and outputting address information from the storage means for each output destination in parallel for each output destination. The address management device according to any one of claims 2 to 4, wherein the address management device is provided. 6. A cell switching apparatus for temporarily storing input cells in cell storage means shared by a plurality of output destinations, and then exchanging the input cells with one or more output destinations determined based on the header information. A cell information management method for managing, for each cell, a correspondence between address information indicating a storage position in the cell storage means and one or a plurality of output destinations of the cell, wherein the cell information is allocated to an input cell. The address information,
One or a plurality of output destinations determined based on the header information of the input cell are held in each of the storage means corresponding one-to-one, and the address information is output from the storage means corresponding to the designated output destination. It is detected whether or not the same address information that has been output is still held in another storage means. If it is determined that the same address information is not held in any of the storage means, the address information is output. Cell information management method, wherein the information is held as address information that can be assigned to a new input cell.