JP5816063B2 - Crossbar circuit for applying adaptive priority scheme and method of operating such a crossbar circuit - Google Patents

Description

  The present invention relates to a crossbar circuit for applying an adaptive priority scheme and a method of operating such a crossbar circuit.

  A crossbar circuit is a switch board for connecting multiple inputs to multiple outputs in a matrix fashion. Thus, a crossbar circuit can be used to interconnect multiple source circuits and multiple destination circuits, thus allowing multiple data inputs from any of the multiple source circuits to the crossbar circuit. Can be output to any one of the destination circuits. The crossbar circuit can be used in various implementations. For example, in a data processing system implementation, such a crossbar circuit is used to store a plurality of processors used to perform data processing operations on data values, and the data values. Multiple memory devices can be used to interconnect, thereby allowing data values to be routed from any memory device to any processor.

  Well-known techniques for generating crossbar circuits route large areas for the crossbar circuit and control signals to those components due to the components required to form the crossbar circuit It requires a large number of control lines that are required to do this, and also consumes a large amount of power. Furthermore, their complexity increases exponentially with size, with most of the known techniques being used with the crossbar circuitry required to interconnect multiple source circuits with multiple destination circuits. To be impractical. Several well-known techniques are discussed below.

  Papers by K Chang et al., “A 50 Gb / s 32 × 32 CMOS Crossbar Chip using Asymmetric Serial Links”, 1999 Symposium on VLSI Circuits, Digest of Technical Papers A22 by T. × 256 CMOS Crossbar Fabric Fabric Designing Pipelining MUX ”, IEEE International Symposium on Circuits and Systems, 2002, 568-571 pages from any input source to any output It describes a crossbar circuit using a hierarchical arrangement of multiplexers. However, such a MUX-based crossbar circuit is relatively large in size and consumes much power. In addition, the crossbar circuit typically requires a significant number of control lines to control the various multiplexers. Such MUX-based designs typically support, at least in part, as the size increases, it becomes increasingly difficult to route the necessary control signals to the various multiplexers, so supporting inputs and outputs Cannot scale with increasing numbers. Furthermore, if the input data is multi-bit data routed on the input bus, the routing of the data path itself becomes very complex.

  R Golshan et al., “A Novel Reduced Swing CMOS Bus Bus Circuit Circuit for High Speed, Low Speed Power VLSI Systems”, IEEE International Symposium 54, IEEE International Symposium 54 An XY type crossbar circuit passing in the vertical direction is described. At the intersection between each input path and output path, a storage element is provided in the form of a flip-flop circuit, and its output controls the transistors used to connect the input path to the output path. However, such a design requires a large number of control lines to program the various flip-flops in order for the crossbar circuit to perform the required routing. Further, input data provided on the input data path is used to drive output data on the associated output data path. As the crossbar circuit grows to accommodate a large number of inputs and outputs, the output data path capacitance increases and correspondingly provides larger drive transistors at the input to overcome the increased capacitance There is a need to. In addition, the connecting transistor driven by the flip-flop at the intersection between the data input path and the data output path also needs to increase in size when the size of the crossbar circuit increases. Furthermore, typically, when the size of the crossbar circuit increases, it becomes necessary to include one or more buffers in the data output path. All these factors cause significant problems in the layout of the crossbar circuit elements and associated control lines, especially when the size of the crossbar circuit is increased to accommodate more inputs and outputs. Hence, this approach is complicated and cannot be extended.

  P Wijetunga's paper "High-Performance Crossbar Design for System-On-Chip", Proceedings of the Third-Re-Ti-P Describes a crossbar design that employs a pass transistor chain as a transmission circuit located at each intersection. When a pass transistor chain is required to connect input data to the output data path, a current sensing circuit located on the output data path is used to detect the input data value. A very disadvantage of this design is that it consumes a large amount of power due to the requirement to position a current sensing device on each output path. In addition, a large number of control signals need to be routed within the crossbar circuit, and in fact, as these control signals increase the size of the crossbar circuit to accommodate more inputs and outputs, the routing requirements Will dominate. Thus, again, this design cannot be easily extended to larger crossbar circuit designs.

  M Borgati et al., “A Multi-Context 6.4 Gb / s / Channel On-Chip Communication Network using 0.18 μm Flash-EEP de S ed e S d, S, Describes a programmable crossbar implemented using a matrix of improved flash EEPROM devices. However, as is apparent from FIG. 26.5.6, the number of memory cells involved in routing data input from the source device to the destination device depends on where those devices are connected in the crossbar, Therefore, the timing of the signal passing through the crossbar is not deterministic. In addition, a large number of control lines are required to allow programming of the various flash EEPROM cells, and a considerable amount of time is required to program the various flash EEPROM cells. Thus, any reconfiguration of the crossbar device takes considerable time.

  Thus, the design of such a crossbar is complex and also requires more input and output devices to be supported by the crossbar due to the proliferation of required control lines. Will increase. Furthermore, the crossbar timing is not deterministic, making the crossbar design unsuitable for a particular implementation.

  In summary, it can be seen from the above discussion that existing crossbar designs typically involve complex routing of control signals, and that complexity increases rapidly as the size of the crossbar increases. It will be. Partly due to the number of control lines required, and partly due to the need to increase the size of certain components provided within the crossbar as the size of the crossbar increases. Often, the design consumes large amounts of power and is not scalable.

  Shared US Published Patent Application No. 2010/0211719 (the entire contents of which are hereby incorporated by reference) allows routing patterns to be cached locally at intersections in the crossbar and then route data It describes the crossbar circuit design used to do this. This significantly reduces routing congestion when generating a wiring layout for the crossbar circuit. The design can be easily extended, and thus the crossbar circuit can be easily utilized even when the number of source and destination circuits connected to the crossbar circuit is large. In addition, the design generates a standard layout that provides a fixed latency for the transfer of data through the crossbar circuit.

  Another problem in crossbar design is how to provide a crossbar with collision detection and resolution capabilities. Multiple requests for the same destination in the switching fabric are referred to as collisions. As the number of sources and destinations increases, collisions become more frequent. In such situations, arbitration becomes a bottleneck of the overall efficiency of the crossbar circuit.

The most modern switching fabric mainly consists of two modules: a crossbar that transmits data and an arbiter that makes up the crossbar. In such an implementation, the source circuit sends a channel request to the arbiter. The arbiter samples all requests and uses some prioritization scheme to accept some or all of the requests and configures the crossbar accordingly. This scheme has two major problems with scalability.
1) Routing all request signals from the source circuit to the arbiter and returning all acceptance signals becomes increasingly difficult in larger systems.
2) The arbiter needs to know all incoming requests, as well as the current state of the crossbar, before it can make a decision. Monitoring the state of the crossbar on a cycle-by-cycle basis requires additional logic as well as interconnection. This contributes to additional delay.

  Many attempts have been made to address the scalability and arbitration delay of packet switching networks. Chi H. Other papers “Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers”, IEEE International Conference on Computer Design, 14-16 Oct. In 1991, pages 233-238, the author describes an arbiter disassembly that allows some requests to be accepted before the arbitration process is complete. However, the worst-case arbitration delay remains the same. In general, the arbitration delay increases linearly with size.

  Delgado-Frias et al., “A VLSI Crossbar Switch with Wrapped Wave Front Arbitration”, IEEE Transactions on Circuits and Systems, Volume 50, Issue 50. 2003, pages 135-141, and Kavaldjiev N. A paper by A et al., “A Virtual Channel Router for On-chip Networks”, IEEE International SoC Conference, 12-15 Sept. On pages 2004, 289-293, the author discusses the handling of arbitration in the crossbar. However, the disclosed implementation is not scalable and is limited to a 4 × 4 size crossbar.

  Shin E. In an article by "Round-robin Arbiter Design and Generation", International Symposium on System Synthesis, 2002, pages 243-248, the author proposes a tool for generating round robin arbiters. The approach is hierarchical, trying to make a 32 × 32 switch from a 4 × 4 switch.

  William W. Plummer's paper "Asynchronous Arbiters", IEEE Transactions on Computers Archive Volume 21, Issue 1 (January 1972), pages 37-42, Charles E. et al. Molnar et al., “Simple Circuits that Work for Complicated Reasons”, International Symposium on Advanced Research in Asynchronous Circuits and Systems. 2000. (ASYNC 2000) Proceedings, and Mark B. et al. In the paper by Joseph et al. "CMOS Design of the Tree Arbiter Element", IEEE Transactions on VLSI systems, Volume 4, Issue 4, Dec 1996, Dec 1996, pages 472-476, arbitration is described. . These designs take advantage of metastability to achieve randomness. However, delays in metastable systems can sometimes be high, which limits their use in real-time systems that require reliable throughput.

  In summary, many solutions found in the literature use a hierarchical approach to making large crossbar switches using 2x2 or 4x4 switches. Therefore, the delay increases linearly with the size of the crossbar switch. This leaves no room for voltage scaling for a wide range of parallel systems (SIMD / MIMD type applications).

  Further, for example, the above-mentioned paper “A Virtual Channel Router for On-chip Networks”, IEEE International SoC Conference, 12-15 Sept. In previous attempts to integrate arbiters and crossbars together, as discussed on pages 2004, 289-293, it was only possible to bring them in close proximity. However, the logic and interconnections for both functionalities remained incompatible.

  In conventional implementations, collision detection and resolution is done hierarchically. This is accomplished in multiple stages of arbitration logic, after each stage the number of requests is reduced by a certain percentage.

  Shared US Published Patent Application No. 2010/0211720 (the entire contents of which are incorporated herein by reference) implements a very effective solution to conflict by applying a predetermined priority scheme. While providing a very standard design, with uniform delay across all paths, and requiring few control lines designed by a typical prior art crossbar, A self-arbitrate design of the crossbar circuit is described. Such a crossbar circuit can be easily expanded to form a large crossbar.

  However, certain types of priority schemes are still difficult to implement efficiently, for example, adaptive priority, where the associated priority of the source circuit changes during each application of the adaptive priority scheme. It is a ranking scheme. US 2010/0211720 proposed the use of a priority configuration module that is capable of reprogramming values in a selected priority storage circuit of the crossbar in a priority assignment mode of operation. It is also possible to make such a priority configuration module adaptive by monitoring the operation of the crossbar and deciding how to update the priority storage circuit depending on the analysis. It was also confirmed. However, such an approach affects the efficiency of the crossbar for a number of reasons.

  First, in order to reprogram the priority storage circuit, it is necessary to enter a dedicated priority assignment mode of operation, whereby a clock cycle is simply spent performing the priority update process. End up. Also, it is typically only possible to reprogram the crossbar cell storage circuit connected to one data output path at a time. Further, for the adaptive priority configuration module, firstly, information representing the operation of the crossbar is extracted from the crossbar, then the extracted information is analyzed and then stored in the associated priority storage circuit. In order to do so, it is necessary to enter the modified priority data into the crossbar, thereby resulting in an inefficient update process.

  One type of adaptive priority scheme that has traditionally been difficult to implement efficiently is that the associated priority of the various source circuits depends on which source circuit gets the current arbitration process. It is an updated longest time elapsed (LRG) priority scheme. Specifically, if the source circuit X gets an arbitration process, all sources having a lower priority than the source X will increase their priority and give a higher priority than the source X according to the LRG scheme. All sources that have have their priority maintained at their current level, and source X is demoted to have the lowest relative priority.

  The LRG priority scheme guarantees fairness and better quality of service (QoS) than other priority schemes (eg, round robin, pseudo-round robin, random priority assignment, etc.), but its hardware Implementation typically introduces significant overhead in the area, performance, and energy consumption of the crossbar circuit. In addition, hardware complexity increases in a quadratic manner with the size of the crossbar circuit.

  In current switching fabrics that support LRG, the arbiter updates the priority assigned to the different sources by recording all incoming and acceptance requests in the network. This requires additional memory, processing elements, and wires to implement it in hardware.

US Published Patent Application No. 2010/0211719 US Published Patent Application No. 2010/0211720

Paper by K Chang et al. “A 50 Gb / s 32 × 32 CMOS Crossbar Chipping Asymmetric Serial Links”, 1999 Symposium on VLSI Circuits, Digest of Technical Papers page 22 T Wu et al., “A 2Gb / s 256 × 256 CMOS Crossbar Switch Fabric Core Designing Pipelined MUX”, IEEE International Symposium on Circuits and Systems 68, 2nd page. R Golshan et al., “A Novel Reduced Swing CMOS Bus Bus Circuit Circuit for High Speed Low Power VLSI Systems, IEEE International Symposium on Circus 54, IEEE 1-35”. P Wijetunga's paper, “High-Performance Crossbar Design for System-On-Chip”, Proceedings of the Third-Japan-Ari-Smop M Borgati et al., “A Multi-Context 6.4 Gb / s / Channel On-Chip Communication Network using 0.18 μm Flash-EEP de S ed e S d, S, Chi H. Other papers “Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers”, IEEE International Conference on Computer Design, 14-16 Oct. 1991, pages 233-238 Delgado-Frias et al., “A VLSI Crossbar Switch with Wrapped Wave Front Arbitration”, IEEE Transactions on Circuits and Systems, Volume 50, Issue 50. 2003, pages 135-141 Kavaldjiev N.M. A paper by A et al., “A Virtual Channel Router for On-chip Networks”, IEEE International SoC Conference, 12-15 Sept. 2004, 289-293 pages Shin E. Other paper "Round-robin Arbiter Design and Generation", International Symposium on System Synthesis, 2002, pages 243-248. William W. Plummer's paper "Asynchronous Arbiters", IEEE Transactions on Computers Archive Volume 21, Issue 1 (January 1972), pages 37-42. Charles E. Molnar et al., “Simple Circuits that Work for Complicated Reasons”, International Symposium on Advanced Research in Asynchronous Circuits and Systems. 2000. (ASYNC 2000) Proceedings Mark B. Joseph et al., “CMOS Design of the Tree Arbiter Element”, IEEE Transactions on VLSI systems, Volume 4, Issue 4, Dec 1996, pages 472-476.

  Therefore, it would be desirable to provide an improved crossbar design that overcomes some of the aforementioned problems associated with supporting an adaptive priority scheme.

  Viewed from a first aspect, the present invention interconnects a plurality of source circuits and a plurality of destination circuits, so that data input from any of the plurality of source circuits to the crossbar circuit is A crossbar circuit capable of outputting to any one of the plurality of destination circuits, the plurality of data input paths passing through the crossbar circuit, each data input path including the plurality of sources A plurality of data input paths that can be connected to one of the circuits and provide a plurality of word lines, and a plurality of data output paths that pass through the crossbar circuit across the plurality of data input paths. Each data output path can be connected to one of the plurality of destination circuits and provides a plurality of bit lines, and a plurality of data output paths and one of the data input paths And the A crossbar cell associated with each intersection with one of the data output paths, each crossbar cell storing a routing value depending on a voltage on at least one of the plurality of bit lines. A configuration storage circuit that can be programmed in an arbitration mode of operation, wherein the routing value is a bit of the data output path at the associated intersection along the data input to the associated intersection along the word line of the data input path The first value is programmed to indicate that it is output on the line, and the routing value is a bit of the data output path at the associated intersection along the data input to the associated intersection along the word line of the data input path. In the configuration memory circuit, which is programmed as indicated by the second value that it is not output on the line, and in transmission operation mode Responsive to a routing value having the first value to detect a data input along a word line of the data input path and to output an indication of that data on a bit line of the data output path at the associated intersection An arbitration circuit that operates in the arbitration mode of operation depending on a transmission request received by a crossbar cell from a transmission circuit and a source circuit connected to a data input path of an associated intersection, the source circuit comprising: If the transmission request is asserted to indicate that data is desired to be routed from the data input path to the data output path at the relevant intersection, the arbitration circuit may use the same data output to apply the adaptive priority scheme. Other crossbar cell arbitration circuits associated with the path Operated in combination and arranged to selectively modify the voltage of a plurality of bit lines, and therefore when there are a plurality of asserted transmission requests for the same data output path, the same data output path and The only associated crossbar cell configuration storage circuit has its routing value programmed to the first value, thereby conflicting between the plurality of asserted transmission requests according to the adaptive priority scheme. In order to apply the arbitration circuit and the adaptive priority scheme, the priority data identifying which of the plurality of bit lines should have their voltages modified by the associated arbitration circuit A priority storage circuit configured to store an adaptive priority score by an arbitration circuit A priority storage circuit configured to self-update the priority data stored therein depending on the voltage of at least one of the plurality of bit lines during each application A crossbar circuit comprising a bar cell is provided.

  According to the present invention, a crossbar cell is associated with each intersection between a data input path and a data output path, and each crossbar cell depends on a routing value stored in an associated configuration storage circuit in a transmission mode of operation. And resolving conflicts between a plurality of asserted transmission requests in a transmission circuit and arbitration mode of operation arranged to selectively connect data on the data input path to the data output path. Therefore, an arbitration circuit that operates in combination with an arbitration circuit of another crossbar cell is provided. Specifically, when a transmission request is asserted from a source circuit to a crossbar cell, the arbitration circuit of that crossbar cell will apply to other crossbar cells associated with the same data output path in order to apply the adaptive priority scheme. Operates in combination with the arbitration circuit to selectively modify the voltage on multiple bit lines, so if there are multiple asserted transmission requests for that same data output path, the only associated with the same data output path The crossbar cell configuration memory circuit has its routing value programmed to a first value (ie, a value that causes the crossbar cell to link its data input path to its data output path in the transmission mode of operation).

  In addition, each crossbar cell has priority data that identifies which of the multiple bit lines should have their voltages modified by the associated arbitration circuit in order to apply the adaptive priority scheme. A priority storage circuit configured to store, depending on the voltage of at least one of the plurality of bit lines, during each application of the adaptive priority scheme by the arbitration circuit, stored therein A priority storage circuit configured to self-update the priority data.

  Thus, according to the present invention, in arbitration mode of operation, only one source circuit is granted access to a particular data output path at any point in time to detect a conflict of the particular data output path. It can be seen that the bit lines of the data output path are reused to resolve these conflicts and to update the priority data stored in the priority storage circuit. This provides a fast and scalable technique for implementing an adaptive priority scheme within a crossbar circuit. The approach can be greatly expanded over prior art techniques (in embodiments of the invention, hardware complexity increases linearly with the size of the interconnect network provided by the crossbar). It can be implemented with little overhead on the interconnect network and with little performance impact.

  In the arrangement of the present invention, both the arbiter function and the crossbar function are integrated into the crossbar circuit. Arbiters are dominated by logic, but crossbars are dominated by routing, and by combining these two functions together in the crossbar cell of the crossbar circuit, the routing space and the silicon space in the chip More efficient utilization is achieved. In addition, the communication overhead that conventionally occurs between the crossbar and the arbiter is now more or less eliminated. By storing the crossbar configuration in the crossbar cell associated with each intersection in the crossbar circuit, it is possible to reuse the bit lines of the data output path for arbitration.

  According to the present invention, the crossbar circuit can be laid out in the form of an SRAM array topology, the crossbar cells are laid out as an array, the data input path provides a word line, and the data output path is a bit line. I will provide a. Such an arrangement allows a very efficient layout, both in terms of size and in terms of the number of interconnections required.

  Although the adaptive priority scheme can take a variety of forms, in one embodiment, the adaptive priority scheme is a longest elapsed time (LRG) scheme after acceptance. As previously mentioned, LRG schemes have traditionally been complex to implement in hardware, and therefore the ability to provide LRG schemes using embodiments of the present invention is much superior to well known prior art approaches. Significant improvement.

  In one embodiment, each data output path provides n bit lines, and each configuration memory circuit has a routing value programmed into the configuration memory circuit, of which n For up to n crossbar cells associated with one and thus associated with the same data output path, the configuration memory circuit of those crossbar cells has a different associated bit line of the n bit lines. Within each crossbar cell, an arbitration circuit and a priority storage circuit are associated with n-1 bit lines except for one bit line associated with the crossbar cell's configuration storage circuit, and the adaptive priority scheme is To apply, the priority storage circuit identifies which of those n-1 bit lines should have their voltage modified by the arbitration circuit.

  In one particular embodiment, the priority storage circuit may be formed of n-1 priority storage elements, one for each of the n-1 bit lines associated with the priority storage circuit. The priority storage element can take a variety of forms, but in one embodiment is formed of SRAM cells.

  In one such embodiment, in the arbitration mode of operation, any crossbar cell arbitration circuit associated with the same data output path that receives the asserted transmission request to apply the adaptive priority scheme comprises: After selectively modifying the voltage on the n bit lines, each configuration memory circuit of the crossbar cell that receives the asserted transmission request samples the voltage on its associated bit line to program the routing value. Configured to do.

  In one embodiment, each crossbar cell is a release circuit coupled to one bit line associated with the crossbar cell's configuration storage circuit, and upon receiving an asserted release request, the channel release circuit: The level on which the second value is stored as the routing value in the configuration memory circuit of the crossbar cell is corrected to the voltage on the one bit line, thereby enabling the reassignment of the data output path. And a release circuit that causes the crossbar cell to release the associated data output path. This allows a source circuit to release a particular data output path when it has finished sending data, thereby allowing another source circuit to later try to capture that data output path It provides a simple and effective mechanism for doing this.

  In one embodiment, the priority storage circuit in those crossbar cells associated with the released data output path depends on the voltage of at least one of the plurality of bit lines and the priority data stored therein In response to the asserted release request to self update. Thus, in such an embodiment, the asserted release request provides a convenient event for triggering the execution of the self-update process and is self-updated during each use of the adaptive priority scheme by the arbitration circuit. Ensure that the process is executed.

  In one embodiment, each priority storage circuit comprises a plurality of priority storage elements, each priority storage element being associated with one of the plurality of bit lines, and within each priority storage circuit The current value of the priority storage element indicates the relative priority level of the source circuit coupled to the crossbar cell containing the priority storage circuit for the associated data output path.

  In one embodiment where the adaptive priority scheme is a longest time elapsed since acceptance (LRG) priority scheme, then the voltage in the priority storage circuit of those crossbar cells associated with the released data output path. Those priority storage elements that are associated with bit lines modified by the release circuit are set to a first value, thereby the relative priority level of each source circuit except the source circuit that releases the data output path. Is increased or maintained. Further, for a crossbar cell that contains a release circuit that has received an asserted release request, the priority storage circuit has its priority storage element cleared to a second value, thereby releasing the data output path. The source circuit to be assigned is assigned a lower priority than the other source circuits. This provides a particularly efficient mechanism for implementing the LRG scheme, and the relative priority level of the source circuit is updated independently for each data output path when that data output path is released.

  In one embodiment, at the time of initialization, each crossbar cell priority storage circuit provides a predetermined relative priority level of the plurality of source circuits for each of the plurality of data output paths. Initialized to value.

  In one embodiment, the initial relative priority level can be specified independently for each data output path. Further, in one embodiment, each priority storage circuit is responsive to a reset signal that is asserted at the time of initialization to set itself to a predetermined value. In one particular embodiment, the individual priority storage elements of each priority storage circuit, when applied with a reset signal, have their values either logic 1 or logic 0 depending on their form. Can take one of two forms.

  In one particular embodiment, each of the bit lines is precharged to a first voltage level, and upon receipt of the asserted release request, the release circuit is configured with a single associated with the crossbar cell's configuration storage circuit. Discharge the voltage on the bit line. In addition, each configuration storage circuit senses its associated bit line voltage to update the routing value to the second value if there is an asserted release request for the associated release circuit, and subsequently A sense amplifier enable latch that performs a discharge operation by the release circuit, thereby releasing the associated data output path. Thus, in such an embodiment, the bit line sensed by the sense amplifier enable latch is discharged and later sampled to release the channel in the crossbar cell.

  In one embodiment, each data input path provides n word lines, and a request to release up to n crossbar cells associated with the same data output path causes n word lines in that same data output path to To be input to the crossbar circuit. Further, each release circuit is associated with one of the n word lines, so for up to n crossbar cells associated with the same data input path, the release circuit of those crossbar cells Having a different associated word line of the n word lines receiving the release request via Thus, in such an embodiment, the release request can be issued in an efficient manner through reuse of the word line of the data input path.

  In one particular embodiment, a release request is issued in the arbitration mode of operation and the control signal identifies whether the n word lines of the associated data input path are carrying a release request or a transmission request. In this way, it is issued by a plurality of source circuits in the arbitration operation mode. Thus, in such an embodiment, the control signal acknowledges whether the information routed on the word line identifies a release request or a transmission request, and therefore whether an arbitration circuit or a release circuit needs to be activated. Can be used for. In one particular embodiment, the control signal actually takes the form of two separate signal lines, one of which is a request_channel signal and the other is a release_channel signal, one of these two signals. Can be set at any point in time. In one embodiment, these two signals are provided on a per-row basis, and therefore, within any particular row, the crossbar cell can be either a release request or a transmission request at any point in time. Will be processing. Some implementations can provide finer granularity of control signals, so that some crossbar cells in a row can handle release requests while the other handles transmission requests. doing.

  Configuration memory circuits of different crossbar cells in the same data output path are associated with different bit lines and the arbitration circuit of those crossbar cells in that data output path receiving the asserted transmission request has n By selectively modifying the voltage on the bit line, the configuration memory circuit of each crossbar cell that receives the asserted transmission request samples the voltage on its associated bit line and subsequently performs the arbitration process. It is possible to implement an adaptive priority scheme by ensuring that only one of the lines is the value that causes the associated configuration storage circuit to store the first value as a routing value. Yes, so that only a single source circuit grants access to the data output path at any point in time To enable it to be.

  In a manner in which the arbitration circuit selectively corrects, the voltages on the n bit lines may change depending on the implementation. However, in one embodiment, each of the bit lines is precharged to a first voltage level to apply the adaptive priority scheme and then receives an asserted transmission request during the arbitration mode of operation. Any crossbar cell arbitration circuit associated with the same data output path selectively discharges the voltages on the n bit lines. Thus, in such an embodiment, the bit line is conditionally discharged to apply an adaptive priority scheme, thereby resolving any conflicts during the arbitration mode of operation.

  There are a number of ways in which a transmission request can be asserted from the source circuit to the crossbar cell. However, in one embodiment, each data input path provides n word lines, and in the arbitration mode of operation, transmission requests for up to n crossbar cells associated with the same data input path are the same data input path. Are input to the crossbar circuit via the n word lines. Thus, in such embodiments, the data input paths reuse themselves in the arbitration mode of operation to provide asserted transmission requests.

  In one particular embodiment, each configuration memory circuit is associated with one of the n word lines, so for up to n crossbar cells associated with the same data input path, the crossbar cell's The configuration memory circuit has a different associated word line of the n word lines through which a transmission request is received.

  In embodiments where n word lines in the data input path and n bit lines in the data output path are reused during the arbitration mode of operation, conflict detection and resolution can be performed in a single stage, thereby It can be seen that there is a significant performance benefit when compared to prior art approaches where collision detection and resolution is done hierarchically in multiple stages.

  In particular, it will be appreciated that conflict detection and resolution can be performed in a single stage for a crossbar circuit containing a matrix of up to n × n crossbar cells.

  However, the techniques of embodiments of the present invention can also be used with crossbar circuits having larger matrix crossbar cells. Specifically, in one embodiment, a matrix of mn × mn crossbar cells, where m is an integer greater than or equal to 2, is provided, the matrix is divided into sections, and a series of arbitration operations are the same. The only crossbar cell configuration storage circuit associated with the data output path is used to apply an adaptive priority scheme to have its routing value programmed to the first value, thereby allowing the adaptation Resolve conflicts between multiple asserted transmission requests according to a type priority scheme. For each arbitration operation in the series, one or more of the sections in the plurality of sections undergo the arbitration operation.

  In one particular embodiment, each arbitration operation operates on a single section, so that after performing the series of arbitration operations, all of the plurality of sections are undergoing the arbitration operation. Thus, as an example, for a 64 × 64 crossbar circuit with a 16-bit data input path and a data output path, the crossbar circuit can be divided into four sections and the arbitration operation is Each is executed sequentially. In one embodiment, the counter can increment every cycle to select the section to process during arbitration in that cycle (a 2-bit counter is sufficient in the above example). Such an implementation still maintains minimal wiring and logic overhead benefits, but the arbitration latency for a given request can vary depending on the section to which the request relates (see above). In the example, the latency can vary from 1 to 4 cycles). The priority data is then self-updated after all sections have been processed.

  In an alternative embodiment, all of the plurality of sections include a configuration memory circuit whose routing value is programmed to the first value in a first arbitration operation of the series. In order to identify one of these, a first arbitration operation is performed. Then, in a second arbitration operation of the series, the one of the sections identified by the first arbitration operation is configured to store the configuration value in that section whose routing value is programmed to the first value. A second arbitration operation is performed to identify the circuit. According to such an embodiment, the crossbar is again divided into sections, in which case arbitration is performed in two steps, first between the sections and then all within a given section. It is executed hierarchically between the requests. The same group of bit lines can be used for both arbitration steps. The priority data is then self-updated after both arbitration steps have been performed.

  In one embodiment, each crossbar cell comprises two configuration storage circuits, the first being used to detect whether the associated section contains the highest priority asserted transmission request. The second is used in subsequent arbitration steps to detect whether the highest priority asserted transmission request is associated with that particular crossbar cell.

  As an example, in a 64 × 64 crossbar with a 16-bit data input path and a data output path, the crossbar can again be divided into four sections. If section 0 has the highest priority and at least one source associated with that section asserts a transmission request, the first configuration store in each crossbar cell of that section during the first stage of arbitration The circuit will have a routing value programmed to the first value, while the other sections will have those routing values programmed to the second value (in either case, the program Occurs as a result of the voltage on the bit line associated with each first configuration memory circuit). In the next cycle, only the transmission request asserted for section 0 is considered and the bit line is used again for arbitration, this time the second configuration storage circuit senses the associated bit line. In a particular crossbar cell, if both configuration storage circuits have their routing values set to the first value, this means that the associated asserted transmission request has been prioritized and the data transmission mode of operation. Means that the crossbar cell connects its input to its output.

  Such an implementation has a fixed two-cycle arbitration latency without sacrificing some additional logic, but without sacrificing any additional interconnection. With 16 bit lines in the data output path, it is possible to arbitrate between up to 16 sections, and each section can receive up to 16 asserted transmission requests. Thus, the arbitration latency can hold up to 256 × 256 crossbars in two cycles for one crossbar.

  In one embodiment, when the crossbar cell has its routing value programmed to a first value during the arbitration mode of operation, a grant signal is associated to confirm that the asserted transmission request has been granted. Asserted to the source circuit. In one embodiment, the source circuit can only send a single request at a time, and in such embodiments, typically only a single grant signal is issued per row. However, in alternative embodiments, the source circuit may be able to send multiple requests at a time, and in such embodiments, multiple grant signals may be provided per line. A consent signal is associated with each data output path.

  The transmission circuit can be operated in various ways. However, in one embodiment, in the transmission mode of operation, each data output path associated with the crossbar cell is precharged to a first logic level prior to data transmission, and the transmission circuit of each crossbar cell is connected to the data output path and Comprising a first and a second switch connected in series between two logic levels, and in a transmission mode of operation, the first switch depends on the routing value stored in the associated configuration storage circuit Opened or closed, the second switch is opened or closed depending on the data input on the data input path. In one particular embodiment, the first logic level is the supply voltage level Vdd and the second logic level is grounded. Thus, with such an arrangement, the data on the input data path does not directly drive the data on the output data path, and instead the data on the output data path remains at the first logic level. Or, if both the first and second switches are closed, they are discharged to a second logic level.

  With such a transmission circuit arrangement, the transmission circuit does not need to be changed regardless of the size of the crossbar circuit, and thus provides input data on the length of the data output path and even on the input data path. The drive circuit also does not need to be resized when the crossbar circuit size increases. Therefore, when the size of the crossbar circuit increases, it is not necessary to change the circuit of each crossbar cell, and instead, it is only necessary to increase the number of crossbar cells. Thus, by using such a design, the delay of the crossbar circuit increases linearly with size, and the design of such a crossbar circuit can be reduced to (eg, 128 × 128 or 256 × 256 inputs / Can be used with very large crossbars (with output). In addition, the design is very standard and the delay across all paths through the crossbar circuit is uniform.

  In one embodiment, each of the data input paths comprises n word lines for carrying an n-bit input data value during a transmission mode of operation, and each of the data output paths is n during the transmission mode of operation. With n bit lines for carrying a bit data value, at least a second switch is replicated for each bit line. Thus, the design of the transmission circuit can easily be adapted to various sizes of data input and data output paths without any significant increase in the complexity of any crossbar circuit.

  In one embodiment, in a transmission mode of operation, when the routing value is the first value and the input data bit on the corresponding word line is the first logic level, the bit line of the data output path is Pulled to a logic level of 2. Thus, if the routing value stored in the configuration memory circuit indicates that the data input path should be coupled to the data output path and that the data on the data input path is at a logic one level, the data The output path is discharged to the second logic level.

  In one embodiment, each crossbar cell is configured to turn off the first switch regardless of the routing value while precharging the associated data output path to the first logic level, and the first A conditional discharge circuit is further provided to allow the switch to be controlled by the routing value and subsequently to precharge the associated data output path to the first logic level. Thus, such a conditional discharge circuit isolates the bit line from the input while the bit line of the data output path is precharged, thereby reducing the power consumption of the precharge operation. Such an arrangement also allows the data input path to be driven simultaneously with the precharge operation by a conditional discharge circuit that separates the data output path from the current input, thereby increasing the speed of the operation. Make it possible.

  Further, by using the transmission circuit arrangement described above, all bit lines of the data output path are precharged to a first logic level and then the input value and routing of the associated word line of the data input path. Note that depending on the value, it remains at the first logic level or transitions to the second logic level. As a result, no situation occurs where the voltages on two adjacent bit lines move in opposite directions, thereby reducing capacitive coupling effects and thereby increasing the speed of operation.

  In embodiments where the data output path is precharged prior to data transfer and then selectively discharged depending on the routing and data input values, the power consumption of the crossbar circuit is reduced through the use of a sense amplifier circuit can do. Specifically, in one embodiment, the crossbar circuit detects a data output on the bit line of the data output path during the transmission mode of operation, thereby causing the voltage on the bit line of the data output path to be a second logic level. It further comprises a sense amplifier circuit that allows detection of a transition to the second logic level before reaching the level. Since the detection of the transition occurs before the bit line of the data output path reaches the second logic level, the power required to precharge the bit line of the data output path to the first logic level is greatly reduced. Reduced.

  Thus, in embodiments where such data output path precharge occurs, further power savings can be obtained by suitably encoding the input data before being provided to the crossbar circuit. Specifically, in one embodiment, the crossbar circuit includes an encoding circuit between each of the plurality of source circuits and the plurality of data input paths, each of the plurality of data output paths, and the plurality of the plurality of data output paths. A decoding circuit between the source circuit and the encoding circuit, wherein the encoding circuit applies an encoding operation to encode the input data provided by each source circuit into an encoding format, and the original input data Pulls the data output path to the second logic level when compared to the number of times it may be necessary to pull the data output path to the second logic level when And the decoding circuit identifies original input data provided by the source circuit from the encoded data output on the data output path. Sea urchin, applying the corresponding decoding operation.

  In one particular embodiment, the encoding operation is that the encoding format generated from the input data is only a logic one value when the input data changes, and the data output path changes accordingly. Make sure it is discharged only when you do. The decoding circuit then re-creates the original input data from the encoded data output on the data output path.

  Due to the standard design of the crossbar circuit of the embodiment of the present invention and the manner in which the transmission circuit of each crossbar cell operates, a plurality of source circuits should be connected to one end of a plurality of data input paths. This greatly increases the flexibility in designing the layout of devices in which crossbar and source circuits are provided. Similarly, multiple destination circuits can be connected to either end of multiple data output paths.

  In one embodiment, a series of word line drivers may be used to propagate data input values along the data input paths to the various crossbar cells connected to those data input paths. In a single request embodiment where multicasting is not supported and therefore each source only requires access to a single output path at a time, in situations where it is not required, Considerable power can be consumed in propagating data along the whole. In one embodiment, this power consumption is alleviated by providing a partially activated network arrangement. Specifically, in one embodiment, each data input path consists of a plurality of input path portions separated by a word line driver, each word line driver being provided along an associated data input path, It is activated depending on the routing value stored in the configuration memory circuit of the crossbar cell, which is farther from the source circuit than the word line driver. As a result, each word line driver is provided along an associated data input path, but at least one crossbar cell configuration storage circuit that is further from the source circuit than the word line driver has the first Fired only if it has a routing value set to value. Such an approach can result in significant power savings.

  The crossbar circuit of the embodiment of the present invention may be used in various systems. However, according to the second aspect of the present invention, data processing operations are performed in parallel on a plurality of memory devices for storing data values and a plurality of data values stored in the plurality of memory devices. And a crossbar circuit according to the first aspect of the invention for routing data values from any of the plurality of memory devices to any of the plurality of processors. A data processing apparatus is provided.

  The crossbar circuit of embodiments of the present invention is a particularly simple, scalable, and power efficient route for routing data values from any of the memory devices to any of the processors. Provide mechanism.

  Viewed from a third aspect, the present invention interconnects a plurality of source means and a plurality of destination means, so that data input from any of the plurality of source means to the crossbar circuit is A crossbar circuit that can output to any one of the plurality of destination means, and a plurality of data input path means that pass through the crossbar circuit, wherein each data input path means A plurality of data input path means for connecting to one of the source means and providing a plurality of word line means and passing through the crossbar circuit across the plurality of data input path means A plurality of data output path means, each data output path means being connected to one of the plurality of destination means and providing a plurality of bit line means Output length A crossbar cell means associated with each intersection between the means, one of the data input path means and one of the data output path means, each crossbar cell means comprising a plurality of bit lines Configuration storage means programmable in an arbitration mode of operation for storing a routing value in dependence on a voltage on at least one of the means, the routing value being along the word line means of the data input path means The first value is programmed to indicate that data input to the associated intersection is output on the bit line means of the data output path means at the associated intersection, and the routing value is the data input path means The data input to the associated intersection along the word line means is the bit line of the data output path means at the associated intersection. Detecting and relating data input along the word line means of the data input path means in the configuration storage means and transmission mode of operation, programmed as indicated by the second value not to be output on the stage Connected to a transmission means and an associated intersection data input path means responsive to a routing value having the first value so that an indication of the data is output on the bit line means of the data output path means at the intersection. Arbitration means for operating in the arbitration mode of operation depending on a transmission request received by the crossbar cell means from the source means, wherein the source means is at the associated intersection from the data input path means. If a transmission request is asserted to indicate that you want to route data to the data output path means, Arbitration means operates in combination with arbitration means of other crossbar cell means associated with the same data output path means to apply an adaptive priority scheme to selectively select voltages on a plurality of bit line means. If there are multiple asserted transmission requests for the same data output path means, the configuration storage means of the only crossbar cell means associated with the same data output path means is An arbitration means having its routing value programmed to a first value, thereby resolving a conflict between the plurality of asserted transmission requests according to the adaptive priority scheme; and an adaptive priority scheme In order to apply, any of the plurality of bit line means has an associated arbitrage Priority storage means for storing priority data identifying whether those voltages are to be modified by the network means, a plurality of bits during each application of the adaptive priority scheme by the arbitration means A crossbar circuit is provided comprising crossbar cell means comprising priority storage means for self updating the priority data stored therein depending on the voltage of at least one of the line means.

  Viewed from a fourth aspect, the present invention interconnects a plurality of source circuits and a plurality of destination circuits, so that data input from any of the plurality of source circuits to the crossbar circuit is A method of operating a crossbar circuit so that it can be output to any one of the plurality of destination circuits, wherein the crossbar circuit is a plurality of data input paths passing through the crossbar circuit. Each data input path can be connected to one of the plurality of source circuits and provide a plurality of word lines and a plurality of data input paths and a cross across the plurality of data input paths A plurality of data output paths passing through the bar circuit, each data output path being connectable to one of the plurality of destination circuits and providing a plurality of bit lines Sutra And adopting a crossbar cell associated with each intersection between one of the data input paths and one of the data output paths, and routing in an arbitration mode of operation. Programming a value to each crossbar cell, wherein the routing value is programmed depending on the voltage on at least one of the plurality of bit lines, the routing value along the word line of the data input path The first value indicates that the data input to the associated intersection is output on the bit line of the data output path at the associated intersection, and the routing value is applied to the word line of the data input path. Data input to the associated intersection along the line is output on the bit line of the data output path at the associated intersection. The second value is programmed to indicate that there is no data input along the word line of the data input path in the transmission mode of operation and the indication of that data at the associated intersection. Responsive to a routing value having the first value to output on a bit line of the data output path, and in the arbitration mode of operation, a source circuit connected to the data input path of the associated intersection Depending on the transmission requirements received by the crossbar cell, operating the arbitration circuit in the crossbar cell, wherein the source circuit transfers data from the data input path to the data output path at the relevant intersection. If a transmission request is asserted to indicate that you want to route, The translation circuit operates in combination with other crossbar cell arbitration circuits associated with the same data output path to apply adaptive priority schemes to selectively modify the voltages on multiple bit lines, Thus, if there are multiple asserted transmission requests for the same data output path, the only crossbar cell configuration storage circuit associated with the same data output path will have its routing value programmed to the first value. And resolving a conflict between the plurality of asserted transmission requests according to the adaptive priority scheme, and among the plurality of bit lines to apply the adaptive priority scheme Priority data that identifies which of these should be corrected by the associated arbitration circuit Between the step of storing in a priority storage circuit in the crossbar cell and each application of the adaptive priority scheme by the arbitration circuit depending on the voltage of at least one of the plurality of bit lines. Configuring a priority storage circuit to self-update the priority data.

  The invention will now be further described, by way of example only, with reference to an embodiment thereof illustrated in the accompanying drawings.

FIG. 3 is a block diagram of a crossbar circuit, according to one embodiment. FIG. 3 illustrates how a priority storage circuit provided in accordance with each crossbar cell can be used in one embodiment. FIG. 6 illustrates how a release circuit can be used in one embodiment to allow a crossbar cell to release a particular data output path (also referred to herein as a channel). FIG. 6 illustrates how a priority storage circuit can be updated to support an LRG priority scheme, according to one embodiment. FIG. 6 illustrates how a priority storage circuit can be updated to support an LRG priority scheme, according to one embodiment. FIG. 6 illustrates how a priority storage circuit can be updated to support an LRG priority scheme, according to one embodiment. FIG. 6 illustrates how a priority storage circuit can be updated to support an LRG priority scheme, according to one embodiment. FIG. 6 illustrates how a priority storage circuit can be updated to support an LRG priority scheme, according to one embodiment. FIG. 6 illustrates how a priority storage circuit can be updated to support an LRG priority scheme, according to one embodiment. FIG. 6 illustrates how a priority storage circuit can be updated to support an LRG priority scheme, according to one embodiment. FIG. 6 illustrates how a priority storage circuit can be updated to support an LRG priority scheme, according to one embodiment. FIG. 6 shows a circuit provided in each crossbar cell for multiple crossbar cells in a column. FIG. 6 shows a circuit provided in each crossbar cell for multiple crossbar cells in a column. FIG. 6 shows a circuit provided in each crossbar cell for multiple crossbar cells in a row. FIG. 6 shows a circuit provided in each crossbar cell for multiple crossbar cells in a row. FIG. 3 illustrates in more detail a transmission circuit, an arbitration circuit, and a priority storage circuit that may be provided in each crossbar cell, according to one embodiment. FIG. 3 illustrates in more detail a transmission circuit and a release circuit that may be provided in each crossbar cell, according to one embodiment. FIG. 4 schematically illustrates an implementation of a packet switching crossbar, according to one embodiment. FIG. FIG. 3 illustrates in more detail the components provided in each crossbar cell of a crossbar circuit, according to one embodiment. FIG. 3 illustrates in more detail the components provided in each crossbar cell of a crossbar circuit, according to one embodiment. FIG. 3 illustrates in more detail the components provided in each crossbar cell of a crossbar circuit, according to one embodiment. FIG. 3 illustrates in more detail the components provided in each crossbar cell of a crossbar circuit, according to one embodiment. FIG. 6 shows in more detail the components provided in each crossbar cell of a crossbar circuit, according to an alternative embodiment. FIG. 6 shows in more detail the components provided in each crossbar cell of a crossbar circuit, according to an alternative embodiment. FIG. 6 shows in more detail the components provided in each crossbar cell of a crossbar circuit, according to an alternative embodiment. FIG. 6 shows in more detail the components provided in each crossbar cell of a crossbar circuit, according to an alternative embodiment. FIG. 6 illustrates in more detail the arrangement of configuration memory elements provided within each crossbar cell, according to one embodiment. FIG. 3 is a diagram illustrating a configuration of a pulse generator for generating a discharge signal and a sense enable (SE) signal according to an embodiment. FIG. 3 is a diagram illustrating a configuration of a pulse generator for generating a discharge signal and a sense enable (SE) signal according to an embodiment. FIG. 3 is a diagram illustrating a configuration of a pulse generator for generating a discharge signal and a sense enable (SE) signal according to an embodiment. FIG. 6 illustrates how a channel_free signal is generated according to one embodiment. An encoding that may be used in one embodiment to encode input data before input to the crossbar circuit and to decode output data from the crossbar circuit to reduce power consumption in the crossbar circuit. It is a figure which shows a circuit and a decoding circuit. An encoding that may be used in one embodiment to encode input data before input to the crossbar circuit and to decode output data from the crossbar circuit to reduce power consumption in the crossbar circuit. It is a figure which shows a circuit and a decoding circuit. An encoding that may be used in one embodiment to encode input data before input to the crossbar circuit and to decode output data from the crossbar circuit to reduce power consumption in the crossbar circuit. It is a figure which shows a circuit and a decoding circuit. An encoding that may be used in one embodiment to encode input data before input to the crossbar circuit and to decode output data from the crossbar circuit to reduce power consumption in the crossbar circuit. It is a figure which shows a circuit and a decoding circuit. An encoding that may be used in one embodiment to encode input data before input to the crossbar circuit and to decode output data from the crossbar circuit to reduce power consumption in the crossbar circuit. It is a figure which shows a circuit and a decoding circuit. FIG. 6 illustrates how a crossbar circuit with a narrow data input path and a data output path can be arranged to operate according to one embodiment. FIG. 6 illustrates how a crossbar circuit with a narrow data input path and a data output path can be arranged to operate in accordance with an alternative embodiment. FIG. 6 illustrates how a crossbar circuit with a narrow data input path and a data output path can be arranged to operate in accordance with an alternative embodiment. FIG. 3 illustrates how a crossbar circuit can be used in a partially enabled configuration, according to one embodiment.

  FIG. 1 shows a top view of a proposed switching fabric comprising a crossbar circuit according to one embodiment and a plurality of source and destination circuits connected thereto. The crossbar circuit includes a plurality of data input paths 12 extending in a first direction through the crossbar circuit and a plurality of data output paths 50 extending in a second direction crossing the first direction. In the embodiment of FIG. 1, both of these paths are formed by a multi-bit bus, and in particular, each data input path includes a plurality of word lines, and each data output path includes a plurality of bit lines. .

  At the intersection between each data input path and data output path, a crossbar cell 20 is provided and used to selectively route data received on the associated data input path onto the associated data output path. Is done. Each crossbar cell includes a configuration storage element for storing the on / off state of each crossbar cell, so that when the crossbar cell is in the on state, the input data received on the data input path is the data output path. And the cell is in the off state, the input data simply passes through the cell without being routed on the associated data output path.

  Each data input path 12 is coupled to an associated source circuit 30 from which input data 10 can be received, and each data output path 50 receives output data 70 provided on that data output path. Connected to an associated destination circuit 40 that is disposed.

  In the embodiment shown, the bit line of each data output path 50 is precharged using a precharge module 55, which then transmits the data of that source circuit from one of the source circuits. Depending on the data input to the crossbar cell connected to the output path, it is selectively discharged. This selective discharge of the bit line is detected by a sense amplifier circuit 65 to generate output data 70.

  When the crossbar is in the transmission mode of operation, data is routed through the crossbar circuit in the manner described above, but the crossbar circuit is not necessarily in the transmission mode of operation. Specifically, the crossbar circuit has an arbitration mode of operation while detecting and resolving any conflicts between transmission requests issued by the various source circuits 30. Specifically, multiple requests for the same destination circuit in the switching fabric are referred to as collisions, and collisions become more frequent as the number of sources and destinations increases. As will be discussed in more detail later, each crossbar cell 20 includes an arbitration circuit that detects the presence of a plurality of asserted transmission requests in the arbitration mode of operation, and a plurality of such Operates in combination with other crossbar cell arbitration circuits by reusing bit lines in the data output path to implement adaptive priority schemes and resolve those conflicts in the case of asserted transmission requests To do. The proposed approach provides a high speed, low power, and highly scalable solution to detect and resolve such collisions.

  Each crossbar cell includes a priority storage circuit for storing priority data referenced by the arbitration circuit when the adaptive priority scheme is implemented, the priority storage circuit being adapted by the arbitration circuit. During each application of the priority scheme, the bit lines are reused and configured to self-update the priority data stored therein.

  In FIG. 1, the source circuit is shown on the left side of the crossbar and the destination circuit is shown on the bottom of the crossbar, but the source circuit can be provided on either side of the crossbar circuit, and similarly Circuitry can be provided at either end of the data output path. Thus, it will be appreciated that the crossbar circuit of embodiments of the present invention provides the flexibility to place the source at either horizontal end and the destination at either vertical end. . This simplifies floorplanning of the design by reducing routing congestion.

  FIG. 2 illustrates how the bit lines in the data output path can be reused to detect and resolve conflicts during the arbitration mode of operation. In this embodiment, there are 16 source circuits connected to the crossbar circuit that can issue transmission requests 0-15. For any particular data output path 50, each source circuit is associated with a crossbar cell 20 that is incorporated in its configuration storage circuit in the form of a sense amplifier and latch. Thus, source 0 is associated with a crossbar cell containing sense amplifiers and latches 100, source 1 is associated with a crossbar cell containing sense amplifiers and latches 105, and source 2 contains sense amplifiers and latches 110. Associated with the crossbar cell, the remaining source circuit is similarly associated with the crossbar cell containing the sense amplifier and latch 115.

  In the arbitration mode of operation, the precharge module 55 precharges all the bit lines of each data output path 50, after which the bit lines depend on the asserted transmission requirements and are also an adaptive priority scheme. According to the above, it is selectively discharged. In this example, each data output path 50 comprises 16 bit lines, and it can be seen that each of the sense amplifiers and latch circuits is associated with a different one of those bit lines. Subsequent to bit line precharging, transmission requests asserted by various source circuits are evaluated, but in this embodiment, the asserted transmission requests take a logic one value.

  As shown in FIG. 2, the priority storage circuit of each crossbar cell comprises a series of priority storage elements 130, one for each bit line except the bit line to which the sense amplifier and latch of that crossbar cell are connected. . Specifically, as shown in FIG. 2, each crossbar cell includes a series of transistors 135 associated with each of the bit lines except the bit line connected to the sense amplifier and latch circuit of the crossbar cell. Then, if there is an asserted transmission request, the priority storage element 130 uses it to provide a value to the gates of those transistors 135 depending on the value programmed in those priority storage elements. Is done.

  As shown in FIG. 2, all of the dark shaded priority storage elements 130 are currently programmed to a logic 1 value, and all of the light shaded priority storage elements 130 are currently logical 0. Is programmed to the value of Thus, if there is an asserted transmission request, the transistor attached to the priority storage element that stores the logic 1 value discharges the bit line while the priority storage element that stores the logic 0 value. The attached transistor does not discharge. In the example shown in FIG. 2, if the source 15 has the highest priority for the current application of the adaptive priority scheme, and this source 15 asserted a transmission request, this is related to All discharge of the bit line except the bit line of the sense amplifier and latch circuit 115 is caused. Source 14 has the next highest priority, source 13 has the next highest priority, etc. Source 0 has the lowest priority. Specifically, as can be seen, if a transmission request from source 0 (ie, request 0) is asserted, this does not discharge any bit lines.

  Following the selective discharge operation, any sense amplifier and latch circuit that then receives the asserted transmission request determines whether the associated crossbar cell will couple its input to its output in the transmission mode of operation. In order to store the routing value to be determined, its associated bit line is sampled. Specifically, only if the routing value has a first value (in one embodiment this is a logic one value), the associated crossbar cell outputs its input data during its transmission mode of operation. It will be appreciated that only one crossbar cell has a sense amplifier and latch circuit set to a logic one value at the end of the arbitration mode of operation, according to the scheme described above.

  Thus, as an example, if both source 1 and source 2 issue an asserted transmission request, it can be seen that both asserted request 1 and asserted request 2 discharge the first bit line. . As a result, even if source 0 asserts the request, the associated sense amplifier and latch circuit 100 latches the logic zero value at the end of the arbitration mode of operation, so the request is not granted. Furthermore, the asserted request 2 discharges the second bit line, so that at the end of the arbitration mode of operation, the sense amplifier and latch circuit 105 associated with source 1 latches a logic zero value. Therefore, even if the source 1 asserts the transmission request, if the source 2 has also issued the asserted transmission request, the transmission request is not accepted. Assuming that no other source circuit has asserted a transmission request in that cycle, then the sense amplifier and latch circuit 110 associated with source circuit 2 latches the logic 1 value at the end of the arbitration mode of operation. It will be appreciated that the transmission request from source 2 is accepted accordingly.

  From the above description, it can be seen that the received asserted transmission request causes the suppression of other asserted transmission requests from lower priority sources. The sense amplifier and latch circuit for any asserted transmission request then samples their associated bit lines to determine whether the request has been granted. This technique allows collisions to be detected and resolved in a single cycle. Furthermore, it can be seen that the same bit lines used for detecting and resolving conflicts during the arbitration mode of operation are used for subsequent transfer modes of operation and then for the transfer of data.

  An asserted transmission request can be input into the crossbar circuit in a number of different ways, but in one embodiment, a word line in the data input path is used to input the asserted transmission request. The Thus, when considering an embodiment in which each data input path has 16 word lines, any particular source circuit can route any of up to 16 data output paths through those word lines. It can be seen that in the mode of operation, it is possible to specify whether each individual word line associated with a different data output path wants to assert a transmission request.

  Although not explicitly shown in FIG. 2, in addition to priority storage element 130, to ensure that transistor 135 is turned off during the precharge mode of operation performed by precharge module 55, There are typically also several associated isolation circuits for each transistor 135.

  In one embodiment, each crossbar cell is provided with a release circuit to provide a mechanism for releasing the channel when it is no longer needed. Specifically, once source circuit 30 is granted access to a channel, only that source circuit can release the channel for subsequent assignment to a different source circuit, In response to an asserted release request from a source circuit that is currently granted access to the channel, it is performed by the release circuit. Even if a channel is granted to a particular source circuit, no other source circuit can gain access to that channel, and no assertions are made on that channel issued by other source circuits. The channel is assigned to the source circuit, while the transmitted request does not work.

  FIG. 3 illustrates a release circuit 140 that is added according to one embodiment. In a manner similar to the priority storage element, the release circuit 140 is used to drive the associated transistor 145, in which case the transistor is driven by the same crossbar cell sense amplifier and latch circuit to determine the routing value. Connected to the bit line to be sampled. Thus, when the source circuit wishes to release the channel, it sends a release request to release circuit 140, causing the value of logic 1 to be output to transistor 145 to discharge the associated bit line. The associated sense amplifiers and latches then sample the bit line, thereby storing a logic zero value there, thus releasing the channel. Again, several associated isolation circuits are provided for each transistor 145 to ensure that transistor 145 is turned off during the precharge operation performed by precharge module 55.

  In one embodiment, a release request is issued in an arbitration mode of operation and a source circuit in an arbitration mode of operation to identify whether a word line of the associated data input path is carrying a release or transmission request. A control signal is issued. Thus, this time the word line of the data input path can again be reused to carry the asserted release request to the associated release circuit 140, thereby enabling the Provides a particularly efficient mechanism for releasing accepted channels.

  As described above, the priority storage circuit of each crossbar cell stores priority data referenced by the arbitration circuit when the adaptive priority scheme is implemented, and the priority storage circuit is adapted to adaptive priority by the arbitration circuit. During each application of the ranking scheme, the bit lines are reused and configured to self-update the priority data stored therein. The manner in which this is achieved for a particular embodiment where the adaptive priority scheme is an LRG priority scheme will be further discussed with reference to FIGS. 4A-4H.

  FIG. 4A shows an example with five source circuits that can assert channel requests. In this embodiment, the priority storage circuit of each crossbar cell has four priority storage elements whose stored values collectively indicate the priority of the associated source circuit for the channel to which the crossbar cell is connected. Consists of. As discussed previously with reference to FIG. 2, the arbitration mechanism is implemented in two stages. In the positive phase of the clock, the bit lines are precharged to a logic one level, and subsequently, in the negative phase of the clock, the bit lines are sourced based on the priority stored at the intersection. Selectively discharged at the intersection asserted by the circuit.

  In FIG. 4A, the priority storage circuit of each crossbar cell receives a reset operation so that a predetermined initial priority is assigned to each source circuit for each channel. For the channel embodiment shown in FIG. 4A, priorities are assigned in ascending order, with source 4 having the highest priority, while source 0 has the lowest priority.

  Then, as shown in FIG. 4B, one or more of the source circuits asserts a transmission request. In the example of FIG. 4B, it is assumed that sources 1 and 3 assert a transmission request for the indicated channel. As shown in FIG. 4C, when the bit lines are precharged, the asserted transmission request causes some of the bit lines to be discharged depending on the stored priority data. Specifically, the logic 1 values stored in priority storage elements 160, 162, and 164 associated with source 3 cause bit lines 170, 172, and 174 to discharge, respectively. The logic one value of priority storage element 166 associated with source 1 also discharges bit line 170.

  As shown in FIG. 4D, following the selective discharge process, the sense amplifier and latch (SAEL) circuits 180, 182 associated with source circuit 1 and source circuit 3, respectively, then evaluate their bit lines. . SAEL circuit 182 senses a logic 1 value because bit line 176 was not discharged, indicating that the asserted transmission request of source circuit 3 was successful. On the other hand, the SAEL circuit 180 senses a logic 0 value because the bit line 172 has been discharged, indicating that the asserted transmission request of the source circuit 1 was not successful. The source circuit 3 can now transmit data on the channel.

  As shown in FIG. 4E, the source circuit 3 asserts a release request when it finishes transmitting data. As shown in FIG. 4F, the bit line is precharged, and then the bit line 176 is discharged by the release circuit 190 to which the release request asserted from the source circuit 3 is given. SAEL circuit 182 then senses a logic zero value, thereby releasing the channel.

  Thereafter, as shown in FIG. 4G, the priority stored in the priority storage circuit is updated, this update process comprising a column of priority storage elements 192 coupled to the discharged bit line 176, and It affects both the rows of priority storage elements 194 contained in the crossbar cell that receives the release request. Specifically, as shown in FIG. 4H, all priority storage elements in column 192 are written with a logic 1 value, while all priority storage elements in row 194 have a logic 0 value. A value is written. As a result, it can be seen that the source circuit 3 currently has the lowest priority. Since the priority of the source circuit 4 is higher than that of the source circuit 3, it remains in its original state. In addition, source circuits 0, 1, and 2 upgrade their priority. This priority update process because the new priority is used when evaluating the asserted transmission request the next time the arbitration process is applied by comparing the old priority and the new priority listed in FIG. 4H. Can be seen to achieve the implementation of LRG.

  Although five inputs have been considered for illustrative purposes only, it will be understood that the technique can be used for any number of inputs.

  FIG. 5 (FIGS. 5A and B) shows the main components provided within each crossbar cell, specifically the crossbar cell provided in column 0 for rows 0, 1, and 2. FIG. Thus, crossbar cell 200 is provided at the intersection between row 0 and column 0, crossbar cell 230 is provided at the intersection between row 1 and column 0, and crossbar cell 260 is provided at row 2 and column 0. Provided at the intersection between and.

  Considering first the crossbar cell 200, it consists of a configuration storage circuit 205, a transmission circuit 210, a channel release circuit 215, an arbitration circuit 220, and a priority storage circuit 225. In the arbitration mode of operation, a transmission request is asserted on the data input path (also referred to as the input bus in FIG. 5), and if the source 0 wants to assert the column 0 transmission request accordingly, the input bus Do this by setting bit 0 of. As can be seen, the value of bit 0 is input to AND gate 207, and the other inputs are driven by request channel control signals. During the arbitration mode of operation, if any asserted transmission request is issued on the input bus, the source circuit asserts the request channel control signal. That is, if source 0 has issued an asserted transmission request for channel 0, both inputs to AND gate 207 will have a logic 1 value, and accordingly, both arbitration circuit 220 and configuration memory circuit 205 will Activated (configuration memory circuit is activated via OR gate 208).

  As can be seen, the configuration storage circuit 205 is connected to bit 0 of the data output path for channel 0 (also referred to as the output bus in FIG. 5) and is stored there at the end of the arbitration mode of operation. To determine the value, the value of bit 0 of the output bus is sampled. However, prior to that point, arbitration circuit 220 may arbitrate any other crossbar cell arbitration circuit 250 associated with that column that received the asserted transmission request to selectively discharge the bit lines of the output bus. 280 and so on. Specifically, as can be seen in FIG. 5, the arbitration circuit 220 of the crossbar cell 200 is connected to all of the other bit lines of the output bus except for the bit line 0, and the priority level programmed in the priority level storage circuit 225. Depending on the data, these bit lines are selectively discharged.

  As described above, following the selective discharge operation of arbitration circuit 220, configuration memory circuit 205 then samples the value of its associated output bit line, specifically, that bit line is still precharged. If it is at the voltage level, the logic 1 routing value is stored in the configuration storage circuit 205 to indicate that source 0 is granted access to channel 0. Due to the nature of the adaptive priority scheme implemented by the crossbar cell arbitration circuit in a column, at the end of the arbitration mode of operation, only one crossbar cell for any particular column has its configuration memory circuit. Set to a logic 1 value, in response, only one source circuit may be granted access to a particular destination circuit at any one time.

  Following the arbitration mode of operation, the switching fabric enters a transmission mode of operation, during which each source circuit granted access to a particular channel provides its input data on the input bus. Thus, assuming that source 0 has been granted access to column 0, if the data is issued to transmission circuit 210 on the input bus and the value of logic 1 is stored in configuration storage circuit 205, then If so, connect its input to the output bus for channel 0.

  As described above, in the arbitration mode of operation, it is also possible to release channels if they have previously been granted to a particular source. Thus, by way of example, if source 0 has been previously granted access to channel 0 and accordingly configuration storage circuit 205 has a logic 1 routing value stored therein, in arbitration mode of operation, Source 0 can issue a release channel control signal to AND gate 217 along with a logic one value of bit 0 of the input bus to identify an asserted release request of zero. This causes the value of logic 1 to be input to the channel release circuit 215 and activates the configuration memory circuit via the OR gate 208. In response to this logic 1 value, the channel release circuit discharges bit 0 of the output bus, and then configuration memory circuit 205 resamples the output bus, thereby setting the logic 0 value to the configuration memory circuit. The data is stored in 205.

  The asserted release request also activates the priority storage circuit to self update the priority data stored therein. As discussed previously and shown in FIG. 5, a priority storage circuit is coupled to each bit line of the output bus other than the bit lines to which the same crossbar cell configuration storage circuit is coupled. In addition, as will be discussed in more detail later with reference to FIG. 10D, the priority storage circuit receives a load priority signal, which in one embodiment, updates its value during the self-update process. Used to identify at least some of the individual priority storage elements (in combination with the voltage of the bit line coupled to the priority storage circuit).

  In one embodiment, both the request channel control signal and the release channel control signal can be encoded into a 2-bit signal that is used by the associated source circuit to perform any assertion during the arbitration mode of operation. Determine whether it has issued an issued transmission request, has issued any asserted release channel request, or has not issued any asserted request.

  Crossbar cells 230 and 260 are configured in the same manner as crossbar cell 200, and therefore, elements 235, 237, 238, 240, 245, 247, 250, and 255 of crossbar cell 230 and elements of crossbar cell 260. 265, 267, 268, 270, 275, 277, 280, and 285 correspond to elements 205, 207, 208, 210, 215, 217, 220, and 225 of crossbar cell 200, respectively. However, as is apparent from FIG. 5, the manner in which these various elements are connected to the various word lines and bit lines is slightly different. Since each of the crossbar cells 200, 230, 260 is associated with column 0, the asserted transmission request and the asserted release request are always provided to bit 0 of the associated input bus, and therefore for this purpose. All three crossbar cells are connected to bit 0 (word line 0). However, considering the connection to the bit line, the configuration memory circuit 205 of the crossbar cell 200 is connected to bit 0 of the output bus, while the configuration memory circuit 235 of the crossbar cell 230 is connected to bit 1 and It can be seen that the configuration memory circuit 265 of the bar cell 260 is connected to bit 2. The channel release circuit of each crossbar cell is connected to the same bit line as the associated configuration memory circuit. On the other hand, the arbitration circuit and the priority storage circuit are connected to all of the bit lines except the bit line connected to the related configuration storage circuit. In the transmission mode of operation, if the routing value of the associated configuration storage circuit is set to a logic one value, the transmission circuit will connect the data on the input bus to the associated output bus, so that the transmission circuit will of course be a word. Connected to all of the lines and bit lines.

  FIG. 6 (FIGS. 6A and B) is a view similar to FIG. 5 but with cross-bar cells 200, 300, provided at the intersection between row 0 and column 0, column 1 and column 2, respectively. 330 is shown. The cross bar cell 200 is as described above with reference to FIG. 5, and the cross bar cells 300 and 330 are configured in the same manner. Thus, elements 305, 307, 308, 310, 315, 317, 320, and 325 of crossbar cell 300 and elements 335, 337, 338, 340, 345, 347, 350, and 355 of crossbar cell 330 are respectively Corresponding to elements 205, 207, 208, 210, 215, 217, 220 and 225 of the crossbar cell 200. In this embodiment, since all of the crossbar cells are associated with the same row, the crossbar cells are connected to the bit lines of their respective output buses in the same manner. However, when considering the input bus, an asserted transmission or release request for channel 0 is input to word line 0, while an asserted transmission or release request for channel 1 is input to word line 1. The asserted transmission or release request for channel 2 is input to word line 2. Therefore, the configuration memory circuit, channel release circuit, and arbitration circuit of each crossbar cell are driven by different input word lines accordingly.

  FIG. 7 shows in more detail how the transmission circuit and the arbitration circuit are connected to each bit line. Specifically, element 420 represents a portion of the transmission circuit associated with the individual bit line, and element 440 represents a portion of the arbitration circuit associated with the individual bit line.

  Considering a 16-bit wide channel, the arbitration circuit is associated with all of the bit lines except the bit line to which the crossbar cell configuration memory circuit 410 is connected, so 15 of the 16 bit lines are shown. 7 is connected. As described above with reference to FIGS. 5 and 6, when provided to a crossbar cell, the configuration storage circuit 410 is set to that crossbar cell if there is an asserted transmission request or an asserted release request. The memory configuration signal is received, and in response to the set memory configuration signal, a value on a specific bit line to be connected is sampled as the configuration. This happens during the arbitration mode of operation, and at the end of the arbitration mode of operation, this results in storing the logic 1 routing value in the configuration storage circuit 410, when the crossbar circuit subsequently enters the data transfer mode of operation, It can be seen that the transistor 422 of the transmission circuit 420 is turned on. Thus, if the data input on the corresponding word line is also a logic one value, this turns on transistor 424 and discharges bit line 426 accordingly, which bit line is logic driven by precharge circuit 400. Precharged to a level of 1. Any discharge of bit line 426 is sensed by sense amplifier circuit 430.

  In the arbitration mode of operation, no transmission circuit is used, instead, arbitration circuit 440 is used to selectively discharge bit line 426 depending on the input from AND gate 455 received by transistor 442. . Specifically, when the priority storage element 450 stores a logic 1 value and receives an asserted transmission request on the corresponding word line, the logic 1 value is input to the transistor 442 and the bit line 426 is turned on. Discharge. At the end of the arbitration mode of operation, any configuration storage circuit connected to the bit line 426 of another crossbar cell that has received the asserted transmission request determines the value of the routing value applicable to that crossbar cell. Therefore, the value on the bit line is sampled.

  Each associated arbitration element 440 is provided with a separate priority storage element 450 whose value is updated when the release_channel signal is present, while the corresponding word line release input is also a logic one value. . As will be discussed later with reference to FIG. 10B, the load priority_b signal and voltage on bit line 426 are also used during the priority update process. Further, the priority storage element receives the reset signal, but when set, causes the priority storage element to write a predetermined value (1 or 0 depending on the form of the priority storage element).

  FIG. 8 illustrates a transmission circuit and associated release circuit according to one embodiment. Considering a 16-bit channel, one bit line is connected in each crossbar cell in this manner. The operation of the transmission circuit is not different from that discussed with reference to FIG. 7, and therefore will not be discussed in detail here. However, a release circuit 460 is connected to the bit line 462 instead of the arbitration circuit 440 of FIG. It should also be noted that the crossbar cell configuration memory circuit 410 is also connected to the bit line 462. AND gate 470 corresponds to the AND gate shown in FIGS. 5 and 6 as supplying a channel release circuit, so that the release channel control signal is asserted and the bit on the associated input word line is asserted. This indicates the presence of an asserted release request for a particular channel and results in turning on transistor 465 and discharging bit line 462, as can be seen from FIG. Thereafter, the configuration storage circuit 410 is caused to receive an asserted storage configuration signal that causes the value on the bit line 462 to be resampled, thereby storing a logic zero routing value there, thus releasing the channel. The

  Using the above technique, it is possible to implement a packet switching crossbar, as shown schematically in FIG. In a packet switching environment, a source first sends a request, then sends data upon receipt of the accepted signal, and the request and data are sent on the same input line. From the foregoing discussion of the embodiments of the present invention, by allowing asserted transmission requests to be subsequently input on the same word line used to carry data in a transmission mode of operation, It can be seen that the crossbar circuit of the embodiment of the invention is readily useful in such packet switching embodiments. The request channel and release channel control signals discussed above with reference to FIGS. 5 and 6 can be input via a two-bit request / release input line 500, asserted transmission request or asserted release. The request is entered on the associated data entry path 12. During the arbitration mode of operation, when a particular configuration storage circuit in the crossbar cell stores a logic one value, an acceptance signal is sent on line 505 to the source circuit to indicate that the associated source circuit has been accepted. Is returned. In a single request implementation where any particular source circuit can only request one output channel at any one time, only a single consent signal line 505 is required. However, in an alternative embodiment that supports multicasting (one source circuit can broadcast data on multiple channels at any point in time), then the source circuit can be In such an embodiment, a multi-bit grant signal line 505 may be provided to identify which channel the master has granted access to, in such an embodiment. it can.

  During the arbitration mode of operation, each of the crossbar cells also receives a channel free signal on line 510 that indicates whether the associated channel is free to be allocated to the requesting source; 10 and 11 will be discussed. As discussed in more detail later with reference to FIG. 10D, a load priority_b signal is provided on path 515, which is precharged by precharge module 55 and then in response to the asserted release request. Thus, it is discharged when the priority order data in the priority order storage element is updated.

  Thus, from the previous discussion of FIG. 9 and embodiments of the present invention, in this packet switching crossbar implementation, a precharge and conditional discharge scheme is used to transmit data through the crossbar circuit during the transmission mode of operation. It will be understood that During the aforementioned arbitration mode of operation, bit lines are reused for collision detection and resolution, and word lines are used to carry asserted transmission requests. The 2-bit request / release signal can be used to specify whether a transmission request or a release request is asserted during a particular arbitration mode of operation. Assuming that a transmission request has been asserted, then a grant signal is used to indicate to the source whether the request has succeeded in acquiring the requested channel.

  Existing word lines (input buses) and bit lines (output buses) are used to implement all of the functionality previously described, so that all of these functionalities are achieved with minimal routing overhead. Makes it possible to

  10A-10D show in more detail the circuitry provided in each crossbar cell 20 according to the first embodiment, where the source circuit only issues a single transmission request at a time. Also good. As is apparent from the previous discussion of FIGS. 7 and 8, each bit line in the output path is provided with a pair of transistors 710, 715, 720 to form a transmission circuit, one of these transistors. Receives the value on the corresponding word line at its input and the other transistor receives the routing value of the associated configuration storage element 700 at its input. During the precharge phase, the discharge signal is set to a logic zero value, causing the conditional discharge circuit 705 to separate these transistors 710, 715, 720 of each transmission circuit from the contents of the configuration storage circuit 700. However, when the discharge signal goes high, indicating that the precharge operation has ended and the sensing operation has begun, the configuration memory element 700 will now have the second transistors 710, 715, It can be seen that it provides the value used to drive 720 and causes a selective discharge of the associated bit line depending on the input data received at the first transistor. Conditional discharge circuit 705 also uses the WL_b signal, and FIG. 10B shows how the WL_b signal is generated and circuit 765 of FIG. 10B is provided once per crossbar cell.

  As shown on the right side of FIG. 10A, one of the bit lines is connected to an open channel circuit formed by AND gate 732 and associated transistor 712, while all other bit lines are each , To the arbitration circuit and associated priority storage elements 717, 742 and 722, 752. Each of the components 730, 740, and 750 function in combination with the component 760 to provide a conditional discharge circuit that isolates the associated transistors 712, 717, 722 during the precharge mode of operation. Specifically, during the precharge mode of operation, the discharge signal is low, causing the output from block 760 to be low regardless of the value of the WL signal, resulting in a low output for components 730, 740, and 750. , Thereby turning off transistors 712, 717, 722.

  However, when the discharge signal goes high, and thus the WL signal goes high, this causes a logic 1 value to be output from component 760. Thus, considering the arbitration circuit and associated priority storage elements 717, 742, and 722, 752, in the case of an asserted transmission request in a situation where the associated storage elements 742, 752 also store a logic 1 value, Release_b The signal goes high (because there is an asserted transmission request, not an asserted release request), so the output from AND gates 743, 753 goes high, causing the associated transistors 717, 722 to discharge, respectively. The priority scheme discussed above is implemented. However, if any of the priority storage elements stores a logic zero value, or if the WL signal is not asserted because there is no asserted transmission request, the corresponding transistors 717, 722 will not discharge. .

  Similarly, considering release circuits 712, 732, if there is an asserted release request, if both the release signal and the input 0 word line are set high, this will cause release transistor 712 to discharge and then In addition, the configuration memory element 700 resamples the bit line and resets the routing value to zero. While the release signal is set high, the release_b signal is low, and accordingly, the priority storage elements of other crossbar cells connected to the same bit line being released execute through the release transistor 712. Can not interfere with the release operation.

  FIG. 10B shows a circuit used to acknowledge an asserted request channel or release channel signal. It generates a WL signal that is set high only if a request / release channel signal is acknowledged. This WL signal is then used to activate the configuration storage element 700. The same WL (and WL_b) signal is also used to properly operate the conditional release circuit 705 and the arbitration circuit 760.

  FIG. 10C is provided in connection with the sense amplifier and latch circuit 775 of the configuration storage element 700 to update the stored value and to generate a compliance signal depending on the updated value. The circuit is shown. Specifically, if the sense enable (SE) signal is set and the WL signal is set, this causes the AND gate 770 to output the set QSE (acknowledged SE) signal. If the QSE signal is set, this causes the sense amplifier and latch circuit 775 to sample the current value on the corresponding bit line, which in this embodiment is connected to bit line 0.

  The acceptance signal is generated from the current contents of the sense amplifier and latch circuit 775. Specifically, the NAND gate 780 outputs a signal routed to the separation circuit 785 based on the current content and the WL signal. Isolation circuit 785 ensures that only one crossbar cell in a particular row drives the acceptance signal. In particular, only the crossbar cell associated with the column that the source circuit is currently requesting can generate an acceptance signal. Thus, in this embodiment, if the transmission requirement is set high and the input on word line 0 is set high, this causes the lower transistor in isolation circuit 785 to provide a logic 1 value, Causes the higher transistor to provide a logic zero value, thereby turning on the inverter and propagating the consent signal (if the sense amplifier and latch circuit 775 stores a logic one value, the consent signal is asserted. ) Otherwise, however, a logic 0 value is provided to the lower transistor and a logic 1 value is provided to the higher transistor, thereby turning off the inverter and not propagating any consent signal.

  FIG. 10D illustrates the structure of each priority storage element 742, 752 according to one embodiment. If there is an asserted release request, AND gate 790 outputs a logic 1 value when both the release signal and the input 0 word line are set high. When the discharge signal is also at a logic 1 level, this causes the AND gate 791 to output a logic 1 value and to discharge the load priority_b signal through transistor 792.

  During normal operation, the reset signal has a logic zero value, and therefore the reset_b signal has a logic one level. Thus, for all priority storage elements in the crossbar cell that receive an asserted release request (eg, the priority storage element in row 194 shown in FIG. 4G previously discussed), AND gate 795 When the discharge signal is high, three logic 1 inputs are received, with the intermediate logic 1 input coming from the output of AND gate 790 via OR gate 794. As a result, the transistor 796 is turned on, and the logic 0 value is stored in the priority storage element 798 based on the logic 1 value supplied from the AND gate 790.

  Similarly, for all priority storage elements (eg, priority storage elements in column 192 shown in FIG. 4G discussed above) coupled to a bit line that is discharged by an asserted release request, an AND gate 795 receives three logic 1 inputs when the discharge signal is high, with the intermediate logic 1 input coming from the output of NAND gate 793. Specifically, since the load priority_b signal is at a logic 0 level at this point, this ensures that the NAND gate 793 produces only a logic 1 output when the associated bit line is discharged. To. As a result, the transistor 796 is turned on, and a logic 1 value is stored in the priority storage element 798 based on the logic 0 value supplied from the AND gate 790 (the priority storage element receives the asserted release request). This output will be a logic zero value for the priority storage element connected to the discharged bit line) because it will be in a crossbar cell that is not connected to the source circuit that issues.

  For all other priority storage elements not in row 194 or column 192, the intermediate input of AND gate 795 is a logic zero value, and any updates to the priority value are made accordingly. Absent.

  As shown in FIG. 10D, each priority storage element can take either the form shown in block 798 or the form shown in block 799. During normal use, when the reset signal is low and the reset_b signal is high, both the NAND gate of form 798 and the NOR gate of form 799 operate as inverters, so both forms operate in the same manner. However, during a reset operation, when the reset signal transitions to a logic 1 level, the reset_b signal transitions to a logic 0 level, so that the priority storage element of form 798 stores a value of logic 0, The 799 priority storage element stores a logic 1 value. Thus, the priority storage element can be set to its original configuration in response to a reset signal, and then each time a channel is released, its priority is implemented to implement the LRG priority scheme for that channel. The priority data for the channel is updated. It will be appreciated that the LRG scheme implemented as described above operates independently for each channel in the crossbar circuit.

  FIGS. 11A-11D illustrate circuitry provided in each crossbar cell according to an alternative embodiment of the present invention, where each source can issue multiple requests simultaneously. This allows for a more efficient implementation for performing multicasting within the crossbar. Specifically, in the embodiment of FIGS. 10A-10D, the source circuit can only request one channel at a time, so if multicasting is required, multiple sources are required to acquire multiple channels. Request an arbitration cycle. However, in the embodiment of FIGS. 11A-11D, the source circuit can issue requests for multiple channels at the same time, and potentially obtain multiple channels in one arbitration cycle, thereby Making it possible to achieve multicasting more efficiently.

  FIGS. 11A, 11B, and 11D are identical to FIGS. 10A, 10B, and 10D and are therefore not discussed in detail here. However, as shown in FIG. 11C, since there is no need for an isolation circuit, the structure of the configuration memory circuit is considerably simplified. Instead, a separate consent line is provided in association with each column, so that the current content of the sense amplifier and latch circuit 775 directly generates an acceptance signal when a set WL signal is present. Can be used for Specifically, if the WL signal is set, the source circuit issues an asserted transmission request and the current content of the sense amplifier and latch circuit 775 is a logic 1 value indicating that the transmission request was successful. And then a logic 1 acceptance signal is issued and returned to the source circuit.

  FIG. 12 illustrates an arrangement of configuration memory circuits (ie, sense amplifiers and latch circuits) provided within each crossbar cell, according to one embodiment. The QSE signal generated by AND gate 770 of FIGS. 10C and 11C passes through inverter 850 to generate the QSE_b signal. Thus, when the QSE signal goes high, the PMOS transistor 800 is opened to initiate the sensing operation of the sense amplifier (the sense amplifier is formed by transistors 805, 810, 815, 820). At the start of the sensing operation, transistors 815 and 820 are turned off. When the input line routed to transistor 805 begins to discharge, this turns on transistor 805 and pulls intermediate node I to Vdd. As a result, this turns on transistor 810, creating a positive feedback loop in the sense amplifier after a short period of time, at which point the sense amplifier transitions to ground to generate its output. No longer depends on the signal.

  A series of transistors 825, 830, 835 serve as a transfer mechanism between the sense amplifier and the latch comprised of components 840 and 845. Specifically, during the sensing phase of operation, transistor 830 is turned on, allowing the contents of the latch to be determined by the value of the sense amplifier's intermediate node I. Specifically, if the input to the sense amplifier transitions to a logic zero value, this causes the intermediate node I to transition to Vdd in order to store the logic zero value in the latch in the latch. Will turn on transistor 835. Conversely, if the input line does not discharge, the voltage at the intermediate node remains at a logic zero level, thereby turning on transistor 825 and storing a logic one value in the latch.

  As soon as the QSE signal goes low, transistor 830 turns off, thereby isolating the latch from the sense amplifier output, so it is understood that the latch updates its input only during periods when the QSE signal is high. Will.

  13A-13C show a pulse generator circuit used in one embodiment to generate both the SE signal and the discharge signal. FIG. 13A shows how a discharge signal is generated from the SE signal after some delay is introduced by component 860. In practice, the circuit of FIG. 13A serves as an AND gate and performs an AND between the SE signal and a delayed version of the SE signal.

  FIG. 13B shows a ring oscillator design used to create the SE signal. When the oscillation input signal is high, this activates the ring oscillator to generate the clock signal, and the SE signal is derived from the clock signal through several delay circuits 870.

  As shown in FIG. 13C, the period during which the SE signal is low, that is, the d1 period is determined by the component 870, and the period during which the discharge is high, that is, the d2 period, is determined by the delay circuit 860 in FIG.

  The voltages Vb_SE and Vb_Discharge are used to control the delay periods d1 and d2, and specifically, when these voltages are reduced, the delay period is lengthened accordingly.

  At the positive edge of the clock, data is raised on the word line. At this point, since the “discharge” signal is low, the bit line is separated from the word line. During the “d1” period, data remains on the word line and the bit line is fully precharged. “D2” is a period during which the bit line is conditionally discharged. At the same time, the SE signal goes high and the sense amplifier starts sampling the bit line. The bit line is discharged just enough for the sense amplifier to detect. This is done to save power. Thus, after time “d2”, the “discharge” signal goes low while the SE signal remains high.

  FIG. 14 schematically illustrates how the channel_free signal described in FIGS. 10B and 11B is generated according to one embodiment. Specifically, as shown, the outputs from the various configuration memory circuits 900, 905, 910 in the crossbar cell connected to a particular output channel are logically ORed together by OR gates 902, 907, 912. And then the result is inverted by inverter 915. Therefore, if any of the configuration storage circuits stores a logic 1 routing value, the channel_free signal will be a logic 0 value and only if all of the configuration storage circuits store a logic 0 routing value. It can be seen that the channel_free signal is set to 1. Thus, at the start of the arbitration mode of operation, if one of the configuration storage circuits is already set to a logic 1 value, indicating that the source circuit already has ownership of the channel, then at that time No asserted transmission request is accepted, and only when the channel is released allows another source to make the request and the channel is granted.

  In the embodiment described above, the output data lines are precharged high, so a static high input will cause the data lines to discharge every clock cycle. FIGS. 15A-15E illustrate an encoding scheme that can be used to mitigate this, thereby reducing power consumption. Specifically, FIG. 15A shows an encoder circuit that may be placed between the source and the crossbar input data path, and FIG. 15B shows between the output of the sense amplifier 65 and the destination circuit. Fig. 4 shows an associated decoder circuit that may be arranged. Considering the encoder circuit of FIG. 15A first, each item of new data is latched in flip-flop 600 and the old data is propagated to flip-flop 610 via NAND gate 605. The comparator 615 then compares the new data with the old data and causes a logic 0 value to be output to the inverter 620 whenever there is a difference, so that a logic 1 value is output by the encoder circuit. Thus, from the provided input data, the encoder separates by a logic 1 value whenever the input data changes from a logic 0 value to a logic 1 value or from a logic 1 value to a logic 0 value. To generate a logic 0 value. From the foregoing discussion of the crossbar cell, it can be appreciated that the data output line is only discharged when such a logic 1 value appears, thereby significantly reducing the power consumption associated with precharge operation. I will.

  When the first data item is input, no previous data is compared to it, and the sync signal is used to set the initial state in flip-flop 610 accordingly. In addition, synchronization pulses can be used to reconfigure the encoder hardware (without consuming clock cycles) each time the crossbar is switched to a new configuration.

  The corresponding decoder circuit is shown in FIG. 15B. The structure of components 630 and 635 is schematically illustrated in FIG. 15C by component 660. As shown, such a component actually consists of a series of transistors 665, 670, 675, 680 connected in series.

  The sync_d signal is the same as the sync signal, but is delayed by one clock cycle. The sync_d_b signal is an inverse sync_d signal. The relationship between these three signals is shown in FIG. 15E. The sync signal is an active low signal, therefore, under normal operation (when the circuit is not switched to a new configuration), sync and sync_d are at a high logic 1 level, while the sync_d_b signal is at a low logic level. Note that it is at level 0.

  As can be seen from FIG. 15B, the decoder receives outputs from the sense amplifier, the clock signal, and the sync_d_b signal and provides the internal clock signal to flip-flop 640 via a series of NAND gates 645, 650, 655. The output from flip-flop 640 drives the output to the destination circuit and recreates the original input data from the encoded output received via the sense amplifier.

  In normal operation, since the sync signal is at a logic 1 level and the sync_d_b signal is at a logic 0 level, component 635 is activated while component 630 is deactivated. Three NAND gates 645, 650, 655 provide a pulse to flip-flop 640 when the sense amplifier detects a transition and transmits a high signal. When a switch to a new configuration occurs, the sync and sync_d signals go low while the sync_d_b signal goes high. Thus, at that time, component 630 is activated while component 635 is deactivated. As a result, instead of toggling the previous data through inverter 635, flip-flop 640 takes the data from the sense amplifier (after component 630 inverts it).

  FIG. 15D shows the input data to the encoder circuit, the resulting encoded data output from the encoder circuit, the indication of the corresponding bit line that is discharged each time the encoded data is high, and Fig. 4 illustrates output data generated by a decoder circuit based on information received from a sense amplifier. It can be seen that the output data faithfully reproduces the input data passed to the encoder.

  In the embodiment described above, the size of the crossbar circuit corresponds to the sizes of the input bus and the output bus. Thus, a 16 × 16 crossbar circuit has been discussed, considering an input bus providing 16 word lines and an output bus providing 16 bit lines. However, the technique can also be adapted to operate with a crossbar circuit having an array of crossbar cells larger than the width of the input and output buses (referred to herein as a narrow channel design).

  Considering first a narrow channel design, FIG. 16 shows one embodiment for implementing such a narrow channel design. In this particular embodiment, a 64 × 64 array of crossbar cells 20 is provided in the crossbar, where again the precharge module 55 is used to precharge the bit lines passing through the crossbar. Assume that However, the data input path and data output path are only 16 bits wide, so it is impossible to perform the aforementioned arbitration process in a single cycle. Instead, in such an embodiment, the crossbar can be divided into several sections, in this example the crossbar is divided into four sections 1010, 1020, 1030, and the counter 1040 is Used to identify which section is currently active. Thus, the counter can be incremented every arbitration cycle to select which section to function during the arbitration in that arbitration cycle. Obviously, because each section still has 64 crossbar cells in each row, the data input path 1000 itself does not allow individual data output paths to be identified by asserted transmission requests. Thus, in one embodiment, a 2-bit additional signal 1002 is provided when asserting a transmission request to identify which data output path is requested by the associated source circuit.

  Thus, when the counter has a value of 00, only asserted transmission requests from sources 0-15 are considered and each data output path has a source 0-15 requesting access to that data output path. The highest priority source is granted access to transfer data in the next transmission cycle. After such an arbitration and transmission sequence, the counter is then incremented to 01 and only the asserted transmission requests from sources 16-31 are considered in the next arbitration cycle. This process is repeated in turn for each section. As a result, it will be appreciated that for the dimensions of the embodiment of FIG. 16, the arbitration latency for any given asserted transmission request varies from one to four cycles. For example, in an arbitration cycle where the count is 00, if source 0 asserts a transmission request, that request is arbitrated immediately in that cycle, and if it is the highest priority request in section 1, The request is accepted. However, if source 0 asserts a transmission request when the count is 01, when the counter returns to 00 (correspondingly, section 1 1010 is arbitrated), until the next fourth arbitration cycle, the request It ’s not even a candidate for arbitration.

  The advantage of such an approach is that it provides a good solution in situations where wiring and logic overhead is minimal and therefore the solution can tolerate variations in arbitration latency. is there. However, it should be noted that the worst-case arbitration latency increases as the number of sections increases.

  FIGS. 17A and 17B show an alternative embodiment in which the crossbar is again divided into sections, in which case arbitration is performed in two steps hierarchically. In the first step, arbitration is performed between sections, and then in a second step, arbitration is performed between all asserted transmission requests in a given section. The same bit line group is used for both arbitration steps. In this embodiment, the crossbar cells are represented by the number 20 ', and each of the crossbar cells is basically configured as described above, but here each crossbar cell has two sense amplifier enable latches. (SAEL), the first SAEL is used in the first arbitration cycle, and the second SAEL is used in the second arbitration cycle.

  Thus, in arbitration cycle 1, each of sections 1050, 1060, 1070, 1080 is considered, but the individual crossbar cells 20 ′ for a particular data output path within a given section can be Considered virtually in combination, as schematically illustrated by 1082. Specifically, considering the example of the 64 × 64 crossbar of FIG. 17A with a 16-bit channel, each of the four separate sections 1050, 1060, 1070, 1080 has a relative priority. Have. If section 1 has the highest priority, any asserted transmission request from source 0-15 causes the bit lines for sections 2, 3, and 4 (ie, sections 1060, 1070, 1080) to be discharged. As a result, in section 1, the first set of SAELs latches logic 1 values, and in the other sections, the first set of SAELs latch logic 0 values.

  In the next arbitration cycle, as shown in FIG. 17B, only the requests in section 0 (assuming the sequence of events described above) use the bit line for arbitration. Currently, the process performed in this section 1050 is as described above, ie the bit lines are precharged and then selectively discharged according to the priority information stored in each crossbar cell. . As described above in FIG. 16, an additional 2-bit signal 1002 is used to recognize which output path is required on the word line 1000 by input of a 16-bit value. For multiple requests for any particular data output line, then the request with the highest priority among the sources 0-15 is granted access, and the second set of SAELs is the bit line in a standard manner. Sense. In order to determine whether consent has been granted for a particular source, then both SAELs in the crossbar cell 20 'need to be considered, specifically if they both store a logic one value. In response, an acceptance signal is generated and returned to the source.

  Such an approach has a fixed two-cycle arbitration latency at the expense of some additional logic, but does not have any additional interconnect structure. Having 16 bit lines in a channel can potentially arbitrate between 16 sections, each section containing 16 requests. Thus, the arbitration latency can hold up to 256 × 256 crossbars in two cycles for one crossbar.

  In one embodiment of the approach of FIG. 17A / B, two sets of priority storage elements can be provided for each crossbar cell, one set used in conjunction with the first arbitration cycle (first One set is used in conjunction with the second arbitration cycle (the second set SAEL is used).

  FIG. 18 shows that a sequence of word line drivers 1200, 1205, 1210 is used to propagate data input values along the data input paths to the various crossbar cells 20 connected to those data input paths. Fig. 3 shows an embodiment of a partially activated network. Without such a partially activated network, considerable power can be consumed in propagating data along the entire data input path in situations where it is not needed.

  However, based on signals derived from routing values stored in each of the remaining crossbar cells along the data input path, each of the word line drivers is conditionally activated, presented in FIG. Power saving can be achieved by using the network approach activated in Specifically, as shown, the routing value stored in a particular crossbar cell is logically ORed to the right in a particular row by the routing value held in all other crossbar cells. Depending on the value of the signal at the point where the word line driver arrives in the chain, each word line driver 1200, 1205, 1210 is activated.

  Therefore, in the embodiment described above, at least one of the first 15 crossbar cells in row 0 has its routing value set to 1, and the corresponding source is one of the output paths 0-15. Access to one of the other crossbar cells, but none of the other crossbar cells to the right of the row has a routing value set to 1, in which case the word line drivers 1205 and 1210 are 2 also shows that the word line driver 1200 receives a logic 1 activation signal while receiving a logic 0 activation signal. As shown in the lower half circuit of FIG. 18, each of the word line drivers (for the purposes of illustration, the word line driver 1200 is considered, but all of the word line drivers are similarly configured) The activation signal is used to selectively activate the word line driver. Specifically, the main inverter 1260 in the word line driver is activated only when the activation signal is high, which turns on both transistors 1250 and 1255. When the activation signal is low, these transistors are not turned on and the inverter 1260 is not activated. When activated, inverters 1260 and 1265 operate together to amplify input data for further propagation along the data input path.

  Thus, in the embodiment discussed with reference to FIG. 18, no data is driven on the word line beyond the channel after which the remaining crossbar cell switches are turned off. This can provide a useful power saving scheme for large crossbars, and can result in particularly good power savings in implementations that rarely do multicasting.

  From the foregoing description of the embodiments, such embodiments provide a novel crossbar implementation scheme that can be used to design very large crossbars as may be required for multi-core applications. You will understand. The crossbar circuit of embodiments of the present invention reuses data output lines during the arbitration mode of operation to detect and resolve conflicts and program configuration memory elements in each crossbar cell accordingly. The implementation of the proposed embodiment of the present invention uses the smallest area where a crossbar design is possible. In contrast to typical prior art implementations where both the number of intersections as well as the number of logic incorporated into each intersection is increased, according to embodiments of the present invention, only the number of intersections is increased.

  For embodiments where the size of the array of crossbar cells does not exceed the width of the input and output channels, it is possible to perform the arbitration in a single cycle, thereby minimizing the delay overhead when performing the arbitration Can be suppressed. In addition, embodiments provide a priority storage circuit that reuses a bit line by the arbitration circuit to self-update the priority data stored on the bit line during each application of the priority scheme. Thereby providing a highly efficient, fast and scalable mechanism for implementing an adaptive priority scheme such as the LRG priority scheme.

  Furthermore, integrating the arbiter with the crossbar eliminates communication overhead between the two.

  In addition, when the crossbar cell structure of the above-described embodiment is adopted, the size of the transmission circuit, the size of the drive circuit, the size of the crossbar circuit used to provide input data on each input data path When increases, there is no need to increase the size. In addition, no additional hardware or sizing is required to support multicasting where a single input data value is broadcast to multiple output paths.

  Furthermore, routing is much more straightforward than typical prior art approaches because the standard structure is employed in the above-described embodiments.

  In an embodiment of the present invention, the input is not as a packet with the same bits from different buses, for example as may be required by a typical prior art crossbar employing multiplexing techniques. As supplied in the crossbar. This facilitates the use of the crossbar circuit of the embodiment of the present invention as a wide bus interconnection.

  Due to the crossbar circuit design of embodiments of the present invention, the delay through the crossbar increases linearly with size. This allows the crossbar circuit of such an embodiment to be easily used for very large crossbars, such as 128 × 128 or 256 × 256 input / output crossbars.

  As mentioned above, this design is very standard and the delay across all channels is uniform. Furthermore, the input can be supplied from any horizontal end and the output can be used at any vertical end. This facilitates design floorplanning by reducing routing congestion.

  Due to the standard bit cell-like architecture of the crossbar circuit of embodiments of the present invention, the design and layout of the crossbar circuit can be easily integrated into an existing CAD (Computer Aided Design) flow process.

  Compared to prior art techniques, the crossbar circuit of the embodiments of the present invention employs a high speed sensing technique with smaller interconnect size, so it consumes less power while operating more quickly.

  Although a particular embodiment of the present invention has been described herein, the present invention is not limited thereto and it will be apparent that numerous changes and additions may be made within the scope of the invention. I will. For example, various combinations of the features of the following dependent claims with the features of the independent claims can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 10 Input data 12 Data input path 20 Crossbar cell 30 Source circuit 40 Destination circuit 50 Data output path 55 Precharge module 65 Sense amplifier circuit 70 Output data

Claims (31)

A plurality of source circuits and a plurality of destination circuits are interconnected, so that data input from any of the plurality of source circuits to a crossbar circuit is output to any of the plurality of destination circuits A crossbar circuit that can
A plurality of data input paths passing through the crossbar circuit, each data input path being connectable to one of the plurality of source circuits and providing a plurality of word lines; Data entry path,
A plurality of data output paths passing through the crossbar circuit traversing the plurality of data input paths, each data output path being connectable to one of the plurality of destination circuits; A plurality of data output paths providing a plurality of bit lines;
A crossbar cell associated with each intersection between one of the data input paths and one of the data output paths, wherein each crossbar cell
To store a routing value in dependence on at least one voltage of the plurality of bit lines can be programmed with arbitration operation mode, a configuration storage circuit, said routing value, the data input path A first value is programmed to indicate that data input to the associated intersection along the word line is output on the bit line of the data output path at the associated intersection, and the routing The value indicates that a data input to the associated intersection along the word line of the data input path is not output on the bit line of the data output path at the associated intersection. A configuration memory circuit, programmed as follows:
Detecting, in a transmission mode of operation, the data input along the word line of the data input path and outputting an indication of the data on the bit line of the data output path at the associated intersection; A transmission circuit responsive to the routing value having a first value;
An arbitration circuit that operates in the arbitration mode of operation depending on a transmission request received by the crossbar cell from the source circuit connected to the data input path of the associated intersection, the source circuit comprising: When the transmission request is asserted at the associated intersection to indicate that it is desired to route data from the data input path to the data output path, the arbitration circuit may apply an adaptive priority scheme. Arranged to operate in combination with the arbitration circuit of another crossbar cell associated with the same data output path to selectively modify the voltages of the plurality of bit lines, and thus the same data output path There are multiple asserted transmission requests The configuration memory circuit of the only crossbar cell associated with the same data output path has its routing value programmed to the first value, thereby according to the adaptive priority scheme An arbitration circuit for resolving conflicts between asserted transmission requests of
Configured to store priority data identifying which of the plurality of bit lines should have their voltages modified by the associated arbitration circuit to apply the adaptive priority scheme A priority storage circuit,
During each application of the adaptive priority scheme by the arbitration circuit, the priority data stored therein is self-updated depending on the voltage of at least one of the plurality of bit lines. A priority storage circuit,
A cross bar cell comprising:
A crossbar circuit comprising:   The crossbar circuit of claim 1, wherein the adaptive priority scheme is a longest time elapsed after acceptance (LRG) priority scheme. Each data output path provides n bit lines,
Each configuration memory circuit is associated with one of the n bit lines through which the routing value is programmed into the configuration memory circuit, and thus the highest n associated with the same data output path. For a number of crossbar cells, the configuration memory circuit of those crossbar cells has a different associated bit line of the n bit lines;
Within each crossbar cell, the arbitration circuit and the priority storage circuit are associated with n−1 bit lines except the one bit line associated with the configuration storage circuit of the crossbar cell, and the adaptive type To apply a priority scheme, the priority storage circuit identifies which of those n-1 bit lines should have their voltage modified by the arbitration circuit. The crossbar circuit according to 1.   In the arbitration mode of operation, the arbitration circuit of any crossbar cell associated with the same data output path that receives the asserted transmission request is applied on the n bit lines to apply the adaptive priority scheme. After selectively modifying the voltage, each configuration memory circuit of the crossbar cell that receives the asserted transmission request samples the voltage on its associated bit line to program the routing value. The crossbar circuit according to claim 3 configured. Each crossbar cell
A release circuit coupled to the one bit line associated with the configuration memory circuit of the crossbar cell, and upon receiving an asserted release request, the release circuit receives the second value as the routing value; The crossbar cell has a level that causes the value to be stored in the configuration memory circuit of the crossbar cell to modify the voltage on the single bit line, thereby allowing the data output path to be reassigned. The crossbar circuit of claim 3, further comprising a release circuit that releases the associated data output path.   The priority storage circuit in those crossbar cells associated with the released data output path depends on the voltage of at least one of the plurality of bit lines and the priority data stored therein The crossbar circuit of claim 5, responsive to the asserted release request to self-update. Each priority storage circuit includes a plurality of priority storage elements, each priority storage element being associated with one of the plurality of bit lines, and within each priority storage circuit, the plurality of priority storage elements. A current value of an element indicates a relative priority level of the source circuit coupled to the crossbar cell containing the priority storage circuit for the associated data output path;
The adaptive priority scheme is a longest time elapsed after acceptance (LRG) priority scheme;
Within the priority storage circuit of those crossbar cells associated with the released data output path, those priority storage elements associated with the bit lines whose voltages have been modified by the release circuit are: Set to a value, whereby the relative priority level of each source circuit excluding the source circuit releasing the data output path is increased or maintained;
For the crossbar cell containing the release circuit that has received the asserted release request, the priority storage circuit has its priority storage element cleared to a second value, whereby the data output The crossbar circuit according to claim 6, wherein the source circuit that releases a path is assigned a lower relative priority than the other source circuit.   At the time of initialization, the priority storage circuit of each crossbar cell is set to a predetermined value to provide an initial relative priority level of the plurality of source circuits for each of the plurality of data output paths. The crossbar circuit according to claim 1, which is initialized. Each of the bit lines is precharged to a first voltage level;
Upon receipt of the asserted release request, the release circuit discharges the voltage on the one bit line associated with the configuration storage circuit of the crossbar cell;
Each configuration storage circuit senses the voltage on its associated bit line to update the routing value to the second value if there is an asserted release request for the associated release circuit, and subsequently 6. The crossbar circuit of claim 5, further comprising a sense amplifier enable latch that performs the discharge operation by the release circuit, thereby releasing the associated data output path. Each data input path provides n word lines,
The release request for up to n crossbar cells associated with the same data input path is input to the crossbar circuit via the n word lines of the same data input path;
Each release circuit is associated with one of the n word lines, so for up to n crossbar cells associated with the same data input path, the release circuit of those crossbar cells 6. The crossbar circuit according to claim 5, comprising a different associated word line of the n word lines receiving the release request via the network.   The release request is issued in the arbitration mode of operation, and a control signal is used to identify whether the n word lines of the associated data input path are carrying a release request or a transmission request. The crossbar circuit of claim 10 issued by the plurality of source circuits in an arbitration mode of operation.   Each of the bit lines is precharged to a first voltage level to apply the adaptive priority scheme and then receives the asserted transmission request during the arbitration mode of operation. The crossbar circuit of claim 1, wherein the arbitration circuit of any crossbar cell associated with a path selectively discharges the voltage on the n bit lines.   Each configuration storage circuit includes a sense amplifier enable latch that senses the voltage on its associated bit line when an asserted transmission request is present, and subsequently performs the selective discharge operation by the arbitration circuit. The crossbar circuit according to claim 12, comprising: Each data input path provides n word lines,
In the arbitration operation mode, the transmission request of up to n crossbar cells associated with the same data input path is input to the crossbar circuit via the n word lines of the same data input path. The crossbar circuit according to claim 1.   Each configuration memory circuit is associated with one of the n word lines, so for up to n crossbar cells associated with the same data input path, the configuration memory circuit of those crossbar cells is 15. A crossbar circuit according to claim 14, comprising different associated word lines of the n word lines through which the transmission request is received. a matrix of mn × mn crossbar cells, where m is an integer greater than or equal to 2,
The matrix is divided into a plurality of sections;
A series of arbitration operations apply the adaptive priority scheme such that the configuration memory circuit of the only crossbar cell associated with the same data output path has its routing value programmed to the first value. For resolving conflicts between multiple asserted transmission requests according to the adaptive priority scheme,
The crossbar circuit of claim 15, wherein for each arbitration operation in the series, one or more of the sections in the plurality of sections are subjected to the arbitration operation.   17. The crossbar of claim 16, wherein each arbitration operation operates on a single section, and thus, after performing the series of arbitration operations, all of the plurality of sections are undergoing the arbitration operation. circuit. In a first arbitration operation of the series, all of the plurality of sections include the configuration storage circuit whose routing value is programmed to the first value. To identify the first arbitration operation,
In a second arbitration operation of the series, the one of the sections identified by the first arbitration operation is configured such that the routing value is programmed to the first value in the section. The crossbar circuit of claim 16, wherein the crossbar circuit is subjected to the second arbitration operation to identify a configuration memory circuit.   The asserted transmission request is accepted for the one crossbar cell associated with the same data output path, the configuration storage circuit having its routing value programmed to the first value during the arbitration mode of operation. The crossbar circuit of claim 1, wherein an acknowledge signal is asserted to the associated source circuit to confirm that it has been done. In the transmission mode of operation, each data output path associated with a crossbar cell is precharged to a first logic level before data transmission, and the transmission circuit of each crossbar cell is
First and second switches connected in series between the data output path and a second logic level;
In the transmission mode of operation, the first switch is opened or closed depending on the routing value stored in the associated configuration memory circuit, and the second switch is on the data input path. The crossbar circuit of claim 1, wherein the crossbar circuit is opened or closed depending on the data input at.   Each data input path comprises n word lines for carrying an n-bit input data value during the transmission operation mode, and each data output path includes an n-bit data value during the transmission operation mode. 21. The crossbar circuit of claim 20, comprising n bit lines for transporting at least the second switch for each bit line. Wherein in the transmission mode of operation, it is said routing value is the first value, when the input data bit or One-enabled word line is the first logic level, the bit lines of the data output path, 21. The crossbar circuit of claim 20, wherein the crossbar circuit is pulled to the second logic level.   Each crossbar cell turns off the first switch regardless of the routing value, while precharging the associated data output path to the first logic level, and the first switch 23. The cross of claim 22, further comprising a conditional discharge circuit controlled by the routing value and subsequently allowing the associated data output path to be precharged to the first logic level. Bar circuit. Wherein during the transmission operation mode, the detection of the data outputs of said bit lines of the data output path, whereby, before the voltage on the bit lines of the data output path reaches the second logic level, the 23. The crossbar circuit of claim 22, further comprising a sense amplifier circuit that enables detection of a transition to a second logic level. An encoding circuit between each of the plurality of source circuits and the plurality of data input paths;
A decoding circuit between each of the plurality of data output paths and the plurality of destination circuits;
The encoding circuit applies an encoding operation so that the input data provided by each source circuit is encoded into an encoding format, and the original input data passes through the crossbar circuit The data output path is pulled to the second logic level when compared to the number of times that it may be necessary to pull the data output path to the second logic level, and then they are Reduce the number of times it is necessary to precharge to a logic level of
Said decoding circuit, the provided by the source circuit from sign-data output at the data output on the path, so as to identify the input data of the original, to apply a corresponding decoding operation, according to claim 22 Crossbar circuit.   The crossbar circuit according to claim 1, wherein the plurality of source circuits can be connected to one end of the plurality of data input paths.   The crossbar circuit according to claim 1, wherein the plurality of destination circuits can be connected to any one end of the plurality of data output paths. Each data input path consists of multiple input path parts separated by a word line driver,
Each word line driver is provided along the associated data input path, but depends on the routing value stored in the configuration storage circuit of the crossbar cell, which is further from the source circuit than the word line driver. Is started,
Thereby, each word line driver is provided along the associated data input path, but the configuration storage circuit of at least one crossbar cell that is further from the source circuit than the word line driver is 2. The crossbar circuit of claim 1 that is activated only if it has a routing value set to a value of one. A plurality of memory devices for storing data values;
A plurality of processors for performing data processing operations in parallel on the plurality of data values stored in the plurality of memory devices;
The crossbar circuit of claim 1 for routing the data value from any of the plurality of memory devices to any of the plurality of processors;
A data processing apparatus. A plurality of source means and a plurality of destination means are interconnected so that data input from any of the plurality of source means to a crossbar circuit is output to any of the plurality of destination means A crossbar circuit that can
A plurality of data input path means passing through the crossbar circuit, each data input path means being connected to one of the plurality of source means and providing a plurality of word line means A plurality of data input path means,
A plurality of data output path means passing through the crossbar circuit traversing the plurality of data input path means, each data output path means being connected to one of the plurality of destination means; A plurality of data output path means for providing a plurality of bit line means;
Crossbar cell means associated with each intersection between one of the data input path means and one of the data output path means, each cross bar cell means comprising:
The function of at least one voltage of the plurality of bit line means for storing a routing value can be programmed in the arbitration mode of operation, a configuration storage unit, wherein the routing value, the data input path The first value indicates that data input to the associated intersection along the word line means of the means is output on the bit line means of the data output path means at the associated intersection. And wherein the routing value is a data input to the associated intersection along the word line means of the data input path means on the bit line means of the data output path means at the associated intersection. Configuration storage means programmed as indicated by the second value not being output;
In transmission mode of operation, the data input along the word line means of the data input path means is detected and an indication of the data is output on the bit line means of the data output path means at the associated intersection. Transmission circuit means responsive to the routing value having the first value,
Arbitration means for operating in the arbitration mode of operation depending on a transmission request received by the crossbar cell means from the source means connected to the data input path means of the associated intersection, If the transmission request is asserted to indicate that the source means wants to route data from the data input path means to the data output path means at the associated intersection, the arbitration means For selectively modifying the voltages on the plurality of bit line means, operating in combination with the arbitration means of other crossbar cell means associated with the same data output path means to apply the scheme Therefore, the same data output path If there are multiple asserted transmission requests in a stage, the configuration storage means of the only crossbar cell means associated with the same data output path means has its routing value programmed to the first value. Arbitrating means for resolving conflicts between the plurality of asserted transmission requests according to the adaptive priority scheme;
For storing priority data identifying which of the plurality of bit line means should have their voltages modified by the associated arbitration means to apply the adaptive priority scheme , A priority storage means,
During each application of the adaptive priority scheme by the arbitration means, depending on the voltage of at least one of the plurality of bit line means, for self updating the priority data stored therein Priority storage means;
Cross bar cell means comprising:
A crossbar circuit comprising: A plurality of source circuits and a plurality of destination circuits are interconnected, so that data input from any of the plurality of source circuits to a crossbar circuit is output to any of the plurality of destination circuits A method of operating a crossbar circuit, wherein the crossbar circuit is a plurality of data input paths that pass through the crossbar circuit, each data input path including the plurality of sources. A plurality of data input paths that can be connected to one of the circuits and provide a plurality of word lines, and a plurality of data output paths that pass through the crossbar circuit across the plurality of data input paths Each data output path has a plurality of data output paths that can be connected to one of the plurality of destination circuits and provide a plurality of bit lines; Serial method,
Employing a crossbar cell associated with each intersection between one of the data input paths and one of the data output paths;
In arbitration mode of operation, comprising the steps of programming a route value in each crossbar cell, said routing value is programmed as a function of at least one voltage of the plurality of bit lines, said routing value, As a first value indicates that data input to the associated intersection along the word line of the data input path is output on the bit line of the data output path at the associated intersection. The routing value is programmed so that data input to the associated intersection along the word line of the data input path is not output on the bit line of the data output path at the associated intersection. A step programmed as indicated by a value of 2;
Detecting, in a transmission mode of operation, the data input along the word line of the data input path and outputting an indication of the data on the bit line of the data output path at the associated intersection; Causing a crossbar cell to respond to the routing value having the first value;
Operating the arbitration circuit in the crossbar cell in the arbitration mode of operation in dependence on a transmission request received by the crossbar cell from the source circuit connected to the data input path of the associated intersection. The arbitration circuit is adaptive when the transmission request is asserted to indicate that the source circuit wishes to route data from the data input path to the data output path at the associated intersection. Operating in combination with the arbitration circuit of another crossbar cell associated with the same data output path to selectively modify the voltages of the plurality of bit lines to apply a type priority scheme; Multiple asserts on the same data output path If transmission request exists, the configuration memory circuit only crossbar cells associated with the same data output path has its routing value to be programmed into the first value, whereby said adaptive priority Resolving conflicts between the plurality of asserted transmission requests according to a ranking scheme;
In order to apply the adaptive priority scheme, priority data identifying which of the plurality of bit lines should have their voltages modified by the associated arbitration circuit is stored in the crossbar cell. Storing in the priority storage circuit of
During each application of the adaptive priority scheme by the arbitration circuit, depending on the voltage of at least one of the plurality of bit lines, self-updates the priority data stored therein, Configuring the priority storage circuit;
Including a method.