JPH11340998A - Atm switch and method for managing buffer for atm cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ATM switch that manages a buffer with less hardware. SOLUTION: A flow signal generating section 50 is newly provided with overflow registers OVF#0-OVF#7 corresponding to logic queues LQ#0-LQ#7. A coincidence detection circuit compares counter values of cell counters CC#0-CC#7 with threshold values of threshold value registers THR#0-THR#7. In the case that the counter values are coincident wit the threshold values, a state of an overflow flag register OVF#X corresponding to the register is switched alternately to a set state and a clear state. The overflow flag registers OVF#0-OVF#7 discriminate whether or not the count of the logic queues LQ#0-LQ#7 exceeds the threshold value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM switch and a buffer management method for ATM cells.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional shared buffer type ATM switch having a shared buffer for storing ATM cells (hereinafter referred to as cells). As can be seen from FIG.
The M-switch is composed of a single integrated circuit chip or a plurality of integrated circuit chips. The ATM switch is composed of an 8 × 8 switch having an ATM cell having eight input ports IP # 0 to IP # 7 and eight output ports OP # 0 to OP # 7. 622
Cell input / output is performed at a data transfer rate of Mbps. Each cell includes a header section and a data section, and the header section stores destination information of the cell itself.

The shared buffer type ATM switch includes a physical shared buffer 30. This shared buffer 3
0 forms a logical buffer for each of the output ports OP # 0 to OP # 7.
To LQ # 7. Each logical queue LQ # 0-L
The capacity of the buffer allocated to Q # 7 is flexibly allocated according to the number of cells going to each output port OP # 0 to OP # 7 input to the ATM switch. Cells input from each of the input ports IP # 0 to IP # 7 are stored in the control unit 2
0, the destination information included in the header is analyzed by the internal header analysis unit 21, and the logical queues LQ # 0 to LQ # 7 corresponding to the destination output port via the multiplexer 22.
(Shared buffer 30). The control unit 20
Logical queue L corresponding to output ports OP # 0 to OP # 7
When a cell is stored in Q # 0 to LQ # 7, the cell is read from the logical queue LQ # 0 to LQ # 7, and the logical queue LQ # 0 to LQ is demultiplexed via the demultiplexer 64.
The cell is output to output ports OP # 0 to OP # 7 corresponding to # 7.

[0004] Usually, a shared buffer type ATM switch is
Since there is only one input port of the shared buffer 30, for example, when eight cells are input simultaneously in one cell cycle, the header analysis unit 21 performs the header analysis of the sequentially input cells, and based on the analysis result, , Logical queue LQ #
Cells are sequentially written to X (hereinafter, an unspecified one is represented by X). At the same time as the cell destination information analysis (output port analysis) in the header analysis unit 21, the flow signal generation unit 70 causes the logical queues LQ # 0 to LQ assigned to each of the output ports OP # 0 to OP # 7. It is sequentially checked whether # 7 does not exceed the buffer capacity. Logical queue LQ assigned to each output port OP # 0 to OP # 7
The maximum buffer capacity of # 0 to LQ # 7 is determined by the threshold registers THR # 0 to THR # provided in the flow signal generation unit 70.
7 (see FIG. 5).

FIG. 5 shows the internal configuration of the flow signal generator 70. Eight local threshold registers THR # 0
THR # 7 specifies the maximum buffer capacity of the logical queues LQ # 0 to LQ # 7 of each of the output ports OP # 0 to OP # 7. Global threshold register THRGL is ATM
Specify the maximum buffer capacity of the entire switch. For example,
The total capacity of the shared buffer 30 is 640 cells, which are stored in the logical queues LQ of the eight output ports OP # 0 to OP # 7.
In a case where the usage is equally distributed to # 0 to LQ # 7, the logical queue LQ of each output port OP # 0 to # OP7 is used.
The threshold values of # 0 to LQ # 7 are set to 80 cells. That is, the threshold values of the threshold value registers THR # 0 to THR # 7 are set to 80. The global threshold value of the entire ATM switch is set to 640. That is, the threshold value of the threshold value register THRGL is set to 640. If the counter values of the cell counters CC # 0 to CC # 7 are equal to the threshold values of the threshold value registers THR # 0 to THR # 7, no more cell input is possible or should be suppressed. The flow control signal is output to a device located in the preceding stage of the ATM switch to instruct the cell transmission to stop. The same applies when the counter value of the global cell counter GCC is equal to the global threshold value register THRGL.

The comparison between the counter value and the threshold value is as follows:
This is performed by the comparison circuits 90 to 98. The device located before the ATM switch includes eight flow signals FCO #
Check 0 to FCO # 7. Then, transmission of the cells destined for the output ports OP # 0 to OP # 7 under flow control to the ATM switch is stopped. When over is detected in the global cell counter GCC, it is necessary to stop sending cells to all the output ports OP # 0 to OP # 7. Therefore, the comparison result of the local comparison circuits 90 to 97 and the comparison result of the global comparison circuit 98 are input to the OR circuits OR0 to OR7, and these OR signals are output as flow signals.

If the input cell is a multicast cell, the same cell is copied to a plurality of output ports OP # X and output. Therefore, for example, when a certain cell is multicast to all output ports, the logical queues LQ # 0 to LQ # for each of the eight output ports OP # 0 to OP # 7
Copy to 7 and enter. Therefore, it is necessary to execute the check of the eight cell counters CC # 0 to CC # 7 in parallel in one cell input permission determination. In addition, in order to check whether the global cell counter GCC exceeds the buffer capacity of the entire ATM switch, it is necessary to execute a check of nine cell counters in parallel. Therefore, it is necessary to separately provide nine comparison circuits 90 to 98.

In the above description, the delay priority class management is not performed. However, when the delay priority class management is performed, it is necessary to add a shared buffer 30 for each output port, perform divided management for each class, and provide a logical queue. is there. Consider a case where eight output ports support five classes of delay priority.
One class, eight ports per port, one global per class
A total of 9 cell counters are required for each class, so 4 for 5 classes
Five cell counters are required. In addition to this, ATM
Since a global cell counter for the entire switch is also required, a total of 46 cell counters are required. As described above, 46 threshold registers are required in pairs with the cell counter. The flow signal is generated based on the determination result of the cell counter corresponding to the output port, the determination result of the global counter for each class to which it belongs, and the determination result of the global counter of the entire switch.

The cell counter and the threshold value comparison circuit can be reduced to some extent, for example, by sharing the classes, but due to the processing speed, the number tends to increase as the number of supported delay classes increases. . In addition, if the sharing is performed, for example, the delay time of the selector input to the comparison circuit and the selector for selecting the threshold register increases, and the comparison processing time increases. Need to be installed.

[0010]

As apparent from the above description, as the scale of the output port of the ATM switch is expanded and the number of classes supported in delay priority is increased, the cell counter, the threshold register, and the comparison circuit are increased. , And the hardware of the control circuit is significantly increased. In addition, since the input permission is determined by comparing the magnitude relationship between the threshold value and the cell counter, it is generally composed of a subtractor or the like. This is a factor that lowers the throughput of the entire switch.

[0011] Such a problem occurs not only in the above-described shared buffer type ATM switch but also in an output buffer type ATM switch having a plurality of logical queues and an input type buffer. In addition, the present invention has been made in view of the above-mentioned problem, and has a large switch size, supports a large number of delay priority classes, and manages a logical queue to be managed. Even if the number is huge,
It is an object of the present invention to provide an ATM switch and a buffer management method for ATM cells that can manage a buffer with a small amount of hardware. That is, an object of the present invention is to provide an ATM switch and a buffer management method for an ATM cell which enable high-speed threshold value determination and high throughput.

[0012]

To solve the above problems, an ATM switch according to the present invention comprises a plurality of input ports to which ATM cells are input, a plurality of output ports to which ATM cells are output, and A input from input port
A cell buffer for storing TM cells, wherein a logical queue is assigned to each of the output ports;
A cell buffer for accumulating the ATM cells in the logical queue corresponding to each output port according to a destination of the cell; and a plurality of cell counters provided for each of the output ports, wherein Each time an ATM cell addressed to a port is input to the logical queue of the cell buffer, the counter value is incremented, and each time an ATM cell is output from the logical queue of the cell buffer, the corresponding output port is output. A cell counter for decrementing a counter value, and a plurality of threshold registers provided for each of the cell counters, each of which holds a threshold value of the number of ATM cells stored in each of the logical queues;
A threshold register and a plurality of coincidence detection circuits provided for each of the cell counters, wherein the counter values of the cell counters and the threshold registers provided corresponding thereto are held. A threshold value, for detecting whether or not they match, a match detection circuit, and a plurality of overflow flag registers provided for each of the match detection circuits,
An overflow flag register that alternately switches the state between set and clear each time the match circuit detects a match.

[0013] Also, the ATM cell buffer management method according to the present invention comprises a plurality of input ports to which ATM cells are input, a plurality of output ports to which ATM cells are output, and an ATM input from each of said input ports. A cell buffer for accumulating cells, wherein a logical queue is assigned to each output port, and the AT is assigned to the logical queue corresponding to each output port according to the destination of the ATM cell.
A cell buffer for storing M cells.
An ATM cell buffer management method in a TM switch, wherein a plurality of cell counters provided for each of said output ports each time an ATM cell addressed to a corresponding output port is input to said logical queue of said cell buffer. Incrementing the counter value, decrementing the counter value each time an ATM cell is output from the logical queue of the cell buffer, counting the number of the ATM cells stored in each of the logical queues, With a plurality of threshold registers provided for each cell counter,
A match detection circuit provided for each of the cell counters holds a threshold value of the number of ATM cells stored in each of the logical queues, and a counter value of each of the cell counters;
It is detected whether or not the threshold value of each of the threshold value registers provided in correspondence with the threshold value coincides with each other. If a coincidence is detected by the coincidence detection circuit, The state of the provided overflow flag register is alternately switched between set and clear.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The ATM switch according to the present embodiment is provided with a new overflow register in a flow signal generation unit and a coincidence detecting circuit for comparing a counter value of a cell counter with a threshold value of a threshold value register. In this way, it is possible to determine the input permission / non-permission of the ATM cell with a small amount of hardware and manage the buffer. Hereinafter, this will be described in more detail with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of the ATM switch according to this embodiment. As can be seen from FIG. 1, the ATM switch includes a plurality of input ports IP # 0 to IP # 7 to which ATM cells are input, and the ATM switch.
A plurality of output ports OP # 0 to OP # 7 to which cells are output
And The input ports IP # 0 to IP # 7 are provided with FIFO type buffers 10 to 17, respectively. In the cells input to the buffers 10 to 17, the destination information written in the header of the cells is analyzed by the header analysis unit 21 included in the control unit 20. A control signal is output from the header analysis unit 21 based on the analysis result, and is input to the multiplexer 22. The multiplexer 22 receives the control signal
A cell is allocated for each output port OP # X that is a destination, and a corresponding logical queue L in the shared buffer 30 is allocated.
The cell is stored in the area of Q # X.

When a cell is stored in the shared buffer 30,
Cells are read from the logical queue LQ # X of the shared buffer 30 based on the control signal output from the control unit 20. Then, the connection of the demultiplexer 64 is switched, and a cell is given to the corresponding output port OP # X,
Output to the outside.

The ATM switch is provided with local cell counters CC # 0 to CC # 7 and a global cell counter GCC. The local cell counters CC # 0 to CC # 7 store logical queues LQ # 0 to LQ
Each is provided corresponding to # 7. Logical queue L
Each time a cell is input to any of Q # 0 to LQ # 7, the corresponding cell counter CC # 0 to CC # 7 is incremented and a cell is output from any of logical queues LQ # 0 to LQ # 7. Cell counters CC # 0 to CC # 0
CC # 7 is decremented. Only one global cell counter GCC is provided for the entire ATM switch. Every time a cell is input to any of the logical queues LQ # 0 to LQ # 7, a global cell counter GCC
Are incremented, and logical queues LQ # 0 to LQ # 7
, The global cell counter GCC is decremented each time a cell is output. The counter values of the cell counters CC # 0 to CC # 7 and GCC are input to the flow signal generation unit 50 as CCQ0 to CCQ7 and GCCQ.

FIG. 2 is a diagram showing the internal configuration of the flow signal generator. As can be seen from FIG. 2, the flow signal generation unit 50 is configured to include the coincidence detection circuits 40 to 48. The coincidence detection circuits 40 to 47 have threshold values from threshold value registers THR # 0 to THR # 7, respectively.
The counter values of the cell counters CC # 0 to CC # 7 are input. In these coincidence detection circuits 40 to 47,
It is detected whether or not these threshold values and the counter value match, and if they match, flag switching signals OV0 to OV7 for switching the states of the corresponding overflow flag registers OVF # 0 to OVF # 7 are output. I do. The match detection circuit 48 has a global threshold register T
The threshold value from HRGL and the counter value from global cell counter GCC are input. The coincidence detection circuit 48 detects whether or not the threshold value and the counter value coincide with each other, and if they coincide, outputs a flag switching signal OVGL for switching the state of the global overflow flag register OVFGL.

Overflow flag register OVF # 0
To OVF # 7 are output from corresponding OR circuits OR0 to OR0.
The output from OR7 and the output from the overflow flag register OVFGL are commonly input to OR circuits OR0 to OR7. From the OR circuits OR0 to OR7,
Each of the flow signals FCO # 0 to FCO # 7 is output to a device located at the preceding stage.

In this embodiment, a reset operation is performed when the system is started up.
Threshold registers THR # 0 to THR # 7, THRGL
, Cell counters CC # 0 to CC # 7, GCC, and overflow flag registers OVF # 0 to OVF # 7, O
VFGL is set to zero. Thereafter, when setting the initial value of the system, the threshold value registers THR # 0 to THR # TH
R # 7 and THRGL are written in advance with the cell accumulation permission number as a threshold.

In the ATM switch according to the present embodiment, during the entire operation of the ATM switch, only one cell input or output per one system clock cycle is applied to the logical queues LQ # 1 to LQ # 7. Provide a mechanism that does not do this. For example, even when eight cells are input to one logical queue LQ # X per cell cycle, eight cells are simultaneously stored in one logical clock LQ # X in one system clock cycle. The operation of the cell counter CC # X that manages the number of cells stored in the logical queue LQ # X is prevented from incrementing by eight at a time in one system clock cycle of the switch LSI. Similarly, even when eight cells are output per cell cycle for one logical queue LQ # X, eight cells are output simultaneously for one logical clock LQ # X in one system clock cycle. The cell counter CC # X that manages the number of cells stored in the logical queue LQ # X decrements by 8 at a time in one system clock cycle of the switch LSI. That is, cell counters CC # 0-CC
One of # 7 is one system clock cycle,
Use a control mechanism that only increments or decrements. By providing such a mechanism, the comparison process between the counter values of the cell counters CC # 0 to CC # 7 and GCC and the threshold values of the threshold value registers THR # 0 to THR # 7 and THRGL is subtracted. Match detector 4 instead of detector
0 to 48 can be configured.

Each of the counter values of the cell counters CC # 0 to CC # 7 always passes through a point corresponding to each of the threshold values of the threshold registers THR # 0 to THR # 7 during the switching operation. . These cell counters CC #
Overflow flag registers OVF # 1 to OVF # 7 are provided corresponding to each of 0 to CC # 7.
A state where the cell counter CC # X, which is one of the cell counters CC # 0 to CC # 7, has not exceeded the threshold value;
That is, when the overflow flag register OVF # X corresponding to the cell counter CC # X matches in the cleared state, the overflow flag register OVF # X is set. Conversely, if the values exceed the threshold value, that is, if the overflow flag register OVF # X of the cell counter CC # X is set, the overflow flag register OVF # X is cleared. By the above mechanism, the logical queues LQ # 0 to LQ # 7 in the shared cell buffer 30
Threshold value control becomes possible.

Similarly, the counter value of the global cell counter GCC always passes through a point located at the threshold value of the global threshold register THRGL during the switching operation. For this reason, when the threshold value and the counter value match, the state of the overflow flag register OVFGL is alternately switched between clear and set, so that the entire ATM switch exceeds the threshold value. Or
It is determined whether the state does not exceed the threshold.
As a result, threshold control of the entire ATM switch becomes possible.

Threshold registers THR # 0 to THR # 7
If the user changes the threshold value during the switching operation (hereinafter referred to as a dynamic threshold value change), the consistency of the overflow determination result is lost. It is also possible to provide a mechanism.

For example, when the dynamic threshold value is changed, the overflow flag register OVF # X of the cell counter CC # X of the logical queue LQ # X corresponding to the forcibly changed threshold value is set. Set to prohibit cell input to this logical queue LQ # X. Logical queue LQ # X
A mechanism is provided for clearing the flag of the overflow flag register OVF # X when all the cells are output. As described above, consistency of the determination result can be maintained.

Further, the consistency of the determination result can be ensured by the following mechanism. That is, all the logical queues L
A comparison circuit including a subtraction circuit commonly used in Q # 0 to LQ # 7 is provided. Then, the counter value of the cell counter CC # X of the logical queue LQ # X that has changed the dynamic threshold value and the threshold value of the threshold value register THR # X are input to this comparison circuit. In this way, the overflow is determined by comparing the two, and the cell counter CC that has performed the determination is determined.
A mechanism for resetting the overflow flag register OVF # X of #X may be provided. That is, as a result of the comparison by the comparison circuit including the subtraction circuit, if the threshold value of the new threshold value register THR # X is larger than the counter value of the cell counter CC # X, the flag of the overflow flag register OVF # X is cleared. To On the other hand, if the threshold value of the new threshold value register THR # X is smaller than or equal to the counter value of the cell counter CC # X, the flag of the overflow flag register OVF # X is set.

FIG. 4 is a diagram showing an example of a specific circuit configuration of the coincidence detection circuit. As can be seen from FIG. 4, the coincidence detection circuit includes ENOR gates EN (0) to EN (i) and N
And an AND gate NA. Each of the ENOR gates EN (0) to EN (i) has a threshold value register TH.
Each bit TH (0) to TH (i) from R # X and each bit CCQ (0) to CCQ from cell counter CC # X
(I) has been input.

As described above, the ATM switch according to the present embodiment includes the counter values of the cell counters CC # 0 to CC # 7 corresponding to the logical queues LQ # 0 to LQ # 7 and the cell counters CC # 0 to CC # 7, the threshold value registers THR # 0 to THR # 7 determine whether or not the threshold value matches the threshold value of each of the match detection circuits 40 to
Detect at 47. When the counter value and the threshold value match, each of the logical queues LQ # 0 to LQ #
7 is switched between overflow flag registers OVF # 0 to OVF # 7 provided correspondingly to the respective registers. That is, the overflow flag register OVF #
If the counter value and the threshold value match in a state where 0 to OVF # 7 are cleared (a state where the threshold value is not exceeded), it means that the counter value has exceeded the threshold value. Flag registers OVF # 0 to OVF
Set # 7. Conversely, if the counter value and the threshold value match while the overflow flag registers OVF # 0 to OVF # 7 are set (the threshold value is exceeded), the value becomes equal to or smaller than the threshold value. Overflow flag register OVF #
0 to OVF # 7 are cleared. As described above, the coincidence detecting circuits 40 to 47 detect the coincidence between the threshold value and the counter value, and the logical queues LQ # 0 to LQ # 7 can be used without using the conventional magnitude comparison circuit (full adder). , The circuit scale can be greatly reduced. Also, the time required for the determination is
Since the comparison operation is completed in the time when the two gates of the OR gates EN (0) to EN (i) and the NAND gate NA pass, the speed is greatly increased as compared with the conventional size comparison circuit. be able to.

The present invention is not limited to the above embodiment, but can be variously modified. For example, in the above embodiment, the comparison between the threshold value of the global threshold value register THRGL and the counter value of the global cell counter GCC is performed by the coincidence detection circuit 48. It is also possible to perform the comparison with a conventional magnitude comparison circuit (full adder).

The priority control class includes classes such as CBR and ABR defined by the ATM Forum and the like,
CLP value or VPI / VC written in TM cell header
The association may be performed based on the I value.

Further, although the embodiment of the shared buffer type has been described above as an example, it is needless to say that other types of switches including a cell buffer such as an output buffer type and an input buffer type can be similarly applied. No.

[0032]

According to the ATM switch of the present invention,
Since the match detection circuit can determine whether the cell input is permitted or not, the switch size is large, the number of supported delay priority classes is large, and the number of buffers to be managed is large.
Even with a TM switch, buffer management can be realized with a small amount of hardware. Further, high-speed threshold determination is possible, and an ATM switch with high throughput can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an ATM switch according to an embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration of a flow signal generation unit in FIG. 1;

FIG. 3 is a diagram illustrating an example of a circuit configuration of a match detection circuit.

FIG. 4 is a diagram showing an entire configuration of a conventional ATM switch.

FIG. 5 is a diagram showing an internal configuration of a flow signal generation unit in a conventional ATM switch.

[Explanation of symbols]

10-17 Buffer 20 Control unit 21 Header analysis unit 22 Multiplexer 30 Shared buffer 40-47 Match detection circuit (local) 48 Match detection circuit (global) 50 Flow signal generation unit 64 Demultiplexer CC # 0-CC # 7 Cell counter ( Local) GCC cell counter (global) THR # 0 to THR # 7 Threshold register (local) THRGL Threshold register (global) OVF # 0 to OVF # 7 Overflow flag register (local) OVFGL Overflow flag register (global)

Claims (6)

[Claims] 1. A plurality of input ports to which ATM cells are input, a plurality of output ports to which ATM cells are output, and a cell buffer for storing ATM cells input from each of the input ports, A cell buffer for allocating a logical queue to each output port and storing the ATM cells in the logical queue corresponding to each output port according to the destination of the ATM cell; A plurality of cell counters provided, each time an ATM cell addressed to a corresponding output port is input to the logical queue of the cell buffer, increments the counter value, and outputs an ATM from the logical queue of the cell buffer. A cell counter for decrementing the counter value of the corresponding output port each time a cell is output; A plurality of threshold registers provided for each counter, the threshold register holding a threshold value of the number of ATM cells stored in each of the logical queues; and a plurality of threshold registers provided for each of the cell counters. A coincidence detecting circuit for detecting whether or not a counter value of each of the cell counters and a threshold value held by each of the threshold value registers provided corresponding thereto coincide with each other. A detection circuit; and a plurality of overflow flag registers provided for each of the match detection circuits, wherein each time the match circuit detects a match, the overflow flag register alternately switches a state between set and clear. An ATM switch, characterized in that: 2. For each logical queue in the cell buffer, within one system clock cycle:
A mechanism that performs only the input or output of one ATM cell,
The ATM of claim 1, further comprising:
switch. 3. The ATM switch according to claim 1, wherein a threshold value of each of said threshold value registers is configured to be changeable during a switching operation. 4. When a threshold value of said threshold value register is changed, input of ATM cells to said logical queue corresponding to said threshold value register whose threshold value has been changed is temporarily inhibited. 4. The consistency between the state of the overflow flag register and the state of the logical queue is ensured by outputting all ATM cells accumulated in the logical queue. A described
TM switch. 5. When a threshold value of said threshold value register is changed, a counter value of said cell counter corresponding to said threshold value register whose threshold value has been changed is changed. The threshold value is compared with a threshold value by a comparison circuit, and the content of the overflow flag register is rewritten according to the result of the comparison. The ATM switch according to claim 3, wherein consistency is ensured. 6. A plurality of input ports to which ATM cells are input, a plurality of output ports to which ATM cells are output, and a cell buffer for storing ATM cells input from each of the input ports, A logical queue is assigned to each output port, and the AT is assigned to the logical queue corresponding to each output port according to the destination of the ATM cell.
A cell buffer for storing M cells.
An ATM cell buffer management method in a TM switch, comprising a plurality of cell counters provided for each of said output ports, each time an ATM cell addressed to a corresponding output port is input to said logical queue of said cell buffer. Incrementing the counter value, decrementing the counter value each time an ATM cell is output from the logical queue of the cell buffer, counting the number of the ATM cells accumulated in each of the logical queues, A plurality of threshold registers provided for each cell counter hold a threshold value of the number of ATM cells stored in each of the logical queues, and a match detection circuit provided for each cell counter provides The counter value of each cell counter and the threshold value of each of the threshold value registers provided corresponding thereto are equal to one another. If the match detection circuit detects a match, the state of the overflow flag register provided for each match detection circuit is alternately switched between set and clear. A buffer management method for ATM cells, characterized in that: