JP2000030469A - Associative memory cell and associative memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an associative memory cell and an associative memory which can retrieve plural retrieval data rows or plural mask setting information rows at one time. SOLUTION: This associative memory cell contains (1) two pairs of retrieval data line pairs RB and the inverse of RB, RC and the inverse of RC, (2) N21-N23 and N31-N33 for retrieving whether or not the retrieval data given to these two pairs of retrieval data line pairs each agree with the data held at a node of P1 and N1, and a node of P2 and N2, respectively, and (3) match lines MLB and MLC for outputting these retrieved results.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an associative memory cell and an associative memory, and can be applied to, for example, an apparatus for performing an exchange process in message units.

[0002]

2. Description of the Related Art Document 1: Supervised by Takuo Sugano, edited by Tetsuya Iizuka,
"Design of CMOS LSI", pp.176-177, Baifukan, 19
96 Content Addresable Memory;
AM)), as described in the above-mentioned reference 1, not only does the input of an address as in a normal RAM (Random Access Memory) to read or write a data string, but also the search data This memory is provided with a search function (collation function) for inputting a column and searching for the presence or absence of a word having a matching or similar data column and the number of addresses in a single or several cycles.

In order to provide such a function, a conventional CAM cell has a configuration in which a search function is added to a normal SRAM (Static RAM) cell. Here, generally, as shown in FIG. 2 or FIG. 3, a CAM cell without a search enable line is often used. Also, CAM is
As shown in FIG. 4, similar to the SRAM, the CAM cell has an array structure of n words * m bits. Hereinafter, CA
The basic operation of M will be described with reference to the CAM cell shown in FIG.

[0004] P-channel MOS type FETs (hereinafter referred to by prefixing the symbol "P" and omitting names unless otherwise required) 1 and N-channel MOS type FETs (hereinafter referred to as "N ), And the names are omitted unless otherwise required.) The connection point of 1 and the connection points of P2 and N2 hold complementary logics (binary). For example, the “H” level at the connection point between P1 and N1 is P2 and N
When the "L" level is given to the connection point of No. 2, P1 and N2 are turned on ("turned on" means that the drain-source of the FET is electrically connected, and so on). Used), P2 and N1 are turned off (here, "turned off" means that there is no conduction between the drain and source of the FET, and the same applies hereinafter), so that given logic is maintained. Become.

Here, when the "H" level is applied to the word line WL, N3 and N4 are turned on, so that the bit line pair BL and BL / When a data is given to a line with "/" added to the end of the code, and "-" is added at the top of the code in the drawing), the bit lines BL and BL / And the complementary logic given to P1 and N1
And the connection points of P2 and N2. On the other hand, when data is not applied to bit line pair BL and BL /, complementary logic held at the connection point between P1 and N1 and the connection point between P2 and N2 is applied to bit lines BL and BL /. , Data will be output. As will be understood from this description, data transmitted to and received from the memory is processed as a complementary logical signal in the memory.

When the search data is applied to the bit line pair BL and BL / while the word line WL is at the "L" level, the logic applied to the bit lines BL and BL / is P1 and If the logic held at the connection point of N1 and the connection point of P2 and N2 does not match, the N11 or N12 connected to the "H" level bit line BL or BL / is turned on, and the connection between N11 and N12 is performed. The point becomes "H" level, and as a result, N13 turns on, so that the match line ML becomes "L" level. On the other hand, when the logic applied to the bit lines BL and BL / matches the logic held at the connection point between P1 and N1 and the connection point between P2 and N2, the "L" level bit line BL or BL / Since N11 or N12 connected to / is turned on, if the connection point between N11 and N12 is at "L" level and the match line ML is at "H" level, N1 or N12 is turned on.
3 remains off, and the match line ML is also maintained at the “H” level. However, both bit lines BL and BL /
When the "L" level is applied, the connection point between N11 and N12 is at the "L" level regardless of which of N11 and N12 is turned on, so that N13 remains off and the match line ML is also at the "H" level. The CAM cell shown in Fig. 3 performs the same operation.

That is, in this CAM search operation, all word lines are set to "L" level and all match lines are set to "H".
When the search data string is input to the bit line pair to be searched (care) and the “L” level is input to the bit line pair not to be searched (masked) in the state where the level is set, the matched data string is held. Only the match line connected to the CAM cell in question is held at the “H” level.

On the other hand, various functions are added to the peripheral circuit of the CAM according to the requirements of the application system. For example,
(1) a mask function circuit for setting whether to care or mask, and a mask setting register circuit for storing the information sequence;
(2) An encoder circuit that converts a matched address into a binary signal (especially, in the case of multiple matches, many encoder circuits have a priority function that separates and outputs a high-priority address), and (3) there is no match (4) a multiple match detection circuit that detects the presence of multiple matches, (5) a FULL detection circuit that detects the presence of registered (stored) data at all addresses, (6) which There is an EMPTY detection circuit for detecting that there is no registered (stored) data in the address.

Reference 2: Atsuo Ito, Koji Suzuki, Hidenori Hisamatsu,
Yasuki Ishido, Naoto Honda, "A Study of High-speed and Wide-band Data Exchange System Using ATM", IEICE, Integrated Circuits Workshop, SSE90-128, IN90-89, pp.19-24 Next, this CAM An address translation device, which is a kind of application system using, will be described. FIG.
Connectionless using ATM technology disclosed in
1 shows an outline of a routing process of an address translation device (also called a header converter) in a data exchange system. The message (“cell” in the figure) of the connectionless communication includes the destination address (“DA” in the figure) and the source address (“SA” in the figure). A corresponding connection number (VPI, VCI) is searched by the routing CAM 1 based on the destination address, and a corresponding connection number is read from the header conversion table 2 based on the search result, and the header conversion circuit 3 The read connection number is added to the cell header and converted. The cell with this header converted is A
Via a TM switch, it is assigned to a line in its own station or sent to another station.

Here, the first search method of the routing CAM 1 will be further described. A routing CAM for identifying whether the destination address of the arriving cell is the address of the own station or the address of another station.
In 1, the in-station / out-station identifier is also registered in advance when the destination address is registered. Therefore, first, a search is performed so that the in-station identifier matches, and it is checked whether there is a corresponding connection number in the station. If there is no corresponding connection number, a search is performed so that the outside identifier matches,
Check if there is any other station number. After the search within the office or outside the office is performed in this way, the search for the destination address is performed.

FIG. 6 shows an example of the second search method. For example, assume that there is a destination address having four parts, aaaa-bbbb-cccc-dddd (hexadecimal). 0
When examining a destination address of 120-0301-F61A-1111 as a search data string, first, we want to examine a data string in which all numbers match. However, if there is no data string corresponding to this, it is desired to examine a data string in which the first three parts match. Still, if there is no corresponding data string, it is desirable to further check a data string that matches only at the beginning.
As described above, the search is sequentially performed by changing the part to be collated.

[0012]

However, when the above-described first search method is performed by the CAM used in the conventional address translation device, the search data string is changed every time the data string to be searched changes, and the search is performed again. Since the destination address is searched after the search inside or outside the station is performed, the search must be performed at least twice. Further, when the above-described second search method is performed, it is necessary to change the mask setting information sequence every time the mask setting information sequence for setting the care / mask of the search data changes, and perform the search again.
You must search up to four times.

As described above, the conventional address translator C
In the AM, a plurality of searches are required to process one address, and there is a problem that the processing becomes complicated and the processing speed is reduced.

On the other hand, in order to avoid this, it is only necessary to use CAMs in parallel. However, the number of CAMs required in parallel is required, and there is a problem that the apparatus is large and the price is high.

Therefore, there has been a demand for an associative memory cell and an associative memory which can search for a plurality of search data strings or a plurality of mask setting information strings at one time.

[0016]

According to a first aspect of the present invention, there is provided an associative circuit having a memory cell and a matching unit for determining whether data held in the memory cell matches search data. The memory cell has a plurality of matching units to which different search data are given.

According to a second aspect of the present invention, there is provided an associative memory cell having a memory cell and a collating means for judging a match between the data held in the memory cell and the search data and outputting the same. Retrieve duplicate results 1
It has the above-mentioned extracting means, and each extracting means outputs or stops the output of the judgment result of the above-mentioned collating means which has been redundantly extracted, based on the mask setting information.

Further, the associative memory of the third invention has a plurality of associative memory cells of the first or second invention addressed in a matrix by a plurality of word lines and a plurality of bit line pairs. The match determination signal output from each associative memory cell is output to a plurality of match lines provided corresponding to a plurality of word lines for each search data column and / or for each mask setting information column.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (A) First Embodiment Hereinafter, a first embodiment of an associative memory cell according to the present invention will be described in detail with reference to the drawings.

(A-1) Description of Configuration FIG. 1 is a circuit diagram showing a configuration of an associative memory cell according to the first embodiment. In FIG. 1, the associative memory cell includes P-channel MOSFETs P1 and P2 and N-channel MOSFETs N1 to N4, N11 to N13,
N21 to N23 and N31 to N33.

Each of P1 and P2 conducts between the source and the drain when the gate is supplied with the "L" level, and does not conduct between the source and the drain when the "H" level is supplied to the gate. is there. In addition, in each of the embodiments described below, the ones with the prefix “P” are all the same.

N1 to N4, N11 to N13, N21 to N
Reference numerals 23 and N31 to N33 allow conduction between the source and the drain when the "H" level is applied to the gate, and do not allow conduction between the source and the drain when the "L" level is applied to the gate. . In addition, in each of the embodiments described below, the ones with the prefix “N” are all the same.

Here, the connection relationship between the components will be described. The sources of P1 and P2 are connected to a power supply that supplies an “H” level, the sources of N1 and N2 are connected to ground that supplies an “L” level, and the drain of P1 is N1.
, And the drain of P2 is connected to the drain of N2.

The connection point between P1 and N1 is connected to the drain of N3, and P2, N2, N12, N2
2 and the gate of N32. On the other hand, P2 and N
2 is connected to the drain of N4 and
1, N1, N11, N21 and N31 are connected to the gates.

Further, the gates of N3 and N4 are connected to word line WL, the source of N3 is connected to bit line BL, and the source of N4 is connected to bit line BL /. Between the bit line pair BL and BL /, from the bit line BL side,
The source and drain of N11, the drain and source of N12 are connected, and between the search data line pair RB and RB /, the source and drain of N21 and the drain and source of N22 are connected from the search data line RB side, The source and drain of N31 and the drain and source of N32 are connected between the search data line pair RC and RC / from the search data line RC side.

Further, N13 has its drain connected to the match line MLA, its source connected to ground, its gate connected to the connection point of N11 and N12, and N23 connected to
Its drain is connected to the match line MLB, its source is connected to ground, its gate is connected to the connection point of N21 and N22, and N33 has its drain connected to the match line MLC, its source connected to ground, and its gate connected to N31 and N3.
2 connection points.

Here, the function of each component connected in this way will be described.

P1, P2, N1 and N2 are P1 and N
1 holds the logics complementary to each other and given to the connection point 1 and the connection points P2 and N2. For example, the “H” level at the connection point between P1 and N1 is P2 and N
When the "L" level is given to the connection point of P2, P1 and N2
Are turned on and P2 and N1 are turned off, so that the given logic is maintained.

When the word line WL is supplied with the "H" level, N3 and N4 are turned on, and when data is supplied to the bit line pair BL and BL /, the bit lines BL and BL are set to N3 and N4. The logic of the complementary relation given to / is given to and held at the connection point between P1 and N1 and the connection point between P2 and N2, respectively. When data is not applied to the bit line pair BL and BL /, P1 and N
The logic of the complementary relationship held at the connection point 1 and the connection points P2 and N2 is applied to the bit lines BL and BL /, respectively, and output. On the other hand, N3 and N4 insulate the bit line BL from the connection point between P1 and N1 because the N3 and N4 are turned off when the "L" level is given to the word line WL, and the bit line BL / And the connection point between P2 and N2.

N11 to N13 are connected to the bit lines BL and BL /
Respectively, do not match the logic held at the connection point between P1 and N1 and the connection point between P2 and N2, respectively, when N11 or N11 connected to the "H" level bit line BL or BL / Since N12 turns on, N11 and N1
The connection point of No. 2 becomes "H" level, N13 is turned on, and the match line MLA is set to "L" level. On the other hand, the logic applied to the bit lines BL and BL / is P1
And the logic level held at the connection point between P1 and N1 and the connection point between P2 and N2, the "L" level bit line BL
Alternatively, since N11 or N12 connected to BL / is turned on, if the connection point between N11 and N12 is "L" level and the match line MLA is given "H" level in advance, N13
Are kept off, and the match line MLA is kept at the “H” level. However, bit line pairs BL and B
When "L" level is given to both L /, N11
No matter which of N12 and N12 is turned on, the connection point between N11 and N12 is at the "L" level, so that N13 remains off and the match line MLA is maintained at the "H" level.

N21 to N23 also have the same functions as N11 to N13, except that search data line pairs RB and RB / to be connected and match line MLB are different. , And have the same functions as N11 to N13, except that the correspondingly connected search data line pairs RC and RC / and the match line MLC are different.

(A-2) Description of Operation Next, the operation of the associative memory cell of the first embodiment having the above-described configuration will be described with reference to FIG.

In P1, P2, N1 and N2, a connection point between P1 and N1 and a connection point between P2 and N2 are given.
The logics complementary to each other are held.

Here, when "H" level is applied to the word line WL, N3 and N4 are turned on. Therefore, when data is applied to the pair of bit lines BL and BL /, the bit lines BL and BL / , And the logic of the complementary relation given to P1 and N1 and the connection point between P2 and N2 are held respectively. On the other hand, bit line pairs BL and BL
When data is not applied to /, the logic held at the connection point between P1 and N1 and the connection point between P2 and N2 is applied to bit lines BL and BL /, respectively.

When the search data is applied to the bit line pair BL and BL / while the word line WL is at the "L" level, the logic applied to the bit lines BL and BL / is P1 and If the logic held at the connection point of N1 and the connection point of P2 and N2 does not match, the match line MLA becomes "
L "level. On the other hand, when the logic applied to the bit lines BL and BL / matches the logic held at the connection point between P1 and N1 and the connection point between P2 and N2, the match line MLA is previously set. Is "H" level, the match line ML is "H".
Retained at the level.

When the search data is applied to the search data line pair RB and RB / when the word line WL is at the "L" level, or when the search data line is at the "L" level when the word line WL is at the "L" level. When search data is given to the pair RC and RC /, the same operation is performed, although the corresponding match line MLB or MLC is different.

By such an operation, the bit line pair BL
And three types of search data given to BL /, search data line pairs RB and RB /, and search data line pairs RC and RC / respectively, match with the data held in P1, P2, N1 and N2. Can be searched at once, and these search results are used as match lines MLA, MLB, M
It will be output to each LC. However, in this embodiment, as described above, if each match line is at “H” level, it indicates a match, and if it is at “L” level, it indicates a mismatch.

In this embodiment, two pairs of search data lines (RB and RB / and RC and RC /) are shown. However, the number of pairs is not limited to two but may be n. Of course it is good. However, in this case, three N-channel MOS type FEs are provided for each of the additional search data line pairs.
T must be similarly connected and configured.

(A-3) Description of Effects As described above, according to the first embodiment, (1) two search data line pairs RB and RB /, RC and RC /,
(2) Searching whether or not the search data given to the two search data line pairs matches the data held at the connection points of P1 and N1 and the connection points of P2 and N2, respectively. Since N23 and N31 to N33 and (3) match lines MLB and MLC for outputting the search result are provided, three types of search data can be searched at once.

(B) Second Embodiment Hereinafter, a second embodiment of the content addressable memory cell according to the present invention will be described in detail with reference to the drawings.

(B-1) Description of Configuration FIG. 7 is a circuit diagram showing the configuration of the content addressable memory cell of the second embodiment. In FIG. 7, the associative memory cell includes P-channel MOSFETs P1 and P2 and N-channel MOSFETs N1 to N4, N41 to N44,
N51 to N54 and N61 to N64.

First, the connection relationship between the components will be described. The sources of P1 and P2 are connected to a power supply that supplies an “H” level, the sources of N1 and N2 are connected to ground that supplies an “L” level, the drain of P1 is connected to the drain of N1, and the drain of P2 Is connected to the drain of N2.

The connection point between P1 and N1 is connected to the drain of N3, and P2, N2, N42, N5
2 and N62. On the other hand, P2 and N
2 is connected to the drain of N4 and
1, N1, N41, N51 and N61 are connected to the gates.

Further, the gates of N3 and N4 are connected to the word line WL, the source of N3 is connected to the bit line BL, and the source of N4 is connected to the bit line BL /. Between the bit line pair BL and BL /, from the bit line BL side,
N43 gate and source, N41 drain and source, ground, N42 source and drain, N44
Between the search data line pair RB and RB /, between the search data line RB side, the gate and source of N53, the drain and source of N51, the ground, the source and drain of N52, and the source and drain of N54. The source and the gate are connected, and the search data line pair RC and RC /
Between the search data line RC side, the gate and source of N63, the drain and source of N61, ground,
The source and drain of N62 and the source and gate of N64 are connected.

Further, the drains of N43 and N44 are connected to match line MLA, the drains of N53 and N54 are connected to match line MLB, and the drains of N63 and N64 are connected to match line MLC.

Here, the function of each component connected in this way will be described. In FIG. 7, components corresponding to those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals. Therefore, the components are as described above, and the description is omitted. Hereinafter, components that do not correspond to the first embodiment will be described.

N41 to N44 are bit lines BL and BL /
If the logic given to the N1 does not match the logic held at the connection point of P1 and N1 and the logic held at the connection point of P2 and N2, respectively, N43 connected to N41 or N42 which is turned on.
Alternatively, N44 is supplied with the "H" level from the bit line BL or BL / to its gate to turn on, and set the match line MLA to "
L level. On the other hand, the bit lines BL and B
When the logic given to L / matches the logic held at the connection point of P1 and N1 and the connection point of P2 and N2, respectively, N43 or N44 connected to N41 or N42 to be turned on. , The gate of the bit line BL or BL / is supplied with the "L" level to turn off the gate. If the "H" level is supplied to the match line MLA in advance, the match line ML
A is maintained at "H" level. When "L" level is applied to both bit pairs BL and BL /, both N43 and N44 are turned off, so that match line MLA is maintained at "H" level.

N51 to N54 also have the same functions as N41 to N44, except that search data line pairs RB and RB / to be connected and match line MLB are different. , And have the same functions as N41 to N44, except that search data line pairs RC and RC / to be connected and match line MLC are different.

(B-2) Description of Operation Next, the operation of the associative memory cell of the second embodiment having the above-described configuration will be described with reference to FIG.

In P1, P2, N1 and N2, a connection point between P1 and N1 and a connection point between P2 and N2 are given.
The logics complementary to each other are held.

Here, when "H" level is applied to word line WL, N3 and N4 are turned on. Therefore, when data is applied to bit line pair BL and BL /, bit lines BL and BL / , And the logic of the complementary relation given to P1 and N1 and the connection point between P2 and N2 are held respectively. On the other hand, bit line pairs BL and BL
When data is not applied to /, the logic held at the connection point between P1 and N1 and the connection point between P2 and N2 is applied to bit lines BL and BL /, respectively.

When the search data is applied to the pair of bit lines BL and BL / while the word line WL is at the "L" level, the logic applied to the bit lines BL and BL / is P1 and If the logic held at the connection point of N1 and the connection point of P2 and N2 does not match, the match line MLA becomes "
L "level. On the other hand, when the logic applied to the bit lines BL and BL / matches the logic held at the connection point between P1 and N1 and the connection point between P2 and N2, the match line MLA is previously set. Is "H" level, the match line ML is "H".
Retained at the level.

When the search data is applied to the pair of search data lines RB and RB / when the word line WL is at the "L" level, or when the search data line is at the "L" level when the word line WL is at the "L" level. When search data is given to the pair RC and RC /, the same operation is performed, although the corresponding match line MLB or MLC is different.

By such an operation, the bit line pair BL
And three types of search data given to BL /, search data line pairs RB and RB /, and search data line pairs RC and RC / respectively, match with the data held in P1, P2, N1 and N2. Can be searched at once, and these search results are used as match lines MLA, MLB, M
It will be output to each LC. However, in this embodiment, as described above, if each match line is at “H” level, it indicates a match, and if it is at “L” level, it indicates a mismatch.

In this embodiment, two pairs of search data lines (RB and RB / and RC and RC /) are shown. However, the number of pairs is not limited to two but may be n. Of course it is good. However, in this case, three N-channel MOS type FEs are provided for each of the additional search data line pairs.
T must be similarly connected and configured.

(B-3) Description of Effects As described above, according to the second embodiment, N11 to N13, N21 to N23, and N31 to N33 of the first embodiment.
Instead of N41 to N44, N5
Since 1 to N54 and N61 to N64 are provided, effects similar to those of the first embodiment can be obtained with different connection configurations.

(C) Third Embodiment Hereinafter, a third embodiment of the content addressable memory cell according to the present invention will be described in detail with reference to the drawings.

(C-1) Description of Configuration FIG. 8 is a circuit diagram showing the configuration of the associative memory cell of the third embodiment. 8, the associative memory cell includes P-channel MOSFETs P1 and P2 and N-channel MOSFETs N1 to N4, N11 to N13,
N71, N72, N81 and N82.

First, the connection relationship between the components will be described. The sources of P1 and P2 are connected to a power supply that supplies an “H” level, the sources of N1 and N2 are connected to ground that supplies an “L” level, the drain of P1 is connected to the drain of N1, and the drain of P2 Is connected to the drain of N2.

The connection point between P1 and N1 is connected to the drain of N3 and to the gates of P2, N2 and N12. The connection point between P2 and N2 is connected to the drain of N4 and to the gates of P1, N1 and N11.

Further, the gates of N3 and N4 are connected to word line WL, the source of N3 is connected to bit line BL, and the source of N4 is connected to bit line BL /. Between the bit line pair BL and BL /, from the bit line BL side,
The source and drain of N11 and the drain and source of N12 are connected. Here, the connection point of N11 and N12 is connected to the gates of N13, N71 and N81.

Further, N13 has its drain connected to match line MLA and its source connected to ground. The drain and source of N71 and the drain and source of N72 are connected between the match line MLB and ground from the match line MLB side, and N81 is connected between the match line MLC and ground from the match line MLC side. And the drain and source of N82 are connected. The gate of N72 is connected to the mask setting signal line MB /, and the gate of N82 is connected to the mask setting signal line MC /.

Here, the functions of the components connected in this way will be described. In FIG. 8, components corresponding to those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals. Therefore, the components are as described above, and the description is omitted. Hereinafter, components that do not correspond to the first embodiment will be described.

N71 and N72 duplicately extract the logic (coincidence determination result) of the connection point of N11 and N12 and, based on the mask setting signal line MB / given mask setting information, extract the extracted logic (coincidence determination). Output) or output stop. That is, N11 and N1
2 is at "H" level and the mask setting signal line MB
When / is at the "H" level, both N71 and N72 are turned on, and the match line MLB is brought to the "L" level.
When the connection point between N11 and N12 is at the “L” level and / or the mask setting signal line MB / is at the “L” level,
N71 and / or 72 are turned off, and the match line MLB is
If the “H” level is given, the match line MLB is set to “H”.
It keeps the level.

Incidentally, N81 and N82 are also different from N71 and N82 except that the corresponding connected mask setting signal line MC / is different.
It has the same function as 72.

(C-2) Description of Operation Next, the operation of the associative memory cell of the third embodiment having the above-described configuration will be described with reference to FIG. I do.

Information as to whether the search data given to the bit line pairs BL and BL / is to be searched (to be taken care of) or excluded from the search (to be masked) is determined by mask setting signal lines MB / and MC /. And given to. In this embodiment, the "H" level is set when care is performed, and the "H" level is set when masking is performed.
L "level.

Here, when search data is applied to bit line pair BL and BL / while word line WL is at the "L" level, the logic applied to bit lines BL and BL / is P1. When the logic does not match the logic held at the connection point between the nodes N1 and N1 and the connection point between P2 and N2, the match line MLA
When the mask setting signal line MB / is at the "L" level, the match line MLB is maintained at the "H" level because the N72 is in the off state, that is, the bit line pair BL. Even if the data applied to bit line BL and BL / do not match, match line MLB is maintained at the "H" level, so that the data applied to bit line pair BL and BL / is excluded from the search target. (Masked).

Similarly, the mask setting signal MC / is also "L".
If it is at the level, N82 is also in the off state, so that the match line MLC is also kept at the “H” level, that is, excluded from the search target.

In this embodiment, two mask setting signal lines (MB / and MC /) are shown. However, the number of mask setting signal lines is not limited to two and may be n. However, in this case, it is necessary to similarly connect and configure two N-channel MOSFETs to each of the additional search data line pairs.

(C-3) Description of Effects As described above, according to the third embodiment, (1) two mask setting signal lines MB / and MC /, and (2) two masks N71 and N72, N81 and N82 for masking the search data given to the bit line pair BL and BL / based on the mask setting information given to the setting signal line;
(3) Match line ML that outputs the masked search result
With B and MLC, a detection result based on two types of mask setting information can be obtained at once.

(D) Fourth Embodiment Hereinafter, a fourth embodiment of the content addressable memory cell according to the present invention will be described in detail with reference to the drawings.

FIG. 9 is a circuit diagram showing the configuration of the associative memory cell of the fourth embodiment. In FIG. 9, this associative memory cell is composed of P-channel MOSFETs P1 and P1.
2 and N-channel MOS FETs N1 to N4, N1
1, N12, N71, N72, N81, N82, N91
And N92.

The connection relationship between the components of this embodiment is the same as that of the third embodiment except that N13 is removed and the drain of N91 is connected between the match line MLA and the ground from the match line MLA side. N92, the drain and source of N92 are connected, the gate of N91 is connected to the connection point of N11 and N12,
Are connected to the mask setting signal line MA /.

In FIG. 9, components corresponding to those of the third embodiment shown in FIG. 8 are denoted by the same reference numerals. Therefore, the components are as described above, and the description is omitted. Hereinafter, N91 and N92 that do not correspond to the third embodiment will be described.

N91 and N92 indicate that the connection point between N11 and N12 is at "H" level and the mask setting signal line MB /
Is at the "H" level, both N91 and N92 are turned on to bring the match line MLA to the "L" level. When the connection point between N11 and N12 is at the “L” level and / or the mask setting signal line MB / is at the “L” level,
N91 and / or 92 are turned off and the match line MLB is
If the “H” level is given, the match line MLB is set to “H”.
It keeps the level.

Next, the operation of the associative memory cell according to the fourth embodiment having the above-described configuration will be described briefly with reference to FIG. 9, focusing on the differences from the third embodiment.

In the associative memory cell of this embodiment, it is possible to further set whether to care or mask the match line MLA.

That is, the mask setting information of whether to care or mask the match line MLA (however, in this embodiment, "H" level for care, "L" level for mask) By applying the data to the setting signal line MA /, the search data applied to the bit line pair BL and BL / is care or masked.

As described above, according to the fourth embodiment,
In the third embodiment, (1) N13 is removed, and based on (2) the mask setting signal line MA / and (3) the mask setting information given to this mask setting signal line MA /, the bit line pair The search data given to BL and BL / is excluded from search targets, and the detection result is set to match line MLA.
N91 and N92 output to the
The masked detection result can also be output to LA.

For example, match lines MLA, MLB, MLC
In the third embodiment, the detection result of the match line MLA is a basic pattern that is not masked at all and has the highest priority in the third embodiment. In the embodiment, all the match lines ML
A to MLC for mask setting signal lines MA /, MB /,
Since the mask can be arbitrarily set by MC /, it is possible to arbitrarily set which match line is to be output with which priority.

(E) Fifth Embodiment Hereinafter, a fifth embodiment of the content addressable memory cell according to the present invention will be described in detail with reference to the drawings.

FIG. 10 is a circuit diagram showing the configuration of the associative memory cell of the fifth embodiment. In FIG. 10, the associative memory cell includes P-channel MOSFETs P1 and P2 and N-channel MOSFETs N1 to N4, N
11 to N13, N31 to N33, N71, and N72.

The associative memory cell of the fifth embodiment is
It has a configuration in which the first and third embodiments are partially combined. Accordingly, the components and their connection relationships are as described in the first and third embodiments, and the description thereof will be omitted. In FIG. 10, components corresponding to those in the first and third embodiments shown in FIGS. 1 and 8 are denoted by the same reference numerals.

Therefore, the operation of the associative memory cell of the fifth embodiment will be described only briefly.

It is searched for whether or not the search data given to bit line pairs BL and BL / and search data line pairs RC and RC / respectively match the held data, and the match is made to match lines MLA and MLC. Is output.

On the other hand, the mask setting signal line MB / is provided with mask setting information of whether to care or mask the search data given to the bit line pair BL and BL /, and the match line MLB is provided with the mask setting information. A search result based on the setting information is output.

As described above, according to the fifth embodiment,
The same effects as those of the first and third embodiments can be obtained, and a search result obtained by arbitrarily masking a part of a plurality of search data can be obtained by one search.

(F) Sixth Embodiment Hereinafter, a sixth embodiment of the content addressable memory cell according to the present invention will be described in detail with reference to the drawings.

FIG. 11 is a circuit diagram showing the configuration of the content addressable memory cell according to the sixth embodiment. In FIG. 10, the associative memory cell includes P-channel MOSFETs P1 and P2 and N-channel MOSFETs N1 to N4, N
11, N12, N31 to N33, N61 to N64, N7
1, N72, N91 and N92.

The associative memory cell of the sixth embodiment is
It has a configuration in which the second and fourth embodiments are partially combined. Accordingly, the components and their connection relations are as described in the second and fourth embodiments, and description thereof will be omitted. In FIG. 11, components corresponding to those in the second and fourth embodiments shown in FIGS. 7 and 9 are denoted by the same reference numerals.

Therefore, the operation of the content addressable memory cell according to the sixth embodiment will be described only briefly.

It is searched whether or not the search data applied to bit line pairs BL and BL / and search data line pairs RC and RC / respectively match the held data, and match data is output to match lines MLA and MLC. Is output.

On the other hand, mask setting information of whether to care or mask the signal applied to bit line pair BL and BL / is applied to mask setting signal lines MA / and MB /, respectively, and match lines MLA and MLB are provided. Output search results based on the mask setting information.

As described above, according to the sixth embodiment,
The same effects as those of the second and fourth embodiments can be obtained, and a search result obtained by arbitrarily masking all of the plurality of search data can be obtained by one search.

(G) Seventh Embodiment Hereinafter, a seventh embodiment of the content addressable memory cell and the content addressable memory according to the present invention will be described in detail with reference to the drawings.

(G-1) Description of Configuration FIG. 12 is a circuit diagram showing the configuration of the content addressable memory according to the seventh embodiment. In FIG. 12, this associative memory is m
The first to sixth embodiments, which are addressed in a matrix by +1 word lines WL [0 to m] and n + 1 pairs of bit lines BL [0 to n] and BL / [0 to n]. It is composed of (m + 1) * (n + 1) associative memory cells [00-mn] described in any of the embodiments. Further, in this embodiment, the peripheral circuit includes functional blocks PA to PC each including a priority encoder, a multiple match detection circuit, and a mismatch detection circuit. In FIG. 11,
Notationally, three bit line pairs BL [0-2] and BL /
Only the components of [0-2] and the four word lines WL [0-3] are shown.

First, the connection relationship between the components will be described. Word line [a] and bit line pair BL [b] and BL
/ [B] is connected to the associative memory cell [ab]. The match line M of the associative memory cell [a0-an]
The LAs are all connected to a match line MLA [a], the match lines MLB are all connected to a match line MLB [a], and the match lines MLC are all connected to a match line MLC [a]. However, a is any integer from 0 to m, and b is 0 to
n is an arbitrary integer, and is used similarly in the following.

The match lines MLA [0-m] are connected to the function block PA, the match lines MLB [0-m] are connected to the function block PB, and the match lines MLC [0-m].
Is connected to the function block PC.

Next, the functions of the components connected as described above will be described.

The associative memory includes a pair of bit lines BL [0 to n].
And a data string given to BL / [0-n] to an associative memory cell [a0] connected to an arbitrary word line WL [a].
~ An], and conversely, any word line WL
The data string held in the associative memory cell [a0-an] of [a] is converted into the bit line pair BL [0-n] and BL / [0-
n]. Further, in this associative memory, a search data string given to a bit line pair [0 to n] and BL / [0 to n] is held in an associative memory cell [a0 to an] of an arbitrary word line [a]. Whether or not it matches the data string searched, based on a plurality of search data strings and a plurality of mask setting information as described in each embodiment,
The search results are sorted by match line MLA for each priority.
[0-m] and match line MLB [0-m] and match line ML
C [0-m].

The function block PA includes a match line MLA [0
To m], a function of outputting the address of the matched data in binary to the detection signal line AA based on the search result given from the search signal line MMA.
, The detection signal line NMA
It has the function of outputting to

Note that the function block PB also has the match lines MLB [0-m] and the detection signal lines AB, MMB,
Except for the NMB, the function block PA has the same function as that of the function block PA. The function block PC also has corresponding match lines MLC [0 to m] and detection signal lines AC and MM.
It has the same function as the functional block PA except that C and NMC are different.

That is, in this embodiment, the functional blocks PA to PC are provided for each priority of the detection signal output from the associative memory.

(G-2) Description of Operation Next, the operation of the content addressable memory according to the seventh embodiment having the above-described configuration will be described with reference to FIG.

The associative memory cells [00-mn] hold complementary logic.

Here, any one word line WL [a]
Is given an "H" level and the other is given an "L" level.
When a data string is given to bit line pair BL [0-n] and BL / [0-n], the complementary relationship given to bit lines BL [0-n] and BL / [0-n] is obtained. The logic is held in each of the associative memory cells [a0 to an]. On the other hand, when a data string is not applied to bit line pair BL [0-n] and BL / [0-n], associative memory cell [a
0 to an] are stored in the bit line B
L [0-n] and BL / [0-n] to output a data string.

Further, all the word lines WL [0-m] are "L".
In the level state, the bit line pairs BL [0 to n] and BL /
When a search data string is given to [0 to n], a logical string given to bit lines BL [0 to n] and BL / [0 to n] is changed to an associative memory cell [ a0-a
n] is searched based on a plurality of pieces of search data and a plurality of pieces of mask setting information.
A [0-m], MLB [0-m] and MLC [0-m] are output.

In the function block PA, the match line MLA
Based on the search result given from [0 to m], if there is no match, a mismatch signal is output to the detection signal line NMA, and if multiple matches occur at the same time, a multiple match signal is output to the detection signal line MMA. You. If they match, the address holding the matching complementary signal is output to the detection signal line AA. However, if there are two or more matching data at the same time, one of the addresses is output according to a predetermined rule.

In the functional block PB, the match lines MLB [0 to m] and the detection signal lines AB and MM are connected.
Except for the difference between B and NMB, the same operation as that of the functional block PA is performed. In the functional block PC, the correspondingly connected match lines MLC [0 to m] and the detection signal lines AC and MM are connected.
The same operation as that of the functional block PA is performed except that C and NMC are different.

With such an operation, the associative memory constituted by the associative memory cells described in the above embodiments can simultaneously output search results by priority according to a plurality of search data strings and a plurality of mask setting information. Can be smoothly processed in the peripheral circuit (e.g., whether a matching data string has been registered, at which address it has been registered, or at two or more addresses if registered). become.

In this embodiment, the search signals from the associative memory have three priority levels. However, the priority order is not limited to three and may be n. However,
In this case, for each additional configured priority,
It is necessary to connect and configure the functional blocks in the same manner.

(G-3) Description of Effect As described above, according to the seventh embodiment, (1) m + 1
Word lines WL [0-m] and n + 1 bit line pairs B
(M + 1) * (n + 1) associative memories according to any of the first to sixth embodiments, addressed in a matrix with L [0 to n] and BL / [0 to n] Based on the associative memory composed of cells [00-mn] and (2) priority levels of detection results output from the associative memory, based on the given detection results of the same priority,
Outputs the address that holds the matched data,
Since it has the functional blocks PA to PC for detecting whether multiple matches or not all match or not, the associative memory constituted by the associative memory cells described in each of the above embodiments can be used for a plurality of search data strings and a plurality of Based on the mask setting information, the peripheral circuit can smoothly process the search results simultaneously output according to the priority order.

(H) Eighth Embodiment Hereinafter, an eighth embodiment of the content addressable memory cell and the content addressable memory according to the present invention will be described in detail with reference to the drawings.

In the seventh embodiment, the function blocks PA to PC are provided for each of the priorities of the search results outputted from the associative memory. Only the search result with the highest priority among the search results is detected, and it is not necessary to perform processing for all the priority orders. That is, in the eighth embodiment, there is provided a means for selecting only a search result having the highest priority among search results in which a match is detected, and a function block for the selected search result (however, in this embodiment,
(Shown separately in a priority encoder and a coincidence pattern detection circuit).

(H-1) Description of Configuration FIG. 13 is a circuit diagram showing the configuration of the content addressable memory according to the eighth embodiment. In FIG. 13, this associative memory is not shown, as in the seventh embodiment.
(M + 1) * (n + 1) associative memory cells according to any of the first to sixth embodiments, addressed in a matrix by +1 word lines and n + 1 bit line pairs [ 00 to mn]. Further, in this embodiment, the mismatch detection circuits NDA to ND are used as peripheral circuits.
C, m + 1 selectors S0 to Sm, a priority encoder PE, and a matching pattern detection circuit MPC. In FIG. 13, only the configuration of the match line portions corresponding to the four word lines [0 to 3] is shown.

First, the connection relationship between the components will be described. The associative memory is the same as in the seventh embodiment. Match line MLA [0-m] of the associative memory
Are respectively connected to the selectors S0 through the mismatch detection circuit NDA.
To Sm, match lines MLB [0 to m] are connected to selectors S0 to Sm via a mismatch detection circuit NDB, and match lines MLC [0 to m] are connected to selectors S0 via a mismatch detection circuit NDC, respectively. To Sm. The detection signal lines NMA to NMC of the mismatch detection circuits NDA to NDC are connected to the selectors S0 to Sm and the match pattern detection circuit MPC. Further, the selector S0
To Sm are connected to the priority encoder PE.

Next, the functions of the components connected as described above will be described. The associative memory is the same as in the seventh embodiment, and a description thereof will be omitted.

The mismatch detection circuit NDA is provided with a match line MLA.
Based on the search results given from [0 to m], if all do not match, a mismatch is detected, and a mismatch detection signal is output to the detection signal line NMA. Note that the mismatch detection circuits NDB and NDC also have corresponding match lines MLB [0 to MLB [0].
m] and MLC [0 to m] and detection signal lines NMB and NM
It is similar to the mismatch circuit NDA except that C is different.

The selectors S0 to Sm are provided with a mismatch detection circuit N
Based on the inconsistency detection signals output by DA to NDC, among the search results output from the associative memory, the search result having the highest priority among those having detected a match is selected, and only the selected search result is given priority. This is given to the encoder.

The priority encoder PE outputs the address of the matched data in binary to the detection signal line A0 based on the search result selected by the selectors S0 to Sm. Here, if there are two or more coincident data at the same time, one of the addresses is output according to a predetermined rule.

The match pattern detection circuit MPO outputs a binary code indicating the priority of the detection result output to the priority encoder PE to the detection signal line MP based on the mismatch detection signals output from the mismatch detection circuits NDA to NDC. Things.

(H-2) Description of Operation Next, the operation of the associative memory according to the eighth embodiment having the above-described configuration will be described with reference to FIG. 13, focusing on differences from the seventh embodiment. I do.

In the associative memory, whether a given search data string matches a data string held in an associative memory cell of an arbitrary word line is determined based on a plurality of search data and a plurality of mask setting information. The search results are searched, and the match lines MLA [0-m] and MLB are
[0-m] and MLC [0-m]. In this embodiment, the search result output to the match line MLA [0 to m] has the highest priority, and thereafter, the match line ML
It is assumed that B [0 to m] and MLC [0 to m] decrease in this order.

In the mismatch detection circuit NDA, the match line ML
Based on the search results given from A [0 to m], if all do not match, a mismatch is detected, and a mismatch detection signal is output to the detection signal line NMA. In this embodiment, when a mismatch is detected, "H" is applied to the detection signal line NMA.
When a match of one or more levels is detected, an “L” level is output to the detection signal line NMA. Also, in the mismatch detection circuits NDB and NDC, the mismatch detection signals are similarly output to the detection signal lines NMB and NMC for the match lines MLB [0 to m] and MLC [0 to m].

Here, in the selectors S0 to Sm, based on the inconsistency detection signals output from the inconsistency detection circuits NDA to NDC, among the search results output from the associative memory, those having the highest priority among those which have detected a match. Higher search results are selected and only the selected search results are provided to the priority encoder.

In the priority encoder PE, the address of the matched data is output in binary to the detection signal line A0 based on the search result selected by the selectors S0 to Sm. In the matched pattern detection circuit MPO, the non-match detection circuits NDA to NDC are output. , Based on the mismatch detection signals respectively output from the detection signal line M, the binary code indicating the priority order of the detection results output to the priority encoder PE.
Output to P.

FIG. 14 is a circuit diagram showing a detailed configuration of any one of the selectors S0 to Sn. FIG. 15 is a diagram showing the logic of the select signal generated by the detailed configuration and the output from the coincidence pattern detection circuit MPO. It shows the binary code. It should be noted that in FIG.
The “H” level is indicated as “1” and the “L” level is indicated as “0.” “X” indicates a case where either the “H” level or the “L” level is acceptable.

In FIG. 14, the selector has transfer gates N201 to N203 and a select signal generator (not shown).

In the select signal generation section, based on the mismatch detection signals output from the mismatch detection circuits NDA to NDC, the select signal S is provided so as to satisfy the logic shown in FIG.
A to SC are generated, and transfer gates N201 to N201 are generated.
N203.

On the other hand, transfer gates N201 to N2
At 03, when the applied select signal is at the "H" level, the terminals are made conductive, while when the applied select signal is at the "L" level, the terminals are not made conductive.

That is, if the mismatch detection circuit NDA does not detect a mismatch ("L" level) due to such an operation, that is, if a match exists in the search result with the highest priority, the other mismatch detection circuit NDB And the detection of NDC, the transfer gate N201 becomes conductive, the match lines MLA [a] and ML [a] become conductive, and the match line M
The search result output from LA [0-m] is given to the priority encoder PE.

When the mismatch detection circuit NDA detects a mismatch ("H" level) and the mismatch detection circuit NDB does not detect a mismatch ("L" level), that is, the search result matches the search result with the highest priority. Does not exist, and there is a match in the search result with the next highest priority, the transfer gate N202 becomes conductive regardless of the detection of the mismatch detection circuit NDC, and the match lines MLB [a] and ML [a] are Conducts,
The search results output from the match lines MLB [0 to m] are given to the priority encoder PE.

Further, the mismatch detecting circuit NDA detects mismatch ("H" level), the mismatch detecting circuit NDB detects mismatch ("H" level), and the mismatch detecting circuit NDC does not detect mismatch ("L"). Level), that is, if there is no match in the search results of the top two priorities and there is a match in the search result of the lowest priority, the transfer gate N203 becomes conductive and the match line MLC [a ] And ML [a] are conducted, and the search result output from the match line MLC [0-m] is given to the priority encoder PE.

Further, all the non-coincidence detecting circuits NDA
If NDC detects a mismatch ("H" level), no search result is given to the priority encoder PE.

In this embodiment, three priority levels are shown as in the seventh embodiment. However, it is needless to say that the priority order is not limited to three and may be n. . However, in this case, it is necessary to similarly connect and configure the functional blocks for each of the added priorities.

(H-3) Description of Effects As described above, according to the eighth embodiment, (1) based on the search result output from the associative memory, if all of the priorities do not match each other, they do not match. And a mismatch detection circuit NDA to NDC for detecting mismatch and outputting a mismatch detection signal;
(2) Based on the inconsistency detection signals output by the inconsistency detection circuits NDA to NDC, only the search result with the highest priority among the results of the match detection from the associative memory, in which the match is detected, is selected. Selector S0
ＳSm, a plurality of functional blocks provided for each priority in the seventh embodiment can be realized by one, and the amount of hardware such as transistors can be significantly reduced.

(I) Other Embodiments The associative memory cell or the associative memory described in each of the above embodiments is not limited to a device for performing an exchange process in units of messages, but can be applied to other similar devices. Of course.

In the seventh embodiment, the function blocks PA to P having the functions of a priority encoder, a multiple match detection circuit and a mismatch detection circuit are provided as peripheral circuits.
Although C is shown, the functional blocks PA to PC may have some of these functions or may have functions other than these.

Further, instead of the priority encoder PE shown in the eighth embodiment, a multiple coincidence detecting circuit may be applied, or a circuit having another function may be applied.

Furthermore, in the third to sixth embodiments, a plurality of matching results are extracted, and each of the extracted matching results is output or stopped based on the mask setting information. The present invention can be applied to only a component for extracting a plurality of results of the coincidence determination.

[0142]

As described above, according to the first aspect of the present invention,
In an associative memory cell having a memory cell and a matching unit for determining whether data held in the memory cell matches the search data, the associative memory cell has a plurality of matching units provided with different search data. On the other hand, the match with the data held in the memory cell can be determined by one search.

According to the second aspect of the present invention, there is provided an associative memory cell having a memory cell and a collating means for judging and outputting coincidence between the data held in the memory cell and the retrieval data. Has one or more extracting means for redundantly extracting the determination result, and based on the mask setting information, each extracting means outputs or suspends the determination result of the matching means extracted redundantly. A match between the data held in the memory cell and the search data based on a plurality of mask setting information can be determined by one search.

Further, according to the associative memory of the third aspect of the present invention, the plurality of associative memory cells of the first or second aspect of the present invention, which are addressed in a matrix by a plurality of word lines and a plurality of bit line pairs. Since the match determination signal output from each associative memory cell is output to a plurality of match lines provided corresponding to a plurality of word lines for each search data column and / or for each mask setting information column, a plurality of A match between the data held in the memory cell and the data held in the memory cell can be determined by a single search for the search data string, or the match between the data held in the memory cell and the search data based on a plurality of pieces of mask setting information. Can be determined by one search.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of an associative memory cell according to a first embodiment.

FIG. 2 is a circuit diagram showing a configuration of a conventional associative memory cell.

FIG. 3 is a circuit diagram showing a configuration of a conventional associative memory cell.

FIG. 4 is a block diagram showing a configuration of a conventional associative memory.

FIG. 5 is an operation explanatory diagram of a conventional address translation device to which an associative memory is applied.

FIG. 6 is an explanatory diagram of a second search method of the address translator.

FIG. 7 is a circuit diagram illustrating a configuration of an associative memory cell according to a second embodiment;

FIG. 8 is a circuit diagram illustrating a configuration of an associative memory cell according to a third embodiment.

FIG. 9 is a circuit diagram illustrating a configuration of an associative memory cell according to a fourth embodiment.

FIG. 10 is a circuit diagram illustrating a configuration of an associative memory cell according to a fifth embodiment.

FIG. 11 is a circuit diagram illustrating a configuration of an associative memory cell according to a sixth embodiment.

FIG. 12 is a block diagram illustrating a configuration of an associative memory according to a seventh embodiment.

FIG. 13 is a block diagram illustrating a configuration of an associative memory according to an eighth embodiment.

FIG. 14 is a circuit diagram illustrating a detailed configuration of a selector according to an eighth embodiment.

FIG. 15 is an operation explanatory diagram of the selector and the coincidence pattern detection circuit according to the eighth embodiment.

[Explanation of symbols]

PB and PB /, PC and PC / ... search data line pair, P
1, P2 ... P-channel MOS type FET, N1, N2, N
21 to N23, N31 to N33 ... N channel MOS type F
ET.

Claims (8)

[Claims] 1. An associative memory cell having a memory cell and matching means for determining whether data held in the memory cell matches search data, wherein the associative memory cell includes a plurality of matching means to which different search data is given. 2. An associative memory cell, comprising: 2. An associative memory cell, comprising: a memory cell; and a collating means for judging and outputting coincidence between the data held in the memory cell and the search data. An associative memory cell comprising one or more extracting means for extracting. 3. An associative memory cell, comprising: a memory cell; and collating means for judging coincidence between data held in the memory cell and retrieval data, wherein a plurality of the collating means to which different retrieval data are given; 1 is provided corresponding to each matching means, and the determination result of the corresponding matching means is extracted redundantly.
An associative memory cell, comprising: the above extracting means. 4. The associating method according to claim 2, wherein each of the extracting units outputs or stops the determination result of the matching unit extracted in duplicate, based on the mask setting information. Memory cells. 5. The associative memory cell according to claim 2, wherein said collating means outputs or suspends output of the judgment result of the own means based on the mask setting information. 6. A plurality of associative memory cells according to claim 1, which are addressed in a matrix by a plurality of word lines and a plurality of bit line pairs. A match determination signal is output to a plurality of match lines provided corresponding to the plurality of word lines, for each search data string and / or for each mask setting information string. 7. The associative memory according to claim 6, wherein the associative memory is provided for each priority of a match determination signal output for each search data sequence and / or for each mask setting information sequence, and is provided with the same priority given to its own means. Associating means comprising a plurality of coincidence determination signal processing means for detecting a multiple match, detecting a mismatch, or outputting one predetermined address among addresses holding data for which a match has been detected, based on the determination signal. memory. 8. The associative memory according to claim 6, wherein said associative memory is provided for each priority of a match determination signal output for each search data sequence and / or for each mask setting information sequence, and provided with the same priority given to its own means. A plurality of non-coincidence detecting means for detecting a non-coincidence based on the judgment signal; a selecting means for selecting a coordination judging signal having the highest priority among the priorities in which the non-coincidence detecting means does not detect a non-coincidence; Based on the determined match determination signal, a match determination signal processing means for detecting a multiple match, detecting a mismatch, or outputting one predetermined address among the addresses holding the data for which a match has been detected. Associative memory.