JP2000022314A - Method of mounting electronic components - Google Patents

Method of mounting electronic components

Info

Publication number
JP2000022314A
JP2000022314A JP10190453A JP19045398A JP2000022314A JP 2000022314 A JP2000022314 A JP 2000022314A JP 10190453 A JP10190453 A JP 10190453A JP 19045398 A JP19045398 A JP 19045398A JP 2000022314 A JP2000022314 A JP 2000022314A
Authority
JP
Japan
Prior art keywords
mounting
circuit board
adhesive
conductive adhesive
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10190453A
Other languages
Japanese (ja)
Inventor
Yuji Otani
祐司 大谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP10190453A priority Critical patent/JP2000022314A/en
Publication of JP2000022314A publication Critical patent/JP2000022314A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Screen Printers (AREA)
  • Printing Plates And Materials Therefor (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method of mounting electronic components whereby the cobwebbing of an adhesive can be prevented and troubles due to the cobwebbing can be effectively avoided in mounting the electronic components on a circuit board. SOLUTION: In a step of coating a conductive adhesive 14 on conductor lands 12 of a circuit board 11, the conductive adhesive 14 is coated, without causing the cobwebbing, using a mask 15 having a fluoro-resin 19 covering the inside faces of openings 17 to a plane facing the circuit board 11. In mounting, an IC chip 13 is adhered onto the conductive adhesive 14, without reducing the adhesion area, thereby avoiding lowering the mechanical connection strength between the IC chip 13 and circuit board 11 to avoid lowering the product quality.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、回路基板上の所定
の実装領域に電子部品をマスク印刷により塗布された接
着剤で実装する電子部品の実装方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting an electronic component on a predetermined mounting area on a circuit board with an adhesive applied by mask printing.

【0002】[0002]

【発明が解決しようとする課題】近年、回路基板上の実
装領域にマスク印刷により接着剤を塗布し、その接着剤
が塗布された実装領域に電子部品を搭載することによっ
て、回路基板上に電子部品を実装する実装方法が考えら
れている。ところで、この場合、マスク印刷におけるマ
スクとしてメタルマスクを使用する場合、次のような問
題が発生する虞がある。
In recent years, an adhesive has been applied to a mounting area on a circuit board by mask printing, and an electronic component has been mounted on the mounting area on which the adhesive has been applied. A mounting method for mounting components has been considered. By the way, in this case, when a metal mask is used as a mask in mask printing, the following problem may occur.

【0003】すなわち、図6に示すように、回路基板1
上の所定位置にメタルマスク2を配置し、メタルマスク
2に形成された開口部3から接着剤を印刷することによ
って、回路基板1上に接着剤4(図6中、斜線を付して
示している)を塗布し(図6中、(a)参照)、次い
で、メタルマスク2を上記所定位置から上方に移動する
と(図6中、(b)参照)、接着剤4の主成分であるエ
ポキシ樹脂とメタルマスク2の材質であるステンレスと
の間の表面濡れ性が良いことや、接着剤4の自己凝集性
が大きいことに起因して、糸ひき現象が発生し、接着剤
4の厚さにばらつきが生じるという虞がある。
[0003] That is, as shown in FIG.
The metal mask 2 is arranged at a predetermined position on the upper side, and the adhesive is printed from the opening 3 formed in the metal mask 2 so that the adhesive 4 is formed on the circuit board 1 (shown by hatching in FIG. 6). Is applied (see (a) in FIG. 6), and then the metal mask 2 is moved upward from the predetermined position (see (b) in FIG. 6). Due to the good surface wettability between the epoxy resin and the stainless steel that is the material of the metal mask 2 and the large self-cohesiveness of the adhesive 4, stringing occurs and the thickness of the adhesive 4 is reduced. There is a risk that the variation will occur.

【0004】そして、このような糸引き現象が発生した
状態で接着剤4が硬化してしまうと(図6中、(c)参
照)、場合によっては、電子部品(図示せず)を接着剤
4上に搭載できなくなったり、仮に電子部品を接着剤4
上に搭載できたとしても、接着面積が小さくなってしま
うことから、電子部品と回路基板1との間の機械的な接
続強度が低下し、製品の品質が低下するという虞があ
る。
When the adhesive 4 hardens in a state where such a stringing phenomenon has occurred (see (c) in FIG. 6), an electronic component (not shown) may be attached to the adhesive in some cases. 4 cannot be mounted on it, or if the
Even if it can be mounted on the electronic component, the bonding area is reduced, so that the mechanical connection strength between the electronic component and the circuit board 1 is reduced, and the quality of the product may be reduced.

【0005】また、図7に示すように、接着剤として導
電性接着剤を使用し、回路基板1上に設けられた導体ラ
ンド5上に導電性接着剤6を塗布した場合に、上述した
ような糸引き現象が発生してしまうと、場合によって
は、導電性接着剤6が糸引き現象によって連結してしま
う可能性があり、そうなると、電子部品7と回路基板1
との間の機械的な接続強度が低下するだけでなく、導体
ランド5間などで短絡が生じるという虞もある。
Further, as shown in FIG. 7, when a conductive adhesive is used as an adhesive and a conductive adhesive 6 is applied on a conductive land 5 provided on the circuit board 1, as described above. If the stringing phenomenon occurs, the conductive adhesive 6 may be connected by the stringing phenomenon in some cases, and if so, the electronic component 7 and the circuit board 1 may be connected.
Not only does the mechanical connection strength between the conductor lands 5 decrease, but also a short circuit may occur between the conductor lands 5 and the like.

【0006】本発明は、上記した事情に鑑みてなされた
ものであり、その目的は、回路基板上に電子部品を接着
剤で実装するにあたって、接着剤の糸引き現象の発生を
未然に防止でき、その糸引き現象に起因した不具合の発
生を効果的に防止できる電子部品の実装方法を提供する
ことにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent the occurrence of a stringing phenomenon of an adhesive when mounting an electronic component on a circuit board with the adhesive. It is another object of the present invention to provide a method of mounting an electronic component, which can effectively prevent the occurrence of a defect caused by the stringing phenomenon.

【0007】[0007]

【課題を解決するための手段】請求項1に記載した電子
部品の実装方法によれば、まず、接着剤を実装領域に塗
布する塗布工程が行われる。このとき、この塗布工程で
使用するマスクは、少なくとも開口部の内周面から回路
基板側の面にかかる所定部位が接着剤との表面濡れ性の
低い樹脂により覆われているので、例えば、回路基板上
の所定位置にマスクを配置し、接着剤を開口部から印刷
して実装領域に塗布したのち、マスクを上記所定位置か
ら上方に移動したときに、糸ひき現象が発生することが
なく、接着剤の厚さにばらつきが生じることもない。
According to the electronic component mounting method of the present invention, first, an application step of applying an adhesive to a mounting area is performed. At this time, the mask used in this coating step has at least a predetermined portion extending from the inner peripheral surface of the opening to the surface on the circuit board side covered with a resin having low surface wettability with an adhesive. After placing the mask at a predetermined position on the substrate, printing the adhesive from the opening and applying it to the mounting area, when the mask is moved upward from the predetermined position, the threading phenomenon does not occur, There is no variation in the thickness of the adhesive.

【0008】次いで、この塗布工程が行われたのちに、
電子部品を実装領域に搭載する搭載工程が行われる。こ
のとき、上述した塗布工程が行われたことによって、接
着剤は、糸引き現象が生じることなく塗布されているの
で、接着面積が小さくなることもなく、これによって、
電子部品と回路基板との間の機械的な接続強度が低下す
ることを防止でき、製品の品質が低下することを防止で
きる。
Next, after this coating step is performed,
A mounting process for mounting the electronic component in the mounting area is performed. At this time, by performing the above-described application step, the adhesive is applied without causing the stringing phenomenon, so that the bonding area does not decrease, and
A reduction in mechanical connection strength between the electronic component and the circuit board can be prevented, and a reduction in product quality can be prevented.

【0009】請求項2に記載した電子部品の実装方法に
よれば、樹脂をフッ素樹脂にしたので、フッ素樹脂が汎
用性の高い樹脂であることから、容易に入手および取扱
うことができ、また、フッ素樹脂を所定部位に設けるに
あたって、例えば印刷、含浸法、スピンコート法などの
周知の方法を適用することができる。
According to the electronic component mounting method of the present invention, since the resin is made of fluororesin, the fluororesin is a highly versatile resin, so that it can be easily obtained and handled. In providing the fluororesin at a predetermined site, a known method such as printing, impregnation, and spin coating can be applied.

【0010】請求項3に記載した電子部品の実装方法に
よれば、接着剤を導電性にしたので、電子部品と回路基
板とを機械的に接続することに加えて、それらを電気的
に接続することもでき、しかも、その場合には、上述し
たように糸引き現象が発生することがないので、導電性
接着剤が塗布される導体ランド間などで、短絡が生じる
ことを防止できる。
According to the electronic component mounting method of the present invention, since the adhesive is made conductive, the electronic component and the circuit board are electrically connected in addition to the mechanical connection. In this case, since the stringing phenomenon does not occur as described above, it is possible to prevent a short circuit from occurring between conductor lands to which the conductive adhesive is applied.

【0011】[0011]

【発明の実施の形態】以下、本発明の一実施例について
図1ないし図5を参照して説明する。まず、図2には、
本実施例によって得られた電子部品の実装形態を模式的
に示している。図2において、回路基板11は、セラミ
ック基板上にCu厚膜ペースト材料が印刷・焼成されて
形成されたもので、その所定部位には導体ランド(本発
明でいう実装領域)12が設けられている。そして、I
Cチップ(本発明でいう電子部品)13は、導電性接着
剤14(図2中、斜線を付して示している)を介して上
記導体ランド12上に接着されている。尚、導電性接着
剤14は、Agフィラーが充填されたアミン硬化系のエ
ポキシ樹脂であり、その粘度は、150Pa・S(ポア
ズ・秒)である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. First, FIG.
1 schematically illustrates a mounting form of an electronic component obtained according to the present embodiment. In FIG. 2, a circuit board 11 is formed by printing and baking a Cu thick film paste material on a ceramic substrate, and a conductor land (mounting area in the present invention) 12 is provided at a predetermined portion thereof. I have. And I
The C chip (electronic component according to the present invention) 13 is adhered on the conductor land 12 via a conductive adhesive 14 (shown by hatching in FIG. 2). The conductive adhesive 14 is an amine-curable epoxy resin filled with an Ag filler, and has a viscosity of 150 Pa · S (poise seconds).

【0012】このような実装形態は、図3に示すよう
に、塗布工程A1および搭載工程A2を順次実行するこ
とによりなされるもので、以下、各工程A1,A2の具
体的な内容について図1を参照して説明する。
As shown in FIG. 3, such a mounting mode is performed by sequentially executing a coating step A1 and a mounting step A2. Hereinafter, specific contents of each of the steps A1 and A2 will be described with reference to FIG. This will be described with reference to FIG.

【0013】まず、塗布工程A1では、回路基板11上
における所定位置にマスク15を配置し、開口部17か
ら導電性接着剤を印刷することによって、回路基板11
の導体ランド12上に導電性接着剤14を塗布する(図
1中、(a)参照)。尚、印刷条件としては、印刷荷重
は1N、スキージ(図示せず)の移動速度は30mm/
秒である。
First, in a coating step A1, a mask 15 is arranged at a predetermined position on the circuit board 11, and a conductive adhesive is printed from an opening 17 to thereby form the circuit board 11.
A conductive adhesive 14 is applied on the conductive land 12 (see FIG. 1A). As printing conditions, the printing load was 1 N, and the moving speed of a squeegee (not shown) was 30 mm /
Seconds.

【0014】このとき、この塗布工程A1で使用するマ
スク15は、図4に示すように、ステンレス材からなる
厚さ約70μmのメタルマスク16にあって、その開口
部17の内周面17aから回路基板11側となる面(図
4中、下面)18にかけての部位(本発明でいう所定部
位)がフッ素樹脂19で覆われて構成されたものであ
る。
At this time, the mask 15 used in the coating step A1 is a metal mask 16 made of stainless steel and having a thickness of about 70 μm, as shown in FIG. A portion (a predetermined portion in the present invention) extending to a surface (lower surface in FIG. 4) 18 on the circuit board 11 side is covered with a fluororesin 19.

【0015】尚、この場合、上記マスク15は、次のよ
うにして得られたものである。すなわち、メタルマスク
16における回路基板11とは反対側となる面(図5
中、上面)20に、耐熱性が高い例えばポリイミド製の
テープ21を貼り、その状態で、液状のフッ素樹脂を、
印刷、含浸法、スピンコート法などの周知の方法によっ
て、メタルマスク16における開口部17の内周面17
aから回路基板11側となる面18にかけての部位に塗
膜する。次いで、塗膜された液状のフッ素樹脂をオーブ
ンにて加熱硬化し、フッ素樹脂が加熱硬化する途中でテ
ープ21を剥がす。このようにして、マスク15が得ら
れたものである。
In this case, the mask 15 is obtained as follows. That is, the surface of the metal mask 16 opposite to the circuit board 11 (FIG. 5)
Medium, upper surface) 20, a tape 21 made of, for example, polyimide having high heat resistance is attached, and in that state, a liquid fluororesin is
The inner surface 17 of the opening 17 in the metal mask 16 is formed by a known method such as printing, impregnation, or spin coating.
Then, a coating is applied to a portion from a to the surface 18 on the circuit board 11 side. Next, the coated liquid fluororesin is cured by heating in an oven, and the tape 21 is peeled off while the fluororesin is being cured by heating. Thus, a mask 15 is obtained.

【0016】また、この場合、フッ素樹脂19の厚さ
(膜厚)は、約10μmであるが、0.5μm〜10μ
mであれば良いものである。これは、フッ素樹脂19の
厚さが0.5μmよりも小さいと、耐久性の点で不具合
が発生し、一方、フッ素樹脂19の厚さが10μmより
も大きいと、微細加工においてフッ素樹脂19が目詰ま
りを発生するからである。さらに、フッ素樹脂19の厚
さは、全体にわたって一定であることが望ましいが、凹
凸が±10μm未満であれば許容されるものである。こ
れは、凹凸が±10μm以上となると、この塗布工程A
1において、凹凸に伴って生じるマスク15と回路基板
11との間の距離のばらつきが、悪影響を及ぼす虞があ
るからである。
In this case, the thickness (film thickness) of the fluororesin 19 is about 10 μm, but is 0.5 μm to 10 μm.
If it is m, it is good. This is because if the thickness of the fluororesin 19 is smaller than 0.5 μm, a problem occurs in terms of durability. On the other hand, if the thickness of the fluororesin 19 is larger than 10 μm, the fluororesin 19 is not finely processed. This is because clogging occurs. Further, the thickness of the fluororesin 19 is desirably constant throughout, but is acceptable if the unevenness is less than ± 10 μm. This is because when the unevenness becomes ± 10 μm or more, this coating process A
This is because, in 1, the variation in the distance between the mask 15 and the circuit board 11 caused by the unevenness may have an adverse effect.

【0017】そして、導体ランド12上に導電性接着剤
14を塗布したのち、マスク15を上記所定位置から上
方に移動する(図1中、(b)参照)。さて、このと
き、導電性接着剤14の主成分であるエポキシ樹脂とフ
ッ素樹脂19との間は表面濡れ性が低いので、糸ひき現
象が発生することがなく、導電性接着剤14の上面は略
平坦な状態となり、導電性接着剤14の厚さにばらつき
が生じることもない。
After applying the conductive adhesive 14 on the conductor lands 12, the mask 15 is moved upward from the predetermined position (see (b) in FIG. 1). At this time, since the surface wettability between the epoxy resin and the fluororesin 19, which are the main components of the conductive adhesive 14, is low, the threading phenomenon does not occur, and the upper surface of the conductive adhesive 14 The conductive adhesive 14 is substantially flat, and the thickness of the conductive adhesive 14 does not vary.

【0018】次いで、搭載工程A2では、ICチップ1
3を導体ランド12上に、つまり、導体ランド12上に
塗布された導電性接着剤14上に搭載する(図1中、
(c)参照)。尚、搭載条件としては、荷重は6N、荷
重付加時間は1秒である。このとき、上述したような塗
布工程A1が行われたことによって、導電性接着剤14
の上面は略平坦な状態となっているので、接着面積が小
さくなることはない。
Next, in the mounting step A2, the IC chip 1
3 is mounted on the conductive land 12, that is, on the conductive adhesive 14 applied on the conductive land 12 (in FIG. 1,
(C)). In addition, as a mounting condition, a load is 6 N and a load application time is 1 second. At this time, the conductive adhesive 14
Since the upper surface is substantially flat, the bonding area does not decrease.

【0019】このように本実施例によれば、回路基板1
1の導体ランド12上に導電性接着剤14を塗布する塗
布工程A1では、開口部17の内周面17aから回路基
板11側となる面18にかけての部位がフッ素樹脂19
で覆われたマスク15を使用し、次いで、ICチップ1
3を導電性接着剤14上に搭載する搭載工程A2を行う
ようにしたから、塗布工程A1では、導電性接着剤14
が、糸引き現象が発生することなく塗布されるようにな
り、それに応じて、搭載工程A2では、ICチップ13
が、接着面積が小さくなることなく導電性接着剤14上
に接着されるようになり、これによって、ICチップ1
3と回路基板11との間の機械的な接続強度が低下する
ことを防止でき、製品の品質が低下することを防止でき
る。
As described above, according to the present embodiment, the circuit board 1
In the application step A1 of applying the conductive adhesive 14 on the one conductive land 12, the portion from the inner peripheral surface 17a of the opening 17 to the surface 18 on the circuit board 11 side is made of a fluororesin 19
Using the mask 15 covered with the IC chip 1
3 is mounted on the conductive adhesive 14, the application step A1 includes the step of mounting the conductive adhesive 14 on the conductive adhesive 14.
Is applied without causing the stringing phenomenon. Accordingly, in the mounting step A2, the IC chip 13
Can be adhered onto the conductive adhesive 14 without reducing the adhesion area.
It is possible to prevent a decrease in mechanical connection strength between the circuit board 3 and the circuit board 11 and to prevent a decrease in product quality.

【0020】特に、この場合は、接着剤として導電性接
着剤14を使用しているので、ICチップ13と回路基
板11とを機械的に接続することに加えて、それらを電
気的に接続することもでき、しかも、その場合に、導体
ランド12間などで短絡が生じることを防止できる。
Particularly, in this case, since the conductive adhesive 14 is used as the adhesive, the IC chip 13 and the circuit board 11 are electrically connected in addition to the mechanical connection. In this case, a short circuit can be prevented from occurring between the conductor lands 12 and the like.

【0021】また、導電性接着剤14との表面濡れ性の
低い樹脂として、フッ素樹脂19を採用したので、フッ
素樹脂が汎用性の高い樹脂であることから、容易に入手
および取扱うことができ、また、メタルマスク16の所
定部位をフッ素樹脂19で覆うにあたっては、例えば印
刷、含浸法、スピンコート法などの周知の方法を適用す
ることができる。
Further, since the fluororesin 19 is employed as a resin having low surface wettability with the conductive adhesive 14, it can be easily obtained and handled because the fluororesin is a highly versatile resin. In covering a predetermined portion of the metal mask 16 with the fluororesin 19, a known method such as printing, impregnation, and spin coating can be applied.

【0022】本発明は、上記した実施例にのみ限定され
るものでなく、次のように変形または拡張することがで
きる。接着剤としては、導電性接着剤に限らず、絶縁性
の接着剤を使用しても良く、つまり、電子部品と回路基
板とを機械的にのみ接続する構成としても良い。
The present invention is not limited to the embodiment described above, but can be modified or expanded as follows. The adhesive is not limited to the conductive adhesive, but may be an insulating adhesive. That is, a configuration may be used in which the electronic component and the circuit board are mechanically connected only.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例の作用を示す断面図(a),
(b)および側面図(c)
FIG. 1 is a sectional view (a) showing the operation of an embodiment of the present invention,
(B) and side view (c)

【図2】実装形態を模式的に示す側面図FIG. 2 is a side view schematically showing a mounting mode.

【図3】工程の流れを示す流れ図FIG. 3 is a flowchart showing a process flow.

【図4】マスクの断面図FIG. 4 is a sectional view of a mask.

【図5】メタルマスクにテープが貼られた状態を示す断
面図
FIG. 5 is a cross-sectional view showing a state in which a tape is attached to a metal mask.

【図6】従来例を示す図1相当図FIG. 6 is a diagram corresponding to FIG. 1 showing a conventional example.

【図7】他の従来例を示す側面図FIG. 7 is a side view showing another conventional example.

【符号の説明】[Explanation of symbols]

図面中、11は回路基板、12は導体ランド(実装領
域)、13はICチップ(電子部品)、14は導電性接
着剤、15はマスク、17は開口部、17aは内周面、
18は面、19はフッ素樹脂である。
In the drawing, 11 is a circuit board, 12 is a conductor land (mounting area), 13 is an IC chip (electronic component), 14 is a conductive adhesive, 15 is a mask, 17 is an opening, 17a is an inner peripheral surface,
Reference numeral 18 denotes a surface, and 19 denotes a fluororesin.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 回路基板上の所定の実装領域に電子部品
をマスク印刷により塗布された接着剤で実装する電子部
品の実装方法において、 少なくとも開口部の内周面から前記回路基板側の面にか
かる所定部位が前記接着剤との表面濡れ性の低い樹脂に
より覆われたマスクを使用して前記実装領域に接着剤を
塗布する塗布工程と、 前記電子部品を前記実装領域に搭載する搭載工程とを順
次実行することを特徴とする電子部品の実装方法。
An electronic component mounting method for mounting an electronic component on a predetermined mounting area on a circuit board with an adhesive applied by mask printing, wherein at least an inner peripheral surface of an opening portion faces the circuit board side. An application step of applying an adhesive to the mounting area using a mask in which the predetermined portion is covered with a resin having a low surface wettability with the adhesive; and a mounting step of mounting the electronic component on the mounting area. Are sequentially executed.
【請求項2】 前記樹脂は、フッ素樹脂であることを特
徴とする請求項1記載の電子部品の実装方法。
2. The method according to claim 1, wherein the resin is a fluororesin.
【請求項3】 前記接着剤は、導電性であることを特徴
とする請求項1または2記載の電子部品の実装方法。
3. The electronic component mounting method according to claim 1, wherein the adhesive is conductive.
JP10190453A 1998-07-06 1998-07-06 Method of mounting electronic components Pending JP2000022314A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10190453A JP2000022314A (en) 1998-07-06 1998-07-06 Method of mounting electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10190453A JP2000022314A (en) 1998-07-06 1998-07-06 Method of mounting electronic components

Publications (1)

Publication Number Publication Date
JP2000022314A true JP2000022314A (en) 2000-01-21

Family

ID=16258389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10190453A Pending JP2000022314A (en) 1998-07-06 1998-07-06 Method of mounting electronic components

Country Status (1)

Country Link
JP (1) JP2000022314A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100834003B1 (en) 2006-09-19 2008-05-30 동방화닉스 주식회사 Apparatus for Bonding Components on Liquid Crystal Display Panel and Method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100834003B1 (en) 2006-09-19 2008-05-30 동방화닉스 주식회사 Apparatus for Bonding Components on Liquid Crystal Display Panel and Method thereof

Similar Documents

Publication Publication Date Title
JP3086066B2 (en) Cream solder printing method and electronic component soldering method
JPH1064955A (en) Structure for mounting semiconductor chip
US20090211798A1 (en) Pga type wiring board and method of manufacturing the same
JP3608536B2 (en) Electronic component mounting method
JPS63310581A (en) Film body for electric connection
JP2000022314A (en) Method of mounting electronic components
JPH11251728A (en) Printed board and method for coating cream solder
JPH1027952A (en) Printed wiring board and manufacture thereof
JPH02185051A (en) Tape carrier for double-side protective coat type tab
JP2005175020A (en) Wiring board, electronic circuit element and its manufacturing method, and display
JP3896696B2 (en) Electronic component mounting method
JPH05129759A (en) Manufacture of printed wiring board
JP3444787B2 (en) Film carrier tape for mounting electronic components and method of manufacturing film carrier tape for mounting electronic components
JP2002083841A (en) Mounting structure and its manufacturing method
JP3327171B2 (en) TAB tape with stress buffer layer and ball terminals
JP3616657B2 (en) Printed wiring board and printed wiring board manufacturing method
JPH0794854A (en) Printed wiring board with viahole
JP2000022310A (en) Method of mounting electronic components
JP4005077B2 (en) Manufacturing method of semiconductor device and coating method of viscous liquid
JPH01135050A (en) Semiconductor device
JP2023058975A (en) printed wiring board
JP3492826B2 (en) Chip soldering method
JPH0653640A (en) Printed wiring board and manufacture thereof
JPH06206303A (en) Cream solder application device
JP2001119119A (en) Printed circuit board and method for mounting electronic component

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040723

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060912

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061102

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20061212

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070118

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20070216

A912 Removal of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20070309