JP2000020713A - Image processor and projection display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain low speed operation of a line buffer to be used for a circuit part for reduction/expansion processing by providing N partial line buffers for storing preceding line image data equivalent to 1/N (N is a prescribed integer) pieces of pixels in one line of original image data. SOLUTION: In a reduction part 130, image data DV0 inputted to a line buffer part 320 are alternately written in first and second partial line buffers 322 and 324 for every one pixel. Also, those image data are alternately read for every one pixel. As a result, preceding line image data DDV0 being image data before the image DV0 by one line are synchronously outputted from the line buffer part 320. Writing or reading of the image data for the partial line buffers 322 and 324 is executed in a cycle which is two times as fast as the cycle of the original image data DV0 to be inputted or the delayed image data DDV0 to be outputted and operated at a speed which is 1/2 times as fast as that.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing technique for displaying an image represented by an input image signal by reducing or enlarging the image.

[0002]

2. Description of the Related Art The size (resolution) of an image represented by an image signal output from an image generating device such as a personal computer is 640 × 480 pixels, 800 × 600.
Pixels, 1024 x 780 pixels, 1280 x 1024 pixels, etc. have been diversified. On the other hand, an electro-optical device such as a liquid crystal device or a DMD (digital micromirror device) used as a display device of a direct-view display device or as a light modulator of a projection display device has a specific image display size. Therefore, an image larger than the display size cannot be displayed as it is. Therefore, in an image display apparatus using such an electro-optical device, in order to display images having various sizes as described above, the entire image is reduced or enlarged in advance and adjusted to a displayable size. Is being performed. In a case where the input image is displayed on a part of the entire display screen of the electro-optical device, that is, on a so-called window, the input image is reduced or enlarged to have a size that can be displayed on the window. Is performed.

For reducing or enlarging an image, a method based on linear interpolation using a matrix operation of 2 × 2 pixels is generally used. FIG. 12 is an explanatory diagram showing a conventional reduction / enlargement processing unit used for reducing or enlarging an image. This reduction / enlargement processing unit 1000
Line buffer unit 1010 and image interpolation operation unit 1020
And The line buffer unit 1010 includes three line buffers 1011, 1012, and 1013, and a line buffer control unit 1014. The image interpolation calculation unit 1020 includes a 2 × 2 pixel matrix calculation circuit, and is configured to reduce or enlarge an original image (hereinafter, referred to as an original image).
It may be called an “original image”. ) Is performed according to the reduction ratio or the enlargement ratio with respect to the interpolation image data PC.
Is output. Therefore, two lines of image data need to be input to the image interpolation calculation unit 1020 at substantially the same timing.

The line buffer unit 1010 converts original image data PD, which is sequentially input for each pixel of one line, into image data output for each pixel of two lines. Three
Each of the line buffers 1011, 1012, and 1013 has a storage capacity for storing one line of the input image data PD.
014, the image data for one line is sequentially written. For example, the first line buffer 10
11 is selected, and the image data of the first line is written. Next, the second line buffer 1012 is selected, and the image data of the second line is written. continue,
The third line buffer 1013 is selected, and the image data of the third line is written. Then, the first line buffer 1011 is selected again, and the image data of the fourth line is written. This operation is repeatedly executed by the line buffer control unit 1014. Here, the third
When the image data is written to the line buffer 1013 of the first and second lines, the first and second line buffers 1011 and 1012
Has already been written with the image data of the first and second lines. The line buffer control unit 1014 writes the image data of the third line into the third line buffer 1013,
The image data of the first line and the second line are read from 11 and 1012 in the order of writing. In this way, image data for two lines is sequentially input to the image interpolation calculation unit 1005 at substantially the same timing.

As described above, the conventional reduction / enlargement processing unit 1
000 includes three line buffers, writes one line of image data into one of the three line buffers, and reads two lines of image data written into the other two line buffers to read the image. Interpolation image data is generated by the interpolation calculation unit 1020. As a result, it is possible to generate an image according to the reduction ratio or the enlargement ratio.

[0006]

In the reduction / enlargement processing unit 1000, as the resolution of the image represented by the input image data increases, the speed of the image data input to the line buffer unit 1010 increases. Be faster. Therefore, each line buffer 1011, 1012,
The speed for writing one line of image data into the line buffer 1013 must also be increased.
1, 1012 and 1013 require a memory that can operate at higher speed. However, there is a problem that a faster memory is more expensive and power consumption is increased.
Accordingly, there has been a demand for reducing the operation speed of a line buffer used in a circuit unit for performing reduction / enlargement as much as possible.

[0007] Usually, the reduction / enlargement processing unit is often integrated with other various image processing units. Generally, a memory has a large circuit scale, and therefore it is preferable that the storage capacity of the line buffer be small. Also, when a commercially available memory is used without being integrated, it is preferable that the storage capacity of the line buffer be small in order to reduce the size and power consumption of the device. For these reasons, heretofore, there has been a demand to reduce the storage capacity of a line buffer used in a circuit unit for performing reduction / enlargement as much as possible. Note that such a problem is not limited to an image display device using an electro-optical device, but also applies to other types of image display devices having a circuit unit for performing such reduction / enlargement processing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem in the prior art, and has an object to enable the operation speed of a line buffer used in a circuit unit for performing reduction / enlargement processing to be lower than that of a conventional line buffer. As a first object. A second object is to reduce the storage capacity of the line buffer as compared with the related art.

[0009]

In order to solve at least a part of the above-mentioned problems, an image processing apparatus according to the present invention processes original image data representing an original image, thereby obtaining the original image. An image processing apparatus for creating adjusted image data representing an adjusted image obtained by enlarging or reducing the current line image data, while accumulating current line image data as original image data for one input line, A line buffer unit that outputs preceding line image data that is original image data one line before the current line image data, and converts the current line image data and the preceding line image data according to a desired enlargement ratio or reduction ratio. An image interpolation operation unit that generates the adjusted image data by performing an operation. N partial line buffers each storing the preceding line image data corresponding to 1 / N (N is an integer of 2 or more) pixels of one line, and one of the N partial line buffers A line buffer control unit that sequentially switches and selects one pixel timing at a time, outputs the preceding line image data from the selected partial line buffer, and stores the current line image data in the selected partial line buffer And the following.

The projection display device of the present invention is a projection display device for projecting an image on a screen and displaying the image. The projection display device enlarges the original image by processing the original image data representing the original image. Alternatively, an image processing device that creates adjustment image data representing a reduced adjustment image, an image display signal generation unit that generates an image display signal based on the adjustment image data, and a light that forms an image according to the image display signal An electro-optical device that emits light, and a projection optical system that projects light emitted from the electro-optical device. Here, the image processing device corresponds to the image processing device of the present invention.

In the image display device and the projection type display device according to the present invention, each partial line buffer is selected at every timing of N pixels of the current line image data, so that the timing of one pixel of the current line image data is selected. It is possible to operate at an operation speed that is 1 / N times lower than the operation speed when each is selected.

The partial line buffer is one of the original image data formats that can be input to the image processing apparatus.
It is preferable that the number of pixels in the line is 1 / N or more of the number of pixels for one line in the largest original image data format, and the storage capacity is less than one line.

According to the image processing device and the projection display device, the storage capacity of the line buffer used in the circuit section for performing the image reduction / enlargement processing can be reduced as compared with the conventional case. In particular, if the number of pixels in one line is 1 / N of the number of pixels in one line in the original image data format, the storage capacity for one line in the original image data format in which the number of pixels in one line is the largest is provided. A circuit that performs image reduction / enlargement processing alone can be configured.

[0014]

DETAILED DESCRIPTION OF THE INVENTION Overall configuration of projection display device:
Next, embodiments of the present invention will be described based on examples.
FIG. 1 is a block diagram showing a configuration of a projection display apparatus as an embodiment of the present invention. This projection display device 100
Is an image conversion unit 110 and an AD (analog-digital)
The conversion unit 120, the reduction processing unit 130, the image processing control unit 140, the memory 150, the enlargement processing unit 160, the liquid crystal display panel 180 which is a light modulation device, and controls light modulation in the liquid crystal display panel 180. A liquid crystal display driving unit 170, an illumination optical system 190, and a projection optical system 200 are provided.

The image converter 110 outputs an image signal that can be input to the AD converter 120, a horizontal synchronizing signal HD1, a vertical synchronizing signal VD1, and the like according to the input image signal PS. For example, when component image signals (R, G, B image signals, a horizontal synchronization signal, and a vertical image signal) output from a personal computer or the like are input, the R, G, B image signal RGBS is output. AD converter 12
0, and outputs the horizontal synchronization signal HD1 and the vertical image signal VD1 to the image processing control unit 140.
When a composite image signal (an image signal in which a luminance signal, a chrominance signal, and a synchronization signal are superimposed) output from a video recorder or a television is input, a horizontal synchronization signal HD1 and a vertical synchronization signal are converted from the composite image signal. VD
1 and a field signal FD indicating whether the image signal is an odd-field image signal or an even-field image signal, and is output to the image processing control unit 140. The R, G, and B image signals RGBS are separated. The signal is output to the AD converter 120.

The image signal RGBS is converted into a digital image signal DV0 in the AD converter 120 and input to the reduction processor 130. The AD converter 120 converts the R, G, and B image signals included in the image signal RGBS into A
D-convert. Therefore, the digital image signal DV0 is R,
G and B digital image signals are included. The sampling clock signal D used for AD conversion
CLK1 is supplied from the image processing control unit 140.

The reduction processing unit 130 includes an image processing control unit 14
In accordance with a reduction control signal CTL1 supplied from 0, the image data of each of R, G, and B included in the digital image signal DV0 is reduced and output as reduced image data DV1. The reduced image data DV1 is transmitted to the image processing control unit 14
0 is stored in the memory 150. The reduced image data DV1 stored in the memory 150 is stored in the image processing controller 1
The data is read out via the control unit 40 and supplied to the enlargement processing unit 160.

The enlargement processing section 160 includes an image processing control section 14
In response to the enlargement control signal CTL2 supplied from 0, the reduced image data DV1 read from the memory 150 is enlarged to output enlarged image data DV2.

The liquid crystal display driving section 170 converts the image represented by the enlarged image data DV2 into a vertical synchronization signal V2.
D2, the horizontal synchronization signal HD2, and the dot clock signal D
By driving each pixel of the liquid crystal display panel 180 according to CLK2, the incident light is optically modulated and displayed by the liquid crystal display panel 180. Note that the vertical synchronization signal VD2, the horizontal synchronization signal HD2, and the dot clock signal DCLK2 are supplied from the image processing control unit 140. Note that the liquid crystal display panel driving unit 17
0 may be integrally formed on a substrate of a liquid crystal panel display 180 described later.

A light beam of an image formed on the liquid crystal display panel 180 on which light from the illumination optical system 190 is incident is projected on the screen SC by the projection optical system 200. That is, the light emitted from the illumination optical system 190 and incident on the liquid crystal display panel 180 is modulated according to the image data given to the liquid crystal display panel 180, and the light emitted from the liquid crystal display panel 180 is projected onto the screen SC by the projection optical system 200. Projected on
An image is displayed on the screen SC. Note that the liquid crystal display panel 180 in this embodiment corresponds to the electro-optical device of the present invention. The light of the illumination optical system 190 is separated into R light, G light, and B light, and each color light is modulated by the liquid crystal display panel 180 in accordance with each of the R, G, and B image data. When combining the color lights and projecting the combined light from the projection optical system 200, 13 in FIG.
The components 0, 140, 150, 160, 170, and 180 are provided for each color, data processing is performed for each image data of each color, and each color light is optically modulated by each liquid crystal display panel 180.

The image processing control section 140 is provided for each of the circuit sections 11
There is provided a register for storing the processing conditions of 0, 120, 130, 160, and 170. The processing conditions of each circuit section are given from a CPU (not shown) and stored in this register. The image processing control unit 140 generates a control signal used in each circuit unit based on the processing conditions stored in the register. For example, the size of the image represented by the image signal input to the projection display device, the specification of the image signal, and the actual display size of the liquid crystal display panel 180 (the display resolution of the panel or the size of the display window) are stored in the register. It is memorized. In each circuit unit from the image conversion unit 110 to the memory 150, each control signal is generated based on the dot clock signal DCLK1. This dot clock signal DCLK1 is equal to the horizontal synchronization signal HD.
1 is generated by a PLL circuit (not shown). Also, the liquid crystal display panel 1
In each circuit section up to 80, the dot clock signal D
Each control signal is generated based on CLK2. The dot clock signal DCLK2 is supplied to the liquid crystal display panel 1
80 horizontal synchronization signal HD suitable for displaying an image
2 and the vertical synchronization signal VD2.

The image processing control section 140 writes the reduced image data DV1 supplied from the reduction processing section 130 into the memory 150, reads out the reduced image data DV1 written into the memory 150, and supplies the reduced image data DV1 to the enlargement processing section 160. .

Since the projection display device 100 includes the reduction processing section 130 and the enlargement processing section 160, various reduction or enlargement processing can be performed by combining the respective reduction rates and enlargement rates. For example, when the size of the image represented by the input image data is larger than the display screen size of the liquid crystal display panel 180, a reduced image to some extent is generated in advance by the reduction processing unit 130 and stored in the memory 150. In addition, the image can be enlarged and displayed to various image sizes to be displayed on the liquid crystal display panel 180 by the enlargement processing unit 160.

The projection display apparatus 100 shown in FIG. 1 shows a case where only one analog image signal PS is input to the image conversion unit 110, but is configured so that a plurality of image signals are input. , One of them may be selected and processed. Further, a digital image signal supplied via a CPU (not shown) may be input to the reduction processing unit 130.

B. Configuration and operation of reduction processing section 130: FIG.
5 is a block diagram illustrating a configuration of a reduction processing unit 130. FIG.
The reduction processing unit 130 includes a line buffer unit 320 and an image interpolation calculation unit 340. Each of these circuits
It is provided for each color of RGB, and reduction processing is performed for each color. The image interpolation calculation unit 340 includes a 2 ×
It has a two-pixel matrix operation circuit. FIG. 3 is an explanatory diagram illustrating an outline of the interpolation processing in the image interpolation calculation unit 340. FIG. 3 shows a case where an image of 4 × 4 pixels is reduced to an image of 3 × 3 pixels, and O (i, j) (i, j
Is an integer of 1 to 4) indicates the pixel data (original pixel data) of the i-th pixel of the j-th line in the original image before the reduction processing. P (n, m) (n and m are integers of 1 to 3) indicates the n-th pixel data (reduced pixel data) of the m-th line of the reduced image (adjusted image) after the reduction processing. For example, the reduced pixel P (2,2) is equal to 4 of the original image.
Original pixels O (2,2), O (3,2), O (2,
3), corresponds to the pixel at the position surrounded by O (3, 3).
The image interpolation calculation unit 340 includes four original pixels O (2, 2),
The pixel data of the reduced pixel P (2,2) is interpolated from the pixel data of O (3,2), O (2,3), O (3,3).
Therefore, in order to execute a matrix operation of 2 × 2 pixels, the image interpolation operation unit 340 has a line buffer unit 320.
, Two lines of image signals are input at substantially the same timing. That is, the line buffer unit 320, together with the input image data of one line (current line image data), and the image data of one line before (the preceding line image data) for each pixel of the current line image data. Output at the timing.

The line buffer section 320 includes two partial line buffers 322 and 324 and a line buffer control section 326 as shown in FIG. FIG. 4 is a timing chart showing write and read timings of the two partial line buffers 322 and 324 executed by the line buffer control unit 326. FIG.
FIG. 4F shows an image signal (current line image data) DV0 supplied from the D conversion unit, and FIG.
0 shows a delayed image signal (preceding line image data) DDV0 output from 0. FIG. 4 (b) and (c)
Indicates an address signal (address data) 322AD and a write / read control signal 322R / W supplied to the partial line buffer 322. FIGS. 4D and 4E show an address signal (address data) 324AD and a write / read control signal 324R / W supplied to the partial line buffer 324.

As shown in FIG. 4A, the current line image data DV0 output from the AD converter 120 is supplied to the two partial line buffers 322 and 324. (1, j), (2, j)... Indicate (first pixel data of the j-th line), (second pixel data of the j-th line),. As shown in FIG. 4B, the address of the first partial line buffer 322 is set only for a period corresponding to the period Tc of one pixel of the image data DV0 from the timing T1 when the image data DV0 of the first pixel is input. The address has been input from the previous time, and the address is held for a period 2Tc which is almost twice as long as one pixel period Tc. Then, as shown in FIG. 4C, in the holding period 2Tc of the address data 322AD, image data (preceding line image data) O (1, j-1), O (3) one line before in the first half period. , J−1),... Are executed, and image data (current line image data) O (1, j), O (3,
j),... are executed.

On the other hand, as shown in FIG. 4D, the address of the second partial line buffer 324 is inputted from the timing T1 when the image data DV0 of the first pixel is inputted. Period 2Tc which is almost twice as long as Tc
Only that address is held. And FIG.
As shown in (e), in the holding period 2Tc of the address data 324AD, the image data (preceding line image data) O (2, j−1), one line before in the first half period,
O (4, j−1),... Are executed, and image data (current line image data) input in the latter half period
Writing of O (2, j), O (4, j),... Is executed.

Accordingly, the first partial line buffer 322
The read and write of the image data in the second partial line buffer 324 are shifted from the read and write of the image data by a period substantially equal to one pixel cycle Tc.
That is, when the image data is written in the first partial line buffer 322, the image data is read from the second partial line buffer 324, and the image data is read from the first partial line buffer 322. When it is, the image data is written in the second partial line buffer 324. Thereby, the line buffer unit 32
0 is input to the first pixel by pixel.
Are written alternately to the second partial line buffers 322, 324, and the image data written to the two partial line buffers 322, 324 are alternately read for each pixel. As a result, as shown in FIG. 4F, the preceding line image data DDV0, which is the image data one line before the image data DV0 shown in FIG. Is done. Here, the phrase "image data of two lines are output" in synchronization "" means that they are output in accordance with the same clock timing, and the image at the same pixel position on the two lines is output. The data need not be output at the same time. The delayed image data DDV0 shown in FIG. 4F is output at a timing earlier than the image data DV0 shown in FIG. 4A by the period Tc. Since this can be absorbed by latching based on the dot clock signal DCLK1 described above, there is no problem. Therefore, the line buffer unit 320 can supply the image signals of two lines to the image interpolation calculation unit 340 at substantially the same timing.

As described above, the two partial line buffers 3
The image data of each line is alternately written into pixels 22 and 324 for each pixel. Therefore, the storage capacity of one partial line buffer only needs to have a storage capacity (storage capacity) for storing pixel data for 1/2 line.
The line buffer unit 320 includes a partial line buffer 322
And 324 as long as they have a storage capacity for one line of pixel data. Specifically, one partial line buffer only needs to have a storage capacity of １ ／ line of the largest number of pixels for one line among various image signal formats that can be input. That is, the line buffer unit 320 can be configured with a storage capacity of 1/3 of the memory used in the conventional example of FIG. 12, and the reduction processing unit 130 can be realized with a smaller configuration than the conventional example. it can.

As can be seen from FIG. 4, the writing and reading cycles of the image data of the respective partial line buffers 322 and 324 depend on the original image data input to the line buffer 320 and the delay output from the line buffer 320. It can be executed at twice the cycle of the image data. Therefore, it is １ ／ compared to the memory used in the conventional example.
It can be operated at a speed of As a result, a memory that is slower than the memory used in the conventional example can be used, so that the reduction processing unit 130 can be configured at lower cost. Further, low power consumption can be achieved.

As can be seen from the above description, the reduction processing section 130 corresponds to the image processing device of the present invention.

C. Interpolation Process of Image Interpolation Operation Unit 340: The image interpolation operation unit 340 executes an interpolation process according to a given reduction ratio, as described below.

C-1. Horizontal interpolation processing:
For ease of explanation, a case where a 4-pixel image is reduced to a 3-pixel image will be described as an example. An image before reduction is called an “original image”, a pixel in the original image is called an “original image pixel”, and a pixel position defined in the original image is called an “original image pixel position”. The value of the original image pixel position is not limited to an integer, but may be a value including a decimal number. The reduced image is called a “reduced image”, pixels in the reduced image are called “reduced image pixels”, and pixel positions defined in the reduced image are called “reduced image pixel positions”.

FIG. 5 is an explanatory diagram showing pixel positions in the original image and interpolated pixel data which are interpolated based on the original image with respect to the pixel positions in the reduced image.

Generally, an image is multiplied by α in the horizontal direction (α is 1 /
When the number is 2 or more and 1 or less), the position (pixel number) x of the original image pixel to be interpolated as the n-th reduced pixel is given by the following equation (1).

X = 1 + (1 / α) · (n−1) (1)

When α = 3/4, from the above equation (1),
The positions (pixel numbers) of the original image pixels given to the positions (pixel numbers) 1, 2, and 3 of the reduced image pixels are 1, (2 + 1 /
3), (3 + 2/3).

The pixel data of the original image pixel Px whose original image pixel position value is x has the original image pixel positions i and (i
+1) is interpolated from the pixel data of the two original image pixels Pi and Pi + 1. At this time, the pixel data of the original image pixel Px is calculated according to the following equation (2).

Px = kx · Pi + (1−kx) · Pi + 1 (2)

Here, as shown in the following equation (3), the correction coefficient kx is a ratio of the distance between the x pixel and the (i + 1) pixel to the distance between the i pixel and the (i + 1) pixel. Is shown.

K x = {(i + 1) −x} / {(i + 1) −i} = {(i + 1) −x} (3)

A parameter indicating the position of two original image pixels Pi and Pi + 1 used for interpolation of the original image pixel Px.
i is given by the following equation (4).

I = {INT [x]} (4)

As described above, the pixel data of the original image pixel given to the n-th reduced image pixel can be obtained by using the above equations (1) to (4). For example, FIG.
As shown in (3), when α = 3/4, the interpolation pixel data given to the positions (pixel numbers) 1, 2, and 3 of the reduced image pixels are P1, (P1 / 2/3 + P2Ｐ), (P3・
1/3 + P4 · 2/3).

C-2. Vertical interpolation processing: The vertical interpolation processing can be executed in the same manner as in the horizontal direction except that the reduction direction is the vertical direction. In the following, for ease of explanation, a case in which a 4-line image is reduced to a 3-line image will be described as an example. A line in the original image is called an “original image line”, and a line position defined in the original image is called an “original image line position”. The value of the original image line position is not limited to an integer, but may be a value including a decimal number. A line in the reduced image is called a “reduced image line”, and a line position defined in the reduced image is called a “reduced image line position”.

FIG. 6 is an explanatory diagram showing the line positions in the original image and the interpolated line data that are interpolated based on the original image with respect to the line positions in the reduced image.

The image is vertically multiplied by β (β is β to 1)
(The following number), the position (line number) y of the original image line to be interpolated as the m-th reduced line is (1)
Like the equation, it is given by the following equation (5).

Y = 1 + (1 / β) · (m−1) (5)

When β = 3/4, from the above equation (5),
The positions (line numbers) of the original image lines given to the positions (line numbers) 1, 2, and 3 of the reduced image lines are 1, (2
+ ／) And (3 + ２).

Further, the line data of the original image line Ly whose original image line position value is y includes two original image lines Li and Li + whose original image line positions are j and (j + 1).
Interpolated from 1 pixel data. At this time, the line data of the original image line Lx is expressed by the following equation (6) in the same manner as in equation (2).
It is calculated according to the formula.

Ly = ky · Li + (1-ky) · Li + 1 (6)

Here, as shown in the following equation (7), the correction coefficient ky is a ratio of the distance between the y line and the (j + 1) line to the distance between the j line and the (j + 1) line. Is shown.

Ky = {(j + 1) -y} / {(j + 1) -j} = {(j + 1) -y} (7)

The parameter j indicating the position of the two original image lines Lj and Lj + 1 used for interpolation of the original image line Lx is given by the following equation (8).

J = {INT [y]} (8)

As described above, the line data of the original image line given to the m-th reduced image line is obtained by the above (5)
It can be obtained by using the equations (8) to (8). For example, as shown in FIG. 6, when β = 3/4, the interpolation line data given to the positions (line numbers) 1, 2, and 3 of the reduced image lines are L1, (L1 / 2/3 + L2 / 1 /
3), (L3 · 1/3 + L4 · 2/3).

C-3. Interpolation processing associated with horizontal and vertical reductions: In the following, for ease of explanation, 4 ×
An example will be described in which a four-pixel image is reduced to a 3 × 3 pixel image. FIG. 7 is an explanatory diagram showing the interpolated image data given to each pixel on each line of the reduced image when the image is reduced by a factor of 3/4 in the horizontal direction and the vertical direction. O (x, y) in the figure indicates pixel data at the x-th original image pixel on the y-th image line. The parameters x and y indicating the pixel data O (x, y) of the n-th reduced image pixel of the m-th reduced image line have been described above according to the horizontal magnification α and the vertical magnification β ( It is calculated from the expressions 1) and (5), respectively.

The interpolation formula for giving each pixel data can be created by combining the horizontal interpolation formula given by the above formula (2) and the vertical interpolation formula given by the formula (6). FIG. 8 is an explanatory diagram illustrating a method of interpolating the pixel O (x, y). Horizontal correction factor kx
(0 ≦ kx ≦ 1) is given by the above equation (3).
The vertical correction coefficient ky (0 ≦ ky ≦ 1) is given by the above equation (7). Also, x of the y-th image line
The fourth pixel data O (y, x) is composed of four pixels O (i, j), O (i, j + 1), O (i + 1,
j), O (i + 1, j + 1) and correction coefficients Kx, Ky
From this, it can be obtained by the following equation (9).

O (x, y) = ky · kx · O (i, j) + ky · (1-kx) · O (i + 1, j) + (1-ky) · kx · O (i, j + 1) + (1-ky). (1-kx) .O (i + 1, j + 1) (9)

In the expression (9), if ky = 1, the expression (9) is equivalent to the expression (2). That is, (9)
The interpolation image data of the x-th image pixel in the reduction only in the horizontal direction can be obtained from the equation. Similarly, kx =
If it is set to 1, interpolation image data of the y-th line in the reduction only in the vertical direction can be obtained.

Equation (9) is obtained by the following equation (10):
It can be rewritten as in equations 1a) to (11d).

O (x, y) = K00 · O (i, j) + K01 · O (i + 1, j) + K10 · O (i, j + 1) + K11 · O (i + 1, j + 1) (10) K00 = ky · kx ... (11a) K01 = ky. (1-kx) ... (11b) K10 = (1-ky) .kx ... (11c) K00 = (1-ky). (1-kx) ... (11d)

The image interpolation calculator 340 shown in FIG.
This executes the linear operation of the equation (10). That is, the image interpolation calculation unit 340 includes four coefficients K00, K01,
According to the settings of K10 and K11, image data given to each pixel on each line of the reduced image generated by the predetermined reduction processing can be generated.

FIG. 9 shows coefficients K00, K01, K10, and K11 used when the image is reduced by 3/4 in the horizontal and vertical directions.
FIG. Line m and pixel n in the figure
Indicates a reduced image line (reduced image line) and a pixel (reduced image pixel). Four pixels O (i, j), O (i + 1, j), O (i, used for correcting the nth reduced image pixel of the mth reduced image line
j + 1), a parameter i indicating O (i + 1, j + 1),
j is determined according to the equations (1) and (4) and the equations (5) and (8). Also, four interpolation coefficients K00, K0
The values of 1, K10, and K00 are calculated according to the above-described equations (3), (7), and (11a) to (11d).

The image data reduced in the horizontal and vertical directions as described above is temporarily stored in the memory 150. Then, when the stored reduced image data is read out from the memory 150 and displayed, the enlargement processing unit 160 performs an enlargement process. For example, when the image is reduced to 3/4 times and displayed when the image is reduced to 3/4 times, the enlargement processing unit 16
If the value is 0, the reduced image read from the memory 150 is processed at the same magnification.

C-4. FIG. 10 is a block diagram showing a configuration of the image interpolation calculation unit 340. The image interpolation calculation unit 340 includes the interpolation calculation unit 35
0, a latch unit 360, and an output buffer unit 362. The interpolation operation unit 350 includes four multipliers 351 to 354 and three adders 355 to 357. Each of the four multipliers 351 to 354 is
The result of multiplying the first pixel O (i, j) by the coefficient K00, the second
Multiplication result of the pixel O (i + 1, j) and the coefficient K01, the third
Multiplication result of the pixel O (i, j + 1) with the coefficient K10, the fourth
Of the pixel O (i + 1, j + 1) and the coefficient K11. The multiplication results of the four multipliers 351 to 354 are added by the three adders 355 to 355 and output to the latch unit 360. Interpolator 3
Reference numeral 50 executes the interpolation calculation (matrix calculation) represented by the expression (10). Note that the processing in the interpolation calculation unit 350 does not use the illustrated multipliers and adders, but uses the CPU.
Or the like may perform arithmetic processing according to software.

The latch section 360 converts the interpolation data output from the interpolation calculation section 350 into an image processing control section 140 (FIG. 1).
Enable signal En supplied from the
Latch according to TCLK. Output buffer unit 362
Outputs interpolation data according to the read clock RCLK supplied from the image processing control unit 140. Interpolator 3
The interpolation processing executed in 50 generates interpolation data in a pipeline manner every time four input pixels and four coefficients are input. For example, if the original image before the reduction is reduced to 3/4 times, one out of three times of the interpolation data output from the interpolation calculation unit 350 is invalid interpolation data. When unnecessary interpolation data is output from the interpolation calculation unit 350, the latch unit 360 operates to inhibit the latch operation by the enable signal En supplied from the image processing control unit 140, and is effective as a reduced image. Only the interpolation data is latched. The interpolation calculation unit 350
Whether or not the interpolation data output from is valid is easily obtained from the pixel position x and the line position y given by the equations (1) and (5).

The present invention is not limited to the above examples and embodiments, but can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

(1) As described above, the image interpolation operation unit 34
The interpolation process at 0 is described as an example in the case of reducing the image in the horizontal direction and at the same magnification in the horizontal direction. However, the magnification α in the horizontal direction and the magnification β in the vertical direction can be independently set to a positive value of 以上 or more and 1 or less. The magnification α in the horizontal direction and the magnification β in the vertical direction can be any positive value of 1 or more, and the enlargement processing unit 160 in FIG. 1 has the same configuration as the reduction processing unit 130. Can also.

FIG. 11 shows the pixel positions and the interpolation data in the original image that are interpolated based on the original image with respect to the pixel positions in the enlarged image when the horizontal magnification α is 3/2. FIG. Position of enlarged image pixel (pixel number)
From the above equation (1), the positions of the original image pixels given to 1, 2, 3, 4, 5, ... are 1, (1 + 2/3), (2 + 1)
/ 3), 3, (3 + ／),... At this time, the interpolation pixel data given to the positions 1, 2, 3, 4, 5,... Of the enlarged image pixel is given by the above equations (2) to (4).
P1, (P1 / 3 + P2 / 2/3), (P2 / 2 /
3 + P3 1/3), P3, (P3 1/3 + P4.2
/ 3), ... That is, the horizontal enlargement processing can be executed using the above equations (1) to (4). In addition, the enlargement in the vertical direction and the enlargement in the horizontal direction and the vertical direction can be similarly executed using the above equations (5) to (8) and (9).

(2) The line buffer unit 320
Although the case where two partial line buffers are used has been described as an example, N line buffers that store image data for 1 / N lines may be used. Even in this case, the sum of the storage capacities of the memories used is the storage capacity of the image data for one line, and the line buffer unit can be configured. Can be realized. Further, the writing and reading operation speed of each of the N line buffers can be set to 1 / N of the speed of the image data input to the line buffer unit. Therefore, a line buffer having a relatively low operation speed can be used. Further, power consumption can be reduced. Note that the partial line buffer can be configured using a memory or a shift register.

(3) In addition, the image interpolation calculation unit 340
The matrix operation of two rows and two columns for realizing the expression (10) is shown as an example, but the present invention is not limited to this.
A filter based on a higher-order matrix operation may be used. Further, an interpolation operation circuit using a spline or a Bezier curve may be used. For example, when interpolating the data of a line between two lines, it is determined whether the image between the two lines is convex upward or downward from the line data above and below. Depending on the result of this decision,
The correction coefficient may be appropriately converted. In this way, more accurate interpolation can be performed.

(4) Although the above embodiment has been described with reference to a projection type display apparatus, the present invention can be similarly applied to various direct-view type or projection type image display apparatuses having an electro-optical device. Here, the electro-optical device used for the display device is not limited to a liquid crystal panel, and various devices that emit light for forming an image in accordance with an image signal can be used. For example, electroluminescence,
FED, plasma display panel, CRT, DMD
Also available.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a projection display apparatus as an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reduction processing unit 130.

FIG. 3 is an explanatory diagram showing an interpolation process in an image interpolation calculation unit 340.

FIG. 4 is a timing chart showing write and read timings of two partial line buffers 322 and 324 executed by a line buffer control unit 326;

FIG. 5 is an explanatory diagram showing pixel positions in an original image and interpolated pixel data which are interpolated based on the original image with respect to the pixel positions in the reduced image.

FIG. 6 is an explanatory diagram showing a line position in an original image and interpolated line data interpolated based on the original image with respect to a line position in the reduced image.

FIG. 7 is an explanatory diagram showing interpolated image data given to each pixel on each line of a reduced image when the image is reduced by a factor of 3/4 in the horizontal direction and the vertical direction.

FIG. 8 is an explanatory diagram showing a method of interpolating a pixel O (x, y).

FIG. 9 is an explanatory diagram showing coefficients K00, K01, K10, and K11 used when the image is reduced by 3/4 in the horizontal and vertical directions.

FIG. 10 is a block diagram illustrating a configuration of an image interpolation calculation unit 340.

FIG. 11 is an explanatory diagram showing pixel positions and interpolation data in an original image that are interpolated based on the original image with respect to the pixel positions in the enlarged image when a horizontal magnification α is set to 3/2. .

FIG. 12 is an explanatory diagram showing a conventional reduction / enlargement processing unit used for reducing or enlarging an image.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 projection display device 110 image conversion unit 120 AD conversion unit 130 reduction processing unit 140 image processing control unit 150 memory 160 enlargement processing unit 170 liquid crystal display driving unit 180 liquid crystal display panel 190 illumination optics System 200 Projection optical system 320 Line buffer unit 322 Partial line buffer 322AD Address data 324 Partial line buffer 324AD Address data 326 Line buffer control unit 340 Image interpolation operation unit 350 Interpolation operation unit 351 Multiplier 355 ... Adder 360 ... Latch unit 362 ... Output buffer unit 1000 ... Reduction / enlargement processing unit 1005 ... Image interpolation calculation unit 1010 ... Line buffer unit 1011,1012,1013 ... Line buffer 1014 ... Line buffer control unit 1020 ... Image interpolation calculator

Continued on front page F-term (reference) EA27 5C082 AA01 AA03 BA34 BB11 CA33 CA34 DA20 MM04

Claims (4)

[Claims] 1. An image processing apparatus for processing original image data representing an original image to create adjusted image data representing an adjusted image obtained by enlarging or reducing the original image, comprising: A line buffer unit that outputs the previous line image data that is the original image data one line before the current line image data, together with the current line image data while accumulating the current line image data that is the original image data; An image interpolation calculation unit that calculates the line image data and the preceding line image data according to a desired enlargement ratio or reduction ratio to generate the adjusted image data, and the line buffer unit includes: The preceding line image data corresponding to 1 / N (N is an integer of 2 or more) pixels of one line of data is stored, respectively. And selecting one of the N partial line buffers while sequentially switching at each pixel timing, and outputting the preceding line image data from the selected partial line buffer; A line buffer control unit that stores the current line image data in the selected partial line buffer. 2. The image processing apparatus according to claim 1, wherein the partial line buffer has a largest number of pixels per line among original image data formats that can be input to the image processing apparatus. An image processing device having a storage capacity of 1 / N or more of the number of pixels for one line in a format and less than one line. 3. A projection display device for projecting and displaying an image, wherein adjusted image data representing an enlarged or reduced adjusted image of the original image is generated by processing the original image data representing the original image. An image processing apparatus, an image display signal generation unit that generates an image display signal based on the adjusted image data, an electro-optical device that emits light that forms an image according to the image display signal, and the electro-optical device A projection optical system for projecting the light emitted from the image processing apparatus, wherein the image processing apparatus stores the current line image data, which is the original image data for one input line, together with the current line image data. A line buffer unit for outputting preceding line image data which is original image data one line before the current line image data; An image interpolation calculating unit that generates the adjusted image data by calculating the preceding line image data according to a desired enlargement ratio or reduction ratio. N partial line buffers for respectively accumulating the preceding line image data corresponding to 1 / N (N is an integer of 2 or more) pixels, and one of the N partial line buffers for one pixel A line buffer controller that outputs the preceding line image data from the selected partial line buffer while switching and selecting the sequential line for each timing, and stores the current line image data in the selected partial line buffer. A projection display device. 4. The projection display device according to claim 3, wherein the partial line buffer is an original image having the largest number of pixels per line among original image data formats that can be input to the image processing device. A projection display device having a storage capacity of 1 / N or more of the number of pixels for one line in a data format and less than one line.