JP2000020449A - Packet type memory system with arithmetic processing function and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system capable of performing more flexible arithmetic processing by issuing a command from a packet type memory LSI with arithmetic processing function while using a command bus and a control method therefor. SOLUTION: The packet type memory bus of the packet type memory system with arithmetic processing function is provided with a ready signal 17 and a bus arbitrate signal 18. Then, the end of arithmetic processing is reported while using the ready signal line 17 and it is arbitrated while using the bus arbitrate signal line 18 whether a command bus 15 is to be occupied by a memory controller LSI 11 or a packet type memory LSI 13 with arithmetic processing function.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a large-capacity memory L
The present invention relates to a packet-type memory LSI having a packet-type memory bus interface suitable for use in an SI, and more particularly to a memory system of a packet-type memory LSI with an arithmetic processing function in which an arithmetic processing function is added to the packet-type memory LSI, and a control method thereof.

[0002]

2. Description of the Related Art Memory LSI and memory L with arithmetic processing function
As a technique for configuring a memory system with an arithmetic processing function using an SI, for example, the description of Japanese Patent Application Laid-Open No. 10-494428 (Japanese Patent Application No. 08-204668) is referred to.

In connection with this technology, in particular, a packet type memory LSI and a packet type memory LS
A technique for constructing a memory system having a similar arithmetic processing function using I is described in Japanese Patent Application No. 09-095787, which was filed prior to the present application and was not disclosed at the time of filing the present application.

Here, the packet type memory LSI is, for example, a Direct Rambus DRAM (referred to as "DRDRAM") or a Synchronous-Link DRAM (Synchronous Link Dynamic Random Access Memory). SLDRAM), which is characterized by performing memory access using packets, and is described in "IEEE Micro" Nov / Dec, 1997, "Direct
Rambus Technology: The Next Main Memory Standar
d ”, pp18-28, and“ SLDRAM: High-Per ”
formance, Open-Standard Memory ", pp. 29-39, has a detailed explanation.

[0005] A packet-type memory LSI with a built-in coprocessor is one in which a coprocessor is mounted inside the LSI of the packet-type memory LSI. In this specification, an LSI having an arithmetic processing function other than the coprocessor is also referred to. This is also referred to as “packet type memory LSI with arithmetic processing function”.

In general, a memory system is configured by arranging a plurality of memory LSIs, and has only a function of storing data used for calculation. On the other hand, the memory system with an arithmetic processing function described in the above-mentioned Japanese Patent Application Laid-Open No. 10-49428 is configured using a memory LSI and a memory LSI with an arithmetic processing function. The arithmetic processing can be performed by a memory LSI with an arithmetic processing function in a memory system.

A packet-type memory system with an arithmetic processing function described in Japanese Patent Application No. 09-095787 is configured using a packet-type memory LSI and a packet-type memory LSI with an arithmetic processing function. Yes,
The above-described mechanism of performing a memory access to a packet-type memory LSI using a packet is extended, and the execution of the arithmetic processing in the packet-type memory LSI with the arithmetic processing function is controlled using the packet. .

[0008]

The memory system described in the above-mentioned prior application uses a conventional memory bus, particularly a packet-type memory bus, as it is, and has a memory system with an arithmetic processing function. A packet-type memory system with functions is configured. this is,
This is for the reasons described below.

In general, in a memory bus, since only a memory controller LSI is permitted to issue a command on the bus, arbitration of the exclusive right of the memory bus is not required. Further, since communication performed on the memory bus is only memory access such as read and write, the number of communication formats is small, and the communication protocol is relatively simple.

As described above, since the protocol is simple, a conventional memory system with an arithmetic processing function using a memory bus has a feature that mutual communication via the memory bus can be executed in a short time.

Since the memory system with the arithmetic processing function is also a system including the function as the conventional memory system, how to reduce the delay time at the time of memory access is in line with the improvement in the data bandwidth. This is a big issue.

For this reason, it can be said that the above features are very well suited as a bus for a memory system with an arithmetic processing function.

However, the memory controller LSI
That only the master can be a bus master means that the memory controller LS
I to perform an interrupt operation to the memory L with an arithmetic processing function.
It means that SI cannot be a bus master.

In order to cause the memory LSI with the arithmetic processing function to execute complicated arithmetic processing, such an interrupt operation is enabled, and not only the memory controller LSI but also the memory LSI with the arithmetic processing function becomes a bus master. Need to be able to

On the other hand, as a system having a plurality of bus masters, there is a bus connection type parallel processing system in which a plurality of processors are connected to one processor bus and perform parallel operations. The communication protocol of the processor bus in the bus connection type parallel processing system is much more complicated than the communication protocol of the memory bus. This is due to several causes.

A first cause is that the processor bus is a bus on the assumption that a plurality of bus masters exist.
That's what it means. For this reason, there is a possibility that a plurality of bus masters issue requests to the processor bus at the same time, and it is necessary to control the exclusive right of the processor bus to determine which bus master can issue the request.

Further, in order to avoid deadlock and livelock, it is necessary to control the flow on the processor bus.

Further, in order to increase the efficiency of parallel processing / distributed processing, it is necessary to support communication formats on many types of buses or communication patterns on many types of buses.

Furthermore, a mechanism such as cache coherency that guarantees data consistency between a plurality of processors may need to be incorporated in the protocol.

As described above, since the communication protocol is complicated, in these systems, although a plurality of bus masters can be tolerated, a problem arises that it takes time for mutual communication via the processor bus.

Accordingly, the present invention has been made based on the recognition of the above technical problems, and its main object is to provide a packet type memory LSI with an arithmetic processing function and a packet type memory system with an arithmetic processing function as a base. An object of the present invention is to provide a more flexible and high-performance memory system with an arithmetic processing function and a control method thereof, which enable a packet-type memory LSI with an arithmetic processing function to be a bus master.

Another object of the present invention is to provide a packet-type memory with the above-mentioned new packet-type memory bus technology.
A packet-type memory LSI with an arithmetic processing function having an external input / output terminal to which several signal lines have been added is realized. The packet-type memory LSI with the arithmetic processing function and the conventional packet-type memory LSI are connected in the same packet. It is an object of the present invention to provide a memory system with an arithmetic processing function that can be used by being connected to a type memory bus, and a control method thereof.

Still another object of the present invention is to provide a memory access to both the packet type memory LSI connected to the packet type memory bus and the packet type memory LSI with the arithmetic processing function by the time by adding the arithmetic processing function. It is an object of the present invention to provide a memory system with an arithmetic processing function that can be realized without any overhead and a control method thereof.

[0024]

According to the present invention, there is provided a packet-type memory system having an arithmetic processing function, which comprises a plurality of packet-type memory LSIs, one packet-type memory LSI having an arithmetic processing function, and one memory controller LSI.
A memory controller LSI, a packet-type memory LSI, and a packet-type memory LS with an arithmetic processing function.
I is connected by a bidirectional data bus and a command bus, and a memory controller LSI and a packet type memory LSI with an arithmetic processing function are connected to the memory controller LSI.
It is connected by a ready signal line, which is a one-way signal line, and a bus arbitration signal line, which is a bidirectional signal line.

Further, the packet type memory system with arithmetic processing function of the present invention has an arithmetic processing function comprising a plurality of packet type memory LSIs, one packet type memory LSI with arithmetic operation function and one memory controller LSI. In a packet type memory system, a memory controller LSI, a packet type memory LSI, and a packet type memory LSI with an operation processing function are connected by a bidirectional data bus and a command bus, and a memory controller LSI and an operation processing function Packet type memory LSI
A configuration in which the ready signal line and the memory controller interrupt signal line, which are one-way signal lines toward the memory controller LSI, and the packet-type memory interrupt signal line with an arithmetic processing function, which is a one-way signal line from the memory controller LSI, may be used. Good.

The method of controlling a packet-type memory system with an arithmetic processing function according to the present invention uses a bus arbitration signal line to transfer a packet-type memory LSI with an arithmetic processing function from a memory controller LSI to a packet-type memory LSI with an arithmetic processing function. Requests the transfer of the command bus occupation right to the memory controller LSI.

According to the method of controlling a packet type memory system with an arithmetic processing function of the present invention, the right to occupy a command bus is changed from a memory controller LSI using a memory controller interrupt signal line.
And requesting transfer of the command bus occupation right from the packet-type memory LSI with arithmetic processing function to the memory controller LSI using the packet-type memory interrupt signal line with arithmetic processing function.

Further, the control method of the packet type memory system with the arithmetic processing function of the present invention
When the packet-type memory LSI with the processing function requests the transfer of the command-bus occupation right while the I has the command-bus occupation right, the command bus is transferred from the memory controller LSI to the packet-type memory with the processing function. By transmitting the exclusive right transfer command packet using this command, the exclusive right of the command bus is transferred to the packet type memory LSI with the arithmetic processing function.

Further, according to the control method of the packet type memory system with arithmetic processing function of the present invention, when the packet type memory LSI with arithmetic processing function has the exclusive right to the command bus, the memory controller LSI transfers the exclusive right to the command bus. Is transmitted from the packet-type memory LSI with the arithmetic processing function to the memory controller LSI using the command bus, thereby transferring the occupation right of the command bus to the memory controller LSI.

In the packet-type memory system with an arithmetic processing function of the present invention, the packet-type memory LSI has a unique device ID,
The SI has a unique device ID, and the memory controller LSI has a unique device ID.

Further, according to the control method of the packet type memory system with the arithmetic processing function of the present invention, when the packet type memory LSI with the arithmetic processing function acquires the occupation right of the command bus, a device ID unique to the memory controller LSI is obtained.
Is used to specify a memory controller LSI, and a command packet is transmitted to the memory controller LSI.

Further, according to the control method of the packet type memory system with an arithmetic processing function of the present invention, the packet type memory LSI with the arithmetic processing function completes the arithmetic processing using the ready signal line, Type memory L
The fact that the transfer of occupation rights of the SI can be transferred from the packet type memory LSI with the arithmetic processing function to the memory controller LS
Notify I.

[0033]

Embodiments of the present invention will be described. A preferred embodiment to which the present invention is applied will be described. A plurality of packet type memory LSIs (1 in FIG. 1)
2-1 to 12-3), a packet type memory LSI with an arithmetic processing function (13 in FIG. 1), and a memory controller LSI
(11 in FIG. 1) and a memory controller LSI
And a plurality of packet-type memory LSIs and a packet-type memory LSI with an arithmetic processing function are connected by a bidirectional data bus (FIG. 1).
14) and a command bus (15 in FIG. 1), and the memory controller LSI and the packet type memory LSI with the arithmetic processing function are ready signal lines (FIG. 1) which are one-way signal lines toward the memory controller LSI. 17)
And a bus arbitration signal line which is a bidirectional signal line (18 in FIG. 1)
The bidirectional bus arbitration signal line (18 in FIG. 1) is used to connect the memory controller LSI to the packet-type memory LSI with the arithmetic processing function or from the packet-type memory LSI with the arithmetic processing function. It requests the transfer of the command bus occupation right to the memory controller LSI.

Memory controller LSI (11 in FIG. 1)
Has exclusive control of the command bus (15 in FIG. 1),
Packet type memory LSI with arithmetic processing function (13 in FIG. 1)
Sends an exclusive right transfer command packet from the memory controller LSI to the packet type memory LSI with an arithmetic processing function using the command bus, thereby requesting exclusive transfer of the command bus. The right is transferred to the packet-type memory LSI with the arithmetic processing function.

On the other hand, a packet type memory L with an arithmetic processing function
When the memory controller LSI (11 in FIG. 1) requests transfer of the command bus occupancy while the SI (13 in FIG. 1) has the occupation right of the command bus (15 in FIG. 1),
The occupation right of the command bus is transferred to the memory controller LSI by transmitting an occupation right transfer command packet from the packet type memory LSI with arithmetic processing function to the memory controller LSI using the command bus. Hereinafter, the present invention will be described in more detail with reference to first to third embodiments.

[0036]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a packet type memory system with an arithmetic processing function according to the present invention. Referring to FIG. 1, a packet-type memory system 1 with an arithmetic processing function includes a memory controller LSI 11
And a plurality of packet-type memory LSIs 12-1 to 12-3
And one packet-type memory LSI 13 with an arithmetic processing function
And is provided. Memory controller LS
I11 and packet type memory LSIs 12-1 to 12-
3. The memory controller LSI 11 and the packet-type memory LSI 13 with an arithmetic processing function are connected by a bidirectional data bus 14, a command bus 15, and a bidirectional clock signal line 16, respectively.

The packet-type memory system described in Japanese Patent Application No. 09-09758 or Japanese Patent Application No. 8-20
In the packet type memory system with arithmetic processing function described in No. 4668, the command bus 15 is a one-way type bus from the memory controller LSI 11, but in the packet type memory system with arithmetic processing function in this embodiment, The bus 15 is a bidirectional bus.

Further, the memory controller LSI 11 and the packet type memory LSI 13 with an arithmetic processing function are connected to the one-way ready signal line 1 toward the memory controller LSI 11.
7 and a bidirectional bus arbitration signal line 18.

The ready signal line 17 is a signal line used by the packet type memory LSI 13 with an arithmetic processing function to notify the memory controller LSI 11 of the end of the arithmetic processing.

The bus arbitration signal line 18 is a signal line used to arbitrate which of the memory controller LSI 11 and the packet type memory LSI 13 with an arithmetic processing function has the occupation right of the command bus 15.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the configuration of the packet type memory system with an arithmetic processing function according to the present invention.

Referring to FIG. 2, a packet-type memory system 2 having an arithmetic processing function includes a memory controller LSI 2
1 and a plurality of packet type memory LSIs 12-1 to 12-
3 and one packet-type memory LSI 2 with an arithmetic processing function
3 is provided.

The memory controller LSI 21 and the packet type memory LSIs 12-1 to 12-3, and the memory controller LSI 21 and the packet type memory LSI 23 with an arithmetic processing function are respectively connected to the bidirectional data bus 14 and command bus 15, Are connected by a clock signal line 16.

Further, the memory controller LSI 21 and the packet type memory LSI 23 with the arithmetic processing function are provided with a one-way ready signal line 17 toward the memory controller LSI 21, a memory controller interrupt signal line 28, and a one-way from the memory controller LSI 21. They are connected by a packet type memory interrupt signal line 29 with an arithmetic processing function.

The ready signal line 17 is a signal line used by the packet type memory LSI 23 with an arithmetic processing function to notify the memory controller LSI 21 of the end of the arithmetic processing. Also, the controller interrupt signal line 28
Is a signal line used by the packet type memory LSI 23 with an arithmetic processing function to interrupt the memory controller LSI 21. On the contrary, the packet type memory interrupt signal line 29 with the arithmetic processing function is connected to the memory controller LS
I21 is a signal line used to interrupt the packet type memory LSI 23 with an arithmetic processing function.

The packet type memory LSI of the above-mentioned prior application or the packet type memory L with arithmetic processing function
In SI, the command bus 15 is connected to the memory controller L
Although the bus is a one-way bus from the SI 11, the command bus 15 is a bidirectional bus in the packet-type memory system with an arithmetic processing function in the present embodiment.

Next, the operation of the embodiment of the packet type memory system with arithmetic processing function of the present invention shown in FIGS. 1 and 2 will be described.

From the memory controller LSI 11 (21, the parentheses indicate the reference numerals in FIG. 2) using the data bus 14 and the command bus 15, the packet type memory LSI 12
Or a packet type memory LSI 13 with an arithmetic processing function
The memory access to (23) and the operation request access to the packet type memory LSI 13 (23) with the operation processing function using the data bus 14 and the command bus 15 are described in Japanese Patent Application No. 09-097587. Therefore, the description is omitted.

In these packet type memory systems with arithmetic processing functions, the memory controller LSI 11
(21) has the command bus occupation right (that is, it is a bus master), and can freely issue command packets to the command bus 15.

Packet type memory LSI 1 with arithmetic processing function
3 (23) become bus masters in the following manner, and can issue command packets to the command bus 15.

In FIG. 1, the bus arbitration signal line 18
It is assumed that the signal line is active low (active at low level). That is, the memory controller LSI 11
In a state where the packet type memory LSI 13 with the arithmetic processing function is not driving the bus arbitration signal line 18, the bus arbitration signal line 18 is in a high state, and the memory controller LSI 11 or the packet type with the arithmetic processing function When one of the memory LSIs 13 drives the arbitration signal line 18, the bus arbitration signal line 18 is in a low state.

When the packet-type memory LSI 13 with an arithmetic processing function drives the bus arbitration signal line 18 low while the memory controller LSI 11 is a bus master, the memory controller LSI 11 It is determined that the LSI 13 requests the occupation right of the command bus 15.

The memory controller LSI 11 sends an exclusive right transfer command packet via the command bus 15 to the
The occupation right of the command bus 15 is transferred to the packet type memory LSI 13 with the arithmetic processing function by sending the packet type memory LSI 13 with the arithmetic processing function.

Conversely, the packet type memory L with the arithmetic processing function
When the memory controller 11 drives the bus arbitration signal line 18 low in a state where the SI 13 is the bus master, the packet type memory LSI 13 with the arithmetic processing function requests the occupation right of the command bus 15 by the memory controller LSI 11. And judge. The packet-type memory LSI 13 with the arithmetic processing function transfers the occupation right of the command bus 15 to the memory controller LSI 11 by sending an occupation right transfer command packet to the memory controller LSI 11 via the command bus 15.

In FIG. 2, it is assumed that the memory controller interrupt signal line 28 and the packet type memory interrupt signal line 29 having an arithmetic processing function are active-low signal lines. That is, when the memory controller LSI 21 is not driving the packet type memory interrupt signal line 29 with the arithmetic processing function and the packet type memory LSI 23 with the arithmetic processing function is not driving the memory controller interrupt signal line 28, the respective signal lines are high. The signal line is in the (High) state, and the memory controller LSI 21 or the packet-type memory LSI 23 with the arithmetic processing function drives each signal line, so that each signal line is in a low state.

In a state where the memory controller LSI 21 is the bus master, the packet type memory LSI 23 with the arithmetic processing function is connected to the memory controller interrupt signal line 28.
Is driven low, the memory controller LSI 21
Judge that the packet-type memory LSI 23 with the arithmetic processing function requests the occupation right of the command bus 15.
The memory controller LSI 21 transfers the occupation right transfer command packet to the packet type memory LSI 23 with arithmetic processing function via the command bus 15, thereby transferring the occupation right of the command bus 15 to the packet type memory LSI 23 with arithmetic processing function.

Conversely, the packet type memory L with the arithmetic processing function
When the memory controller LSI 21 drives the packet-type memory interrupt signal line 29 with the arithmetic processing function low while the SI 23 is the bus master, the memory controller LSI 21 occupies the command bus 15 in the packet-type memory LSI 23 with the arithmetic processing function. It is determined that the right has been requested.

Packet type memory LSI 2 with arithmetic processing function
3 transfers the exclusive right of the command bus 15 to the memory controller LSI 21 by sending an exclusive right transfer command packet to the memory controller LSI 21 via the command bus 15.

FIG. 3 is a block diagram showing the configuration of the third embodiment of the configuration of the packet type memory system with an arithmetic processing function according to the present invention. With reference to FIG.
This is an extension of the first embodiment described with reference to FIG. Similarly, the second embodiment shown in FIG. 2 can be extended to the configuration of this embodiment.

Referring to FIG. 3, in the present embodiment,
The packet-type memory LSIs 12-1 to 12-3 have unique device IDs 302-1 to 302-3, respectively, and the packet-type memory LSI 13 with an arithmetic processing function has two unique device IDs 303-1 and 303-2. .

Here, the packet type memory LSI 13 with the arithmetic processing function has two device IDs 303-1 and 303-.
As described in Japanese Patent Application No. 09-097587, the transmission of the command packet is performed by distinguishing the memory unit and the arithmetic processing unit in the packet-type memory LSI 13 with the arithmetic processing function from each other. , Device ID 303-1 for the memory unit, and device ID for the arithmetic processing unit
This is because 303-2 is provided separately.

The device ID is used for identifying the command target by giving the device ID of the device which is the target of the command in the command packet. In FIG. 3, the device ID 303-of the memory unit in the packet-type memory LSI 13 with the arithmetic processing function
Since the value of 1 is “4”, for example, if a command packet is sent with the device ID value being “4”, the command will target the memory unit in the packet-type memory LSI 13 with the arithmetic processing function. Become.

In FIG. 3, the memory controller LS
I11 also has a device ID 301. Thus, the device ID 3 is also stored in the memory controller LSI 11.
01, when the packet-type memory LSI 13 with the arithmetic processing function secures the occupation right of the command bus, the memory controller LSI 11 and the packet-type memories LSI 12-1 to 12- 3, it is possible to transmit a command packet to both of them.

This is realized by giving the target device ID in the command packet.

Further, as described above, the packet type memory LSI 13 having the arithmetic processing function is transferred from the memory controller LS
When it is necessary to transmit an exclusive right transfer command packet to I11, the device ID 301 of the memory controller LSI 11 is included in the exclusive right transfer command packet, so that the packet-type memory L
From SI13 to the memory controller LSI11,
The exclusive right transfer command packet can be transmitted.

In each embodiment described with reference to FIGS. 1 to 3, the ready signal line 17 is used for notifying the end of the arithmetic processing of the packet type memory LSI 13 with the arithmetic processing function. For example, the memory controller LSI 11
If (21) has the exclusive right to the command bus 15, the packet-type memory LSI 13 (2
3) sends a ready signal to the memory controller LSI 11 (21) to notify that the next arithmetic processing request command can be accepted.

The packet type memory L with the arithmetic processing function
When the SI 13 (23) has the occupation right of the command bus 15, the packet type memory LSI 1
3 (23) sends a ready signal to the memory controller LSI 11 (21), so that the packet-type memory LSI 13 (23) with an arithmetic processing function can accept an interrupt from the memory controller LSI 11 (21), and the command bus It is possible to notify that the occupation right of the 15 can be transferred to the memory controller LSI 11 (21).

[0068]

As described above, according to the present invention,
A packet-type memory LSI with an arithmetic processing function can issue a command using a command bus, thereby enabling much more flexible arithmetic processing than the system described in the prior application. And an effect is obtained.

More specifically, according to the present invention, the packet type memory LSI with the arithmetic processing function in the packet type memory system with the arithmetic processing function is replaced with the packet type memory LSI in the same packet type memory system with the arithmetic processing function. A memory access command to read and write data, and interrupt a memory controller LSI from a packet-type memory LSI with an arithmetic processing function to request processing or to transfer data. Or request.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a third exemplary embodiment of the present invention.

[Explanation of symbols]

11, 21 Memory controller LSI 12 Packet type memory LSI 13, 23 Packet type memory LSI with arithmetic processing function 14 Data bus 15 Command bus 16 Clock signal 17 Ready signal 18 Bus arbitration signal line 29 Packet type memory interrupt signal line with arithmetic processing function 301, 302, 3031, 3032 Device ID

Claims (11)

[Claims] 1. A packet-type memory system with an arithmetic processing function, comprising at least: a plurality of packet-type memory LSIs; one packet-type memory LSI with an arithmetic processing function; and one memory controller LSI. LSI, the packet-type memory LSI, and the packet-type memory LS with an arithmetic processing function
I is connected by a bidirectional data bus and a command bus, and the memory controller LSI and the packet type memory LSI with the arithmetic processing function are one-way signal lines leading to the memory controller LSI. A packet type memory system with an arithmetic processing function, which is connected by a signal line and a bus arbitration signal line which is a bidirectional signal line. 2. A packet-type memory system having an arithmetic processing function, comprising at least: a plurality of packet-type memory LSIs; one packet-type memory LSI with an arithmetic processing function; and one memory controller LSI. LSI, packet-type memory LSI, and packet-type memory LS with arithmetic processing function
I is connected by a bidirectional data bus and a command bus, and further, the memory controller LSI and the packet type memory LSI with the arithmetic processing function are ready signals which are one-way signal lines toward the memory controller LSI. And a memory controller interrupt signal line, and a packet type memory interrupt signal line having an arithmetic processing function which is a one-way signal line from the memory controller LSI. Memory system. 3. A memory device comprising: a plurality of packet-type memory LSIs; one packet-type memory LSI with an arithmetic processing function; and one memory controller LSI. Packet type memory LS with processing function
I are connected by a bidirectional data bus and a command bus, and further, the memory controller LSI,
The packet type memory LSI with the arithmetic processing function is connected to a ready signal line as a one-way signal line toward the memory controller LSI and a bus arbitration signal line as a bidirectional signal line. A method of controlling a packet-type memory system, comprising: using the bus arbitration signal line to transmit a packet-type memory LSI with an arithmetic processing function from the memory controller LSI.
Or the packet type memory L with the arithmetic processing function
A method of controlling a packet-type memory system with an arithmetic processing function, comprising requesting transfer of occupation right of the command bus from an SI to the memory controller LSI. 4. At least a plurality of packet-type memory LSIs, one packet-type memory LSI with an arithmetic processing function, and one memory controller LSI, wherein the memory controller LSI, the packet-type memory LSI, Packet type memory LS with arithmetic processing function
I are connected by a bidirectional data bus and a command bus, and the memory controller LSI and the packet-type memory LSI with an arithmetic processing function are ready signal lines which are one-way signal lines toward the memory controller LSI. A signal line, and a memory controller interrupt signal line;
A method for controlling a packet-type memory system with an arithmetic processing function, which is connected by a packet-type memory interrupt signal line with an arithmetic processing function, which is a one-way signal line from the memory controller LSI, wherein the memory controller interrupt signal line is The occupation right of the command bus is transferred to the memory controller LSI
Requesting the transfer of the command bus from the packet-type memory LSI with the arithmetic processing function using the packet-type memory with the arithmetic processing function interrupt signal line. Requesting a transfer to the memory controller LSI. 5. When the packet type memory LSI with the arithmetic processing function requests transfer of the occupation right of the command bus while the memory controller LSI has the occupation right of the command bus, the memory controller LSI sends the command operation to the command bus. For packet type memory LSI with processing function,
5. The occupation right of the command bus is transferred to the packet-type memory LSI with the arithmetic processing function by transmitting an occupation right transfer command packet using the command bus. 6. For controlling a packet-type memory system with an arithmetic processing function. 6. The packet type memory LS with an arithmetic processing function.
When the memory controller LSI requests the transfer of the command bus occupation right while I has the command bus occupation right, the packet-type memory LSI with the arithmetic processing function sends the command bus to the memory controller LSI.
5. The arithmetic processing function according to claim 3, wherein the exclusive right of the command bus is transferred to the memory controller LSI by transmitting an exclusive right transfer command packet using the command bus. A control method for a packet type memory system. 7. The packet type memory LSI, the packet type memory LSI with arithmetic processing function, and the memory controller LSI, each having a unique device ID (identification information). Packet type memory system with arithmetic processing function. 8. The packet type memory LS with an arithmetic processing function.
I is a device I unique to each of the memory unit and the arithmetic processing unit
The packet-type memory system according to claim 7, further comprising D (identification information). 9. The packet type memory LSI with arithmetic processing function, wherein the packet type memory LSI, the packet type memory LSI with arithmetic processing function, and the memory controller LSI each have a unique device ID (identification information).
When the SI acquires the command bus occupation right, the device I
5. The method according to claim 3, wherein the memory controller LSI is designated using D, and a command packet is transmitted to the memory controller LSI. 10. The packet-type memory LSI with an arithmetic processing function using the ready signal line to complete the arithmetic processing, or
5. The packet with an arithmetic processing function according to claim 3, wherein the packet type memory LSI with the arithmetic processing function notifies the memory controller LSI that the transfer of the occupation right of the SI is possible. Control method for a portable memory system. 11. A packet-type memory system with an arithmetic processing function, comprising: a plurality of packet-type memories; a packet-type memory with an arithmetic processing function; and a memory controller, wherein the plurality of packet-type memories and the arithmetic processing A packet-type memory with a function, connected to the memory controller by a common bus, for transmitting and receiving a request signal for transfer of the occupation right of the bus between the memory controller and the packet-type memory with the arithmetic processing function; At least a dedicated signal line is used, and the bus is used for a side of the memory controller and the packet-type memory with an arithmetic processing function, which has requested transfer of the bus occupation right from a bus master having the bus occupation right. Characterized in that it is configured to notify the transfer of the exclusive right by using a packet type memory with an arithmetic processing function. Stem.