JP2000020348A - Simulation device and computer readable recording medium storing simulation program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute the integrated logical verification of software corresponding to various parallel operation timing of a system constitution element by providing a simulation device with a means for changing the parallel operation timing of the system constitution element and freely changing the prallel operation timing of the element to be operated in parallel synchronously with a instruction execution process of a CPU. SOLUTION: A CPU simulation device 1 tries an instruction execution process of a real CPU on a host CPU different from the real CPU. A parallel operation element 7 executes parallel operation synchronously with the instruction execution process. A scheduler 9 executes the reception of registration/deletion requests of a time event and the control of the monitor/execution of the events from the device 1 and the element 7. An operation timing changing means 11 changes the operation timing of the element 7. In the case of changing the timing of the element 7, parameters such as a frequency division value and a difference are inputted to the means 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU for actually incorporating software operations such as embedded software.
The present invention relates to a simulation apparatus for testing on a CPU (hereinafter, abbreviated as a host CPU) different from a real CPU (hereinafter, abbreviated as a host CPU) and a computer-readable recording medium on which a simulation program is recorded. The present invention relates to a technology that enables an operation test of software corresponding to various parallel operation timings by making the parallel operation timing with a CPU variable.

[0002]

2. Description of the Related Art A software simulation device (hereinafter, abbreviated as a simulation device) includes a host CPU.
For the purpose of testing the operation of software on a real CPU, it is widely used in recent years for the development of embedded software and the like.

[0003] Generally, a simulation device is a CP
It is possible to not only simulate the instruction set of U, but also perform the logic verification of the module in the software related to the operation of the input / output device attached to the system and the integrated logic verification of the whole software with external input as disturbance. In order to achieve this, a system component that operates in parallel in synchronization with the instruction execution process of the CPU is provided inside the simulation device, and the system configuration includes a peripheral I / O device and a peripheral I / O device including an external environment on the host CPU. It is a mechanism that can reproduce the environment.

[0004] The system configuration and operation of a typical simulation apparatus will be described below with reference to FIGS. 4 to 6.

First, a system configuration of a conventional simulation apparatus will be described with reference to FIG.

The conventional simulation device includes a CPU simulation device 1 for simulating an instruction execution process of a CPU, an address management unit 3 for mapping a memory access event function to a CPU address, and a memory simulation device 5 for simulating a memory operation. CPU by CPU simulation device 1
Parallel operation element 7 that operates in parallel in synchronization with the instruction execution process of
And reception of requests for registration / deletion of time events from the CPU simulation device 1 and the parallel operation element 7.
A scheduler 9 for monitoring and executing events is provided, and the parallel operation element 7 includes a peripheral I / O device, an external environment simulation device, and the like.

Further, the scheduler is composed of a plurality of event tables 15 registered from system components as shown in FIG.
Reference numeral 5 includes a counter field 15a for storing time information of system components, an event information field 15b for storing event information, and a field 15c indicating the next event table. Here, the event information means information on a time event that each system component has in advance.

In the above simulation apparatus, a scheduler in the simulation apparatus manages operations of other system components. Therefore, hereinafter, the operation of the simulation device will be described focusing on the operation of the scheduler.

When the system components operate, each system component registers event information in the scheduler when an event occurs. When the scheduler receives an event registration request from a system component, the scheduler adds an event table containing event information requested from the system component, and reconfigures the inside of the scheduler.
Then, the registered event tables are linked by a chain, and an event table to be executed first is specified. Further, the time to be executed first from the present time is determined from the designated event table, and the determined time information is stored in the counter field of each event table.

As described above, prior to execution of the simulation, the time event of the system component is registered in the scheduler.

Next, the operation of the simulation after the registration of the time event from the system component will be described.
A description will be given by taking as an example the case where the instruction content is an access instruction to an I / O device to which memory mapping is performed.

FIG. 6 is a flowchart for explaining the operation of one instruction by the conventional simulation device.

When the instruction content is an instruction to access a memory-mapped I / O device, a memory access event is indirectly activated, and as described above, the I / O device, which is a system component, generates a time event. Register with the scheduler. When a time event is registered, the scheduler
PU instruction set simulation execution (step S1)
Thereafter, elapsed time information is obtained from the CPU simulation device, and it is monitored whether or not a predetermined elapsed time for executing the registered time event has been reached (step S2).
In this monitoring routine, the scheduler executes the registered event when the time to execute the registered event has been reached (step S3) (step S4).
After executing the event, the counter in the event table,
The contents of the event field are updated (step S
5) After the event ends, the process proceeds to the next event based on the information in the event table (step S6).

As described above, the time event of the system component is registered in the scheduler, and its execution is always started with reference to the CPU instruction time, and the consistency of the logical state inside the CPU before and after the CPU executes the instruction. Secured. That is, a simulation is performed in which system components operate in parallel in synchronization with the CPU instruction execution unit.

[0015]

The system components in the conventional simulation apparatus are configured to operate in synchronization with the execution of instructions by the CPU. However, the fact that the system components always perform the same operation at the same timing and at the same place as described above is a serious problem that the simulation accuracy is reduced unless the environment reproduced on the host CPU is exactly the same as that of the real CPU. cause.

For example, if the cache is not accurately simulated, and if instructions involving memory accesses are frequently consecutive, the number of clocks required for processing the instruction may be reduced to the actual C number.
It is estimated more than that of PU.

Further, when a timer simulation device that operates in synchronization with an instruction is provided, a timer interrupt occurs at intervals shorter than the actual number of instructions.
Such a problem can also occur when the simulation of the pipeline, the weight of the memory, or the like is not accurately performed.

That is, in the conventional simulation apparatus, as long as the system components always perform exactly the same operation at the same timing and at the same place, the range in which the software operation on the actual CPU can be tried on the host CPU is very narrow. , The operation cannot be accurately estimated.

As one means for solving this problem, a method of manufacturing a simulation device that operates with exactly the same timing and accuracy as in an actual environment can be considered.
Producing a simulation device that is suitable for only one environment is problematic in terms of producing a versatile simulation device, and furthermore, producing such a simulation device is a technology at this stage. Very difficult.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a simulation apparatus capable of changing the operation timing of a CPU of a system component for executing an instruction and a computer readable recording of a simulation program. It is to provide a recording medium.

[0021]

In order to solve the above-mentioned problems, the features of the simulation apparatus and the computer-readable recording medium storing the simulation program of the present invention are as follows. A CPU simulation device for testing an instruction execution process, a simulation device having a system component that operates in parallel in synchronization with the instruction execution process, and a computer-readable recording medium on which a simulation program is recorded; There is provided means for changing the parallel operation timing.

(Operation) In the present invention, the parallel operation timing of the system components which operate in parallel in synchronization with the instruction execution process of the CPU can be freely changed.
Comprehensive logic verification of software corresponding to various parallel operation timings of system components can be performed.

[0023]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 1 is a block diagram showing a system configuration of a simulation apparatus embodying the present invention.

The system of the simulation apparatus according to the present invention has a CP
U simulation device 1, an address management unit 3 that maps a memory access event function to a CPU address, a memory simulation device 5 that simulates the operation of a memory, and a parallel operation element 7 that operates in parallel in synchronization with the instruction execution process of the CPU A scheduler 9 for receiving a registration / deletion request of a time event from the CPU simulation device 1 and the parallel operation element 7 and controlling the monitoring and execution of the event; and changing the operation timing of the parallel operation element 7 The parallel operation element 7 includes a peripheral I / O
It consists of a device and an external environment simulation device.

When changing the timing of the parallel operation elements, parameters to be described later are input to the operation timing changing means 11. The parallel operation timing of the parallel operation element can be freely changed by the parameter input.
Hereinafter, parameters that can be input from the operation timing changing unit 11 and their functions will be described.

(A) Divided value M (M> 0) By giving the divided value M, the cycle of the operation timing of the parallel operation element can be changed. For example, when a positive integer is specified for the frequency division value M, the cycle of the parallel operation timing becomes M times longer. On the other hand, when a positive fraction is specified, the period is shortened by M times.

(B) Difference N By giving the difference N, the phase of the operation timing of the parallel operation element can be changed. For example, the difference N
, A parallel operation timing is delayed by N simulation time units as a whole. On the other hand, when a negative number is specified, the parallel operation timing is generally faster by | N | simulation time unit.

(C) Distribution function (mean value μ, standard deviation σ,
Probable variable X) By specifying a distribution function using the average value μ, the standard deviation σ, and the random variable X, a frequency division value or a difference is arbitrarily given based on the distribution function.

(D) Combination of (a), (b), and (c) By combining the above methods (a), (b), and (c), the frequency division value and the difference are obtained, and the parallel operation timing is changed. .

(E) User-defined formula Using a function composed of arbitrary parameters, a frequency division value and a difference are obtained, and the parallel operation timing is changed.

The change of the parallel operation timing is realized by changing the method of updating the value of the counter field of the event table in the scheduler. Hereinafter, the principle will be described.

As described in the prior art, the content of the conventional counter field is used by directly registering the time information from the system components. Therefore, in the present invention, the time information in the counter field is changed by giving a parameter from the operation timing changing means.

For example, when the dividing value M is given by the operation timing changing means, a value obtained by multiplying the time information by the dividing value is registered in the counter field.

That is, (i) When the division value M is given: Counter field value = (time information) × (division value M).

On the other hand, (ii) when the difference N is given, the counter field value = (time information) + (difference N) (iii) when both the frequency division value M and the difference N are given, the counter field value = (time information) × (divided value M)
+ (Difference N) (iv) When a distribution function is given Counter field value = time information, average value μ, standard deviation σ, and a value generated by generating a random number for random variable X.

As described above, according to the present method, the value of the counter field of the event table in the scheduler can be changed regardless of the operation of the CPU.
Thereby, the operation timing of the system components operating in parallel with the CPU simulation device can be freely changed.

In this embodiment, the operation timings of all the system components change according to the parameter designation. However, identification numbers are assigned to the respective system components, and the identification numbers are changed via the operation timing changing means. By specifying, the operation timing can be changed for each system component.

The simulation program is:
It can be stored in a computer-readable recording medium. Here, the recording medium includes a device capable of recording a simulation program, such as a memory device, a magnetic disk device, and an optical disk device.

[Experimental Examples] Hereinafter, experimental results will be shown in which the operation timing of system components that operate in parallel in synchronization with the execution of instructions by the CPU is changed using a simulation apparatus embodying the present invention.

FIG. 2 is a timing chart showing the result of using the simulation apparatus of the present invention to change the parallel operation timing of the system components that operate in parallel with the instruction execution of the CPU in a cycle of 100 simulation time units.

In FIG. 2, the abscissa represents the simulation time, and the point where the chevron-shaped waveform appears indicates the point where the system component operates.

In a conventional simulation device,
Although the original operation cycle of the system components (FIG. 2A), ie, 100 simulation time units, could not be changed, according to the present invention, as described in the previous section,
By specifying a frequency division value or a difference, the operation timing can be changed.

For example, when 2 is specified as a positive integer for the frequency division value M, the operation cycle of the system component is as shown in FIG.
The period becomes longer as shown in the waveform shown in FIG.
0 simulation time unit. Conversely, when a positive fraction 1/2 is specified for the frequency division value M, the operation cycle of the system component becomes shorter as shown in the waveform of FIG. 50 simulation time units.

On the other hand, when -5 is specified for the difference N,
As shown in FIG. 2D, the operation cycle of the system components shifts the operation timing as a whole to the left by 5 simulation time units. That is, the operation starts five simulation time units earlier. At this time, if the frequency division value M is further designated as 2, the operation cycle of the system component is shifted to the left by 5 simulation time units as a whole with 200 operation time units being doubled (FIG. 2 (e)). )).

Further, the value of the dividing value M is added to the average value μ = 1.0.
When a distribution function with 0, standard deviation σ = 0.10, and random variable X = 0.03 is specified, parallel operation is performed with an arbitrary frequency division value M according to the distribution probability in the range of M ≦ X. (FIG. 2F).

FIG. 3 is a timing chart showing the result of changing the parallel operation timing of the system components operating at a cycle of 150 simulation time units using the simulation apparatus of the present invention.

As in FIG. 2, the abscissa represents the simulation time, and the point where the chevron-shaped waveform appears indicates the point where the system component operates. The designated parameter values were the same as the experimental results shown in FIG.

As can be seen from FIG. 3, the timing of the parallel operation can be changed even when a plurality of waveforms are included in one cycle.

[0050]

According to the present invention, there is provided a system component, such as a peripheral I / O device or an external environment simulation device, which can arbitrarily change the operation timing of a system component that operates in parallel in synchronization with the instruction execution process of the CPU. Comprehensive logic verification of software covering various parallel operation timings can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of a simulation device embodying the present invention.

FIG. 2 is a diagram showing a change in operation timing of a system component according to the present invention.

FIG. 3 is a diagram showing a change in operation timing of a system component according to the present invention.

FIG. 4 is a block diagram showing a system configuration of a conventional simulation device.

FIG. 5 is a diagram showing a system configuration of a conventional scheduler.

FIG. 6 is a flowchart for explaining an instruction execution control process by the scheduler.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU simulation apparatus 3 Address management part 5 Memory simulation apparatus 7 Parallel operation element 9 Scheduler 11 Operation timing change means 13 System component 15 Event table 15a Counter field 15b Event information

Claims (4)

[Claims] 1. A simulation device comprising: a CPU simulation device for testing an instruction execution process of a real CPU on a host CPU different from the real CPU; and a system component that operates in parallel in synchronization with the instruction execution process. A simulation device comprising means for changing a parallel operation timing of the system components. 2. The simulation device according to claim 1, further comprising: a scheduler configured to receive a registration / deletion request of a time event from the CPU simulation device and the system component, and to control monitoring and execution of the event. The simulation apparatus, wherein the change of the timing of the parallel operation is performed by changing time information of the system component registered in the scheduler. 3. A function of trying an instruction execution process of the real CPU on a host CPU different from the real CPU, a function of trying an operation of a system component that operates in parallel in synchronization with the instruction execution process, and A computer-readable recording medium on which a simulation program is recorded, wherein the computer realizes a function of changing a parallel operation timing of a component. 4. A computer having a scheduling function for controlling reception of a time event registration / deletion request from the real CPU and the system component, and monitoring / execution of an event, and changing a parallel operation timing of the system component. Is
4. A computer-readable recording medium according to claim 3, wherein the scheduling function is performed by changing time information of the system components.