JP2003015965A - Test system in symmetric multi-processor environment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test system automatically generating a command row generating an access to a memory by same timing from a plurality of processors in a symmetric multi-processor sharing a memory. SOLUTION: A test program has test environment setting process, a command simulator generating an expectation value, test command row performance trace information generating processing, result comparison processing, coverage information storing processing of a test command, and generating processing of a test command row, the test command row is generated in parallel every processor, a kind of an issuing memory access and an address and the number of estimation performance command cycles are accumulated to coverage information, the coverage information is referred by command generation of the processor side, the test command equivalent to the number of the performance command cycles of the processor side of an existing component is selected, and the test command row conflicting the access is generated for the memory of the address by the same timing from the plurality of the processors.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention shares memory.
The present invention relates to a test method on a Symmetric Multi processor, and more particularly to a method for testing reading and writing of data from a plurality of processors to a memory at the same timing.

[0002]

2. Description of the Related Art In a method of executing a test program on a Symmetric Multi processor, a test instruction sequence is generated individually for each processor, so that access competition to a memory at the same address at the same timing as other processors, and Writing to memory from each processor
The realization of a test instruction sequence has been left to execution for a long time in order to cause various operations such as reading to compete at the same timing.

Therefore, the case of accessing the memory of the same address at the same timing of the test instruction sequence of each instruction processor and the case of competing various operations such as writing / reading to the memory at the same timing depend on randomness. Therefore, the frequency of occurrence is low and it depends on the timing of instruction execution from each processor.

Further, Japanese Patent Application No. 7-99206 discloses Symmet.
A method has been disclosed in which each instruction processor in a computer system with a ric Multi processor configuration issues a test instruction sequence at the same time, but it is difficult to apply this method when a large number of memory access instructions are executed by each instruction processor. Is.

[0005]

In the prior art, since the test instruction sequence is independently generated for each processor, access competition with respect to the memory of the same address at the same timing as the other processors, and from each processor. Since various operations such as writing / reading to and from the memory compete with each other at the same timing, the probability of occurrence of a test instruction sequence is low. Therefore, it is possible that each processor cannot generate a test instruction sequence to compete at the same timing.

For this reason, when a test for competing access to the memory from a plurality of processors at the same timing is performed,
It was necessary for each processor to issue a lock control instruction, wait for the completion of the execution operation of each processor, and then control the execution of the target instruction sequence.

The object of the present invention is to solve the above-mentioned problems by
It is intended to provide a more efficient and highly accurate Symmetric Multi processor test method by generating a memory access conflict case at the same timing with an arbitrary instruction sequence between mmetric Multi processors.

[0008]

[Means for Solving the Problems] To achieve the above object,
In the Symmetric Multi processor that shares the memory, in the method of testing by reading and writing data from and to each memory by the test program, the test environment setting process, the instruction simulator that generates the expected value, the test instruction It has column execution trace information generation processing, result comparison processing, test instruction coverage information accumulation processing, and test instruction string generation processing, and test instruction strings for the number of executing processors are executed in parallel in block units, with several instructions for each processor. Generates and stores the type of memory access issued from each processor, the address of memory access, and the number of speculative execution instruction cycles in the coverage information, and the instruction generation on the other processor side refers to the coverage information to generate it. Minutes, select a test instruction equivalent to the number of execution instruction cycles on the processor side, It is characterized by having a function of repeatedly generating a test instruction sequence in which multiple processors compete for access to the memory of the same address at the same timing and various operations such as writing / reading to / from the memory compete. .

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention showing a test program execution system in a data processing device. The test instruction sequence (106) is stored in an arbitrary memory of the data processor, the execution initial value (107) is stored in each hardware resource such as a register, and the execution information of the test instruction sequence is stored in the test instruction sequence coverage information (108). A test instruction sequence environment setting unit (101) to be set.

The test instruction sequence (106) and the initial value of execution (107) are used to generate an expected value (110) and test instruction sequence execution trace information (109) which is a table of the expected execution sequence of each instruction. Instruction simulation unit (102). The execution initial value (107) is used as an initial value, the test instruction sequence (106) is executed by the data processing device to be tested to obtain the execution result value (111), or the test instruction sequence did not end due to a failure due to timer monitoring. At the time, the test instruction sequence execution control unit (103) forcibly ending the timer interrupt generation.

Expected value (110) and execution result value (111)
Error message (11
Execution result comparison unit (104) that outputs 2). Necessary information is extracted from the test instruction sequence (106) and the test instruction sequence coverage information (108), and the test instruction sequence timing adjustment unit (10) is extracted.
5) the test instruction sequence (10
Correct 6).

FIG. 2 is a flow chart showing the processing of the entire test apparatus of FIG. The execution initial value of each processor is set from the execution initial value data group (step 201). Test parameter information is generated for each processor from a parameter group designated by the operator or selected by a random value (step 202). The processor that first generates an instruction determines the target block range (2
A test instruction sequence of 0 to 40 instructions is generated (step 2)
03). Information on the generated test instruction sequence is stored in the test instruction sequence coverage information (step 204).

The second and subsequent processors that generate instructions are
By referring to the test instruction string coverage information together with the information on the test parameters of the processor, calculate the number of execution cycles of the accumulated test instruction string of another processor, and consider the number of instruction cycles of the test instruction string generated by the processor. , If the number of execution cycles in another processor is long, set the register to use so that the number of execution cycles on the processor side becomes long and register conflict with the preceding and following instructions, and use the memory to cause cache miss or TLB miss Adjust the address. On the other hand, if the number of execution cycles in another processor is short, an instruction type that completes execution in an equivalent cycle is selected and generated. The test instruction sequence for several instructions is sequentially generated for each processor by the above method, and the information of the test instruction sequence generated by each processor is stored in the test instruction sequence coverage information (step 204). The above processing is repeatedly generated up to N target block ranges in all processors (step 205).

With reference to the generated test instruction coverage information of the target block range of all processors, the number of execution cycles is compared for each instruction execution number of each processor, and the number of execution cycles of any processor is not biased. A search is made to see if memory accesses at the same timing are competing among multiple processors. If the number of execution cycles is long, the type of the instruction is replaced with an instruction having a short number of execution cycles. On the contrary, if it is short, a dummy instruction is inserted before the relevant instruction, and the number of execution cycles is adjusted to the other processor. After the adjustment / change of all processors is completed, the expected value is generated by instruction simulation. Each instruction is simulated based on the execution initial value and the test instruction sequence to generate expected value and test instruction sequence execution trace information (step 206).
Steps 202 to 206 are repeated until the test instruction sequences for all processors are completed (step 20).
7).

Initial values are set for the resources of each processor, the test instruction sequence is executed on the test target processor, and the execution result is obtained (step 208).

The expected value and the execution result value are compared (step 2
09), if a mismatch occurs, error information is output (step 210), and the steps 201 to 210 are repeated until the execution of all tests is completed (step 211).

FIG. 3 shows a flow chart of the test instruction sequence generation processing. The test instruction coverage information of each processor is retrieved (step 301), and the memory access operation is determined from the test parameters (step 302).

If the access to the same memory is selected by the test parameter (step 303) and the access to the same memory is selected by the test instruction,
An access address is selected from the memory access address information in ascending order of access frequency. If the selected access address is registered in the test instruction coverage information, the access address is selected. If it is not registered, the address used in the test instruction coverage information is selected and the memory access information is updated (step 304). When the same memory is not accessed, an unused address is searched for in the test instruction coverage information, and an access address having a low access frequency is selected from the memory access address information and updated (step 30).
5). Step 302, Step 304, Step 30
The test instruction is generated based on the memory access operation / address determined in step 5 (step 306). The above process is repeatedly generated one instruction at a time.

[0020]

According to the present invention, it is possible to realize access to the same memory from a plurality of processors at the same timing, and to compete memory access operations at the same timing, and it is possible to improve the verification accuracy and to achieve high accuracy. Logical verification is possible.

[Brief description of drawings]

FIG. 1 shows a Symmetric test method according to an embodiment of the present invention.
It is a block diagram which shows the structure of the test process which implements the test of a Multi processor.

FIG. 2 is a flowchart showing the processing of the entire test program shown in FIG.

FIG. 3 is a flowchart of a test instruction sequence generation process in FIG.

[Explanation of symbols]

101 Test instruction sequence environment setting unit 102 Instruction simulation part 103 test instruction sequence execution control unit 104 Execution result comparison 105 Test instruction sequence timing adjustment unit 106 test instruction sequence 107 Initial execution value 108 Test instruction sequence coverage information 109 Test instruction string execution trace information 110 expected value 111 Execution result value 112 Error message

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Claims (3)

[Claims] 1. In a Symmetric Multi processor sharing a memory, a test environment setting process and an instruction simulator for generating an expected value in a method of testing reading and writing of data from and to each memory by a test program in a test program, The test instruction sequence execution trace information generation process, the result comparison process, the test instruction coverage information accumulation process, and the test instruction sequence generation process are included.
mmetric Multi Generates several instructions for each processor in block units, adjusts the type and frequency of memory access issued by each processor, and generates test instructions in block units for all generated processors. Symmetric Mult, which has the function of generating expected values with an instruction simulator and repeatedly generating all test instruction sequences
i Processor test execution method. 2. The test instruction sequence generation process according to claim 1, wherein in the Symmetric Multi processor, when an instruction for accessing a memory is selected in the test instruction sequence of each instruction processor, the test is performed at the same timing in another processor. Characterized by having the function of recognizing the type and access address of the instruction, deciding whether to write or read to the memory, deciding the address to access, and arbitrarily generating the conflict of access to the memory of the same address Symmetric Mu
lti Processor test execution method. 3. The test instruction sequence generation process according to claim 1, wherein by referring to the test parameter and the coverage information of the test instruction, the test instructions of the already generated processor are generated in the test instruction sequence generation of each instruction processor. A test instruction corresponding to the test specified by the test parameter by adjusting the type / function of the column, the memory access address, and the type / function / memory access address of the generated instruction based on the number of execution cycles of the generated instruction. A test execution method for the Symmetric Multi processor, which has the function of generating columns.