JP2000293396A - Method and device for estimating system performance - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method and a device which estimate the performance of each system faster than to perform simulation in each of combinations of plural parts when there are plural parts for constituting each circuit block in a system where plural circuit blocks are connected through a bus. SOLUTION: This device estimates the system performance of a system in which plural circuit blocks are connected through a bus. In such a case, it has a bus information generating device generating bus information when software is carried out, a parts library 14 storing the information of bus operation which is held by parts with respect to each circuit block in the system and a system performance calculating device 15 calculating the system performance from the generated bus information 13 and the information of bus operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method and an apparatus for estimating system performance in a system in which a plurality of circuit blocks are connected by a bus.
The present invention relates to a method and apparatus for estimating the performance of a system in a CAD field for designing a system including a memory, an I / O, an ASIC, and the like.

[0002]

2. Description of the Related Art Conventionally, when designing a system including a processor (CPU), a memory (MEM), an I / O, an ASIC, and the like, a block configuration of the system and software to be executed thereon are determined, and each block is handled. In order to estimate the system performance at the time of software execution when parts groups to be prepared are prepared as a library, a model connecting each part was created, simulation was performed, and the system performance was calculated from the simulation results .
FIG. 17 shows a configuration of a conventional system model, in which a processor (CPU) (11a), a memory (MEM) (11b), an I / O
Blocks such as (11c) and ASIC (11d) are connected to a bus (12), and software (13) to be executed in this system is determined.

[0003]

In order to estimate the performance of the system, a model in which each component is connected is created and simulation is performed as described above, but a certain component is calculated by another component. In order to estimate the performance of the system when the system is changed to the above, it is necessary to reconstruct a system model using the changed parts and perform the simulation again to calculate the system performance. In addition, since it takes a long time to perform the simulation, it has been difficult to check the performance of the system for a large number of combinations of components assigned to each block. The present invention has been made in view of the above problems,
It is an object of the present invention to provide a method and an apparatus for estimating the performance of each system faster than performing a simulation for each combination when there are a plurality of components constituting each circuit block.

[0004]

Means for Solving the Problems To achieve the above object, a method for estimating system performance according to the present invention has information on a bus at the time of executing software and components for each of the circuit blocks in the system. It is characterized in that the system performance is calculated from the bus operation information. In addition, the system performance estimating apparatus according to the present invention includes a bus information generating apparatus that generates bus information when software is executed, and a component library that holds information on bus operations of components for each circuit block in the system. And calculating the system performance from the bus information and the information on the bus operation. Further, the system performance estimating device compares the combination of components, a performance estimation value storage device that holds the estimated value of the system performance for each combination, and the estimated performance value of each combination of components, and And a performance comparison device for finding a combination having the best performance. Further, the bus information of the system performance estimating apparatus is characterized by including the type of bus operation, the number of cycles, the number of interrupt occurrence cycles, and a flag indicating whether or not an interrupt is being processed.

[0005] Further, an apparatus for estimating system performance includes:
It is characterized in that the component information held in the component library includes a bus operation execution time and an interrupt generation cycle number.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. Here, a case where the execution time of software is estimated as the performance of the system will be described. FIG. 1 shows a schematic configuration of a system performance estimating apparatus according to a first embodiment of the present invention. The system performance estimation device consists of a processor (CPU), memory (ME
M), a model (11) of a system in which circuit blocks such as I / O and ASIC are connected by a bus, a simulation device (12) for simulating the model, basic bus information (13) obtained by the simulation, A system library (14) in which design data for each block is prepared as a component, and a system performance calculation device (calculated from the basic bus information (13) and component information) that calculates software execution time in a system of the combination of the components ( 15)
It is composed of As shown in FIG. 2, the system model (11) includes a processor (CPU) (11a), a memory (MEM) (11b),
Circuit blocks such as I / O (11c) and ASIC (11d)
In the configuration connected in 2), the software (23) to be executed in this system is determined. In addition, each block (11a
−11d), the parts (1
4a-14d) are prepared as the component library (14).
As a simulation model, a bus operation is determined from values of a data bus / address bus, a read / write signal, and the like by using a simulation model such as a bus transaction level, RTL, cycle base, and instruction level. You can check the situation.

[0007] The components for realizing each block are prepared as an existing library, or for a new block such as an ASIC, new component information is created and prepared according to the specifications. The component information includes a function required for the simulation, the number of cycles of a bus operation, power consumption, and in the case of an ASIC, the number of cycles when the function is executed. FIG. 3 shows an example of the component information. Frequency, memory (MEM1-MEM3), I / O as information of processors (CPU1, CPU2)
(I / O1-I / O3) information as access time, A
The access time and the execution time when the function is executed are shown as information of the SIC (ASIC1, ASIC2). For example, MEM1 is a component that requires two cycles for a read cycle (Read) and two cycles for a write cycle (Write). Although an ASIC is newly created, a bus operation (Re-operation) between the processor and the ASIC is performed before detailed design data such as RTL is created.
Ad, Write) takes this much time, and the function (Exec) of the ASIC takes this long execution time, and a part is created based on the approximate value at the specification stage.

In order to generate bus information, first, a basic system model (11) is created. For example, the fastest part is selected from the parts of each block, and a model assigned to each block is created. When the basic model is created, the software that has already been determined
Simultaneously with (23), a simulation is performed by the simulation device (12). By simulating the system model (11), bus information when the software (23) is executed is extracted. FIG. 4 shows an example of bus information, which is a sequence of NOPs indicating bus operations (Read, IO-Read, Write) of each block and cycles in which the bus is not used when the software is executed. FIG. 5 is a table showing components used for each block when the simulation is performed. In this case, it is shown that CPU1, MEM1, I / O1, and ASIC1 are used as components. FIG. 6 is a table showing which blocks correspond to which bus operations. FIG. 7 shows the number of bus operations during software execution. In order to determine the execution time of the system when a certain part of the simulated system model is replaced with another part, the flowchart shown in FIG. 8 is executed. First, specify the part to be changed
(Step 31), the bus operation and the cycle number related to the component are acquired (Step 32). Next, it is assumed that the bus information obtained by the above simulation is represented by a data structure as shown in FIG. In this data structure, each element of the list corresponds to one bus operation, and each element has information on the type of bus operation and the number of cycles. Fetch the first operation in this list
(steps 33, 34), if the part to be changed by the bus operation is a related bus operation (step 35), st
Update to the number of cycles taken out by ep32. The next bus operation in the list is fetched (steps 38 and 34), and if the part to be changed is a related bus operation, the number of cycles is updated to the number of cycles fetched in step32. In the same manner, the entire list is examined, and all the bus operations related to the component to be changed are updated. After updating to the end of the list (ste
p37), by taking the sum of the number of cycles for all lists (s
tep39), software execution time when components are changed can be calculated.

As a specific example, an example in which the memory is changed will be described. In the first combination of components, it is assumed that the component MEM1 that requires two cycles of read operation and two cycles of write operation in the memory is selected, and simulation is performed to obtain bus information as shown in FIG. Here, the memory is changed to another component MEM2. MEM2 requires three cycles for a read operation and three cycles for a write operation. First, it can be seen from the correspondence between the components and the bus operations that the read operation and the write operation are affected by the execution time of the software when the memory is changed. Next, the order of the bus operation is traced from the beginning, and in the case of a read operation or a write operation, the cycle number of the new bus operation is updated. The updated bus information is in a state as shown in FIG. The execution time of the software after changing the components is calculated by calculating the total number of cycles in the updated bus operation order. As described above, in the present embodiment, it is possible to calculate the performance of the system at a higher speed than when performing simulation for each combination of components. In addition, the operation of reconstructing a model for each combination of parts and checking the operation of the model can be reduced.

In this embodiment, the case where the memory is changed has been described. However, when the processor is changed, even when the execution time of the instruction of the processor changes, each bus operation or NOP can determine the instruction of the processor. By adding information indicating whether or not this is the case, estimation from the bus information can be realized. Further, even when there are a plurality of bus masters, for example, a plurality of CPUs and ASICs, it can be easily realized by adding information indicating a bus operation of which block. Also, when estimating the power consumption as the performance of the system, similarly to the first embodiment, a model of the basic system is created and simulation is performed to obtain bus information. As the component information, it is assumed that the power consumption value in the bus operation is obtained together with the number of cycles of each bus operation. As in the first embodiment, if the memory is changed, read and write operations increase. Based on the power consumption of the memory, other blocks, and the bus at this time,
Calculate power consumption. Further, in addition to the configuration of the invention in FIG. 1 of the first embodiment, as shown in FIG. 12, a component selection device (41) for selecting a combination of components, a combination of components and the performance of the system in that case By providing a performance estimation value storage device (42) that holds the data and a performance comparison device (43) that finds the combination with the best system performance, the optimum combination of components and the performance estimation value (44) at that time are obtained. be able to. Also, with the increase in speed, many combinations of components can be tried, and by selecting a more optimal combination of components, a high-performance system can be designed.

Next, a method and an apparatus for estimating system performance according to a second embodiment of the present invention will be described with reference to FIGS. In the first embodiment, the system performance calculation device (1
As an example of the processing in 5), the case where the order of the bus operation does not change is described. Here, the case where the order of the bus operation changes will be described. For example,
The CPU requests some processing from the ASIC,
Assume that the ASIC performs processing for several cycles and interrupts the CPU. For simplicity, assume that the ASIC process takes a fixed number of cycles. The ASIC 1, which is a component of the ASIC, interrupts the CPU after performing a four-cycle process after a request from the CPU, that is, a write operation. Also, ASI
In C2, it takes seven cycles before an interrupt occurs. When ASIC1 is used in the first simulation model, the basic bus information is as shown in FIG. When the ASIC-Write operation is executed, the ASIC starts
An interrupt occurs after the cycle. Then, after performing the interrupt process, the process returns to the normal process. Here, when the part is changed to ASIC2, as shown in FIG.
-An interrupt occurs seven cycles after the Write operation. To find this from the bus information in FIG.
As shown in FIG. 15, int (ASIC1) is used for the bus operation during the interrupt processing, and in in the bus operation for the normal processing.
Add the t0 flag. In addition, the operation for waiting for an interrupt is provided with information on the number of cycles after which the interrupt occurs.

FIG. 16 is a flowchart for processing basic bus information having such a data structure. The flowchart shown in FIG. 16 is a process corresponding to step 36 in FIG.
FIG. 16 shows a whole process. Since the portion of FIG. 8 has been described in the first embodiment, only FIG. 16 will be described here. First, it is determined whether or not the current bus operation is an operation that generates an interrupt (step 51). If the current bus operation is an operation that generates an interrupt, the number of cycles after which the interrupt is generated is obtained (step 52). Also,
The number of cycles after the interruption when the component is changed is obtained from the component information (step 53). Next, the order is traced from the current bus operation, and the first element of the interrupt processing corresponding to this bus operation is found (step 54). From this element, the interrupt processing flag int (ASIC
Since 1) is set, the order is further traced while checking this flag to find the end of the interrupt processing (step 55).
Next, create an order that excludes the order of this interrupt processing,
The order of the interrupt processing is temporarily suspended (step 56). Next, a bus operation after the number of cycles obtained in step 163 is obtained from the current bus operation (step 5).
7). Next, check the bus operation in step57,
It is checked whether or not the timing of occurrence of the interrupt is in the middle of a cycle such as a memory read (step 58). If it is in the middle of the bus operation, the number of cycles at which an interrupt occurs is changed to the number of cycles at the time when the bus operation ends (step 59). Then, the interrupt processing temporarily suspended in step 56 is inserted after the end of this bus operation (step 60).

In this manner, the bus operation is rearranged, all the bus operations related to the component to be updated are processed, and the total number of cycles of the updated bus operation is obtained to change the component. Calculate the execution time of later software. As described above, also in the present embodiment, it is possible to calculate the performance of the system faster than performing simulation for each combination of components. In addition, the operation of reconstructing a model for each combination of parts and checking the operation of the model can be reduced. In the above description, the execution cycle of the ASIC is fixed. However, the case where the processing cycle of the ASIC fluctuates due to data from the CPU can be realized as follows. First, a function capable of calculating an interrupt occurrence time based on data from the CPU is prepared in the component information of the ASIC. At the time of the first simulation, CPU information is used as information of each ASIC-Write operation of bus information.
Append data from. When updating the bus information by changing the component, when checking each ASIC-Write operation, the cycle in which an interrupt occurs is calculated from the information of the data from the CPU and the processing content of the ASIC component, and Adds the interrupt generation time to the ASIC-Write operation. Thus, the present invention can be applied even when the execution time of the ASIC varies.

[0014]

According to the present invention, it is possible to calculate the performance of the system faster than performing simulation for each combination of parts. In addition, the operation of reconstructing a model for each combination of parts and checking the operation of the model can be reduced. Further, with the speeding-up, a number of combinations of parts can be tried, and a high-performance system can be designed by selecting a more optimal combination of parts.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a performance estimation device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a block configuration of a system according to an embodiment of the present invention and components of each block.

FIG. 3 is a diagram showing components of each block and information of the components according to the embodiment of the present invention.

FIG. 4 is a diagram showing an order of a bus operation according to the embodiment of the present invention.

FIG. 5 is a diagram showing the assignment of current components to blocks of the system according to the embodiment of the present invention.

FIG. 6 is a diagram showing a correspondence between each block and a bus operation according to the embodiment of the present invention.

FIG. 7 is a diagram showing the number of bus operations according to the embodiment of the present invention.

FIG. 8 is a diagram showing a flowchart for calculating system performance from bus information and component information according to the embodiment of the present invention.

FIG. 9 is a diagram showing a data structure representing an order of a bus operation according to the embodiment of the present invention.

FIG. 10 is a diagram showing an order of a bus operation before a memory change according to the embodiment of the present invention.

FIG. 11 is a diagram showing a sequence of bus operations after a memory change according to the embodiment of the present invention.

FIG. 12 is a diagram showing a configuration for obtaining a combination of parts having optimum performance according to the embodiment of the present invention.

FIG. 13 is a diagram showing basic bus information including interrupt processing according to the embodiment of the present invention.

FIG. 14 is a diagram showing bus information in which the order of bus operations is rearranged by changing components according to the embodiment of the present invention.

FIG. 15 is a diagram showing a data structure for rearranging bus operations according to the embodiment of the present invention.

FIG. 16 is a diagram showing a flowchart for performing rearrangement of bus operations according to the embodiment of the present invention.

FIG. 17 is a diagram showing a block configuration of a system according to a conventional example.

[Explanation of symbols]

 Reference Signs List 101 system model 102 simulation device 103 basic bus information 104 component library 105 system performance calculation device 106 performance estimation value

Claims (5)

[Claims] 1. A method for estimating system performance in a system in which a plurality of circuit blocks are connected by a bus, comprising: information of a bus when software is executed; and a bus of a component for each of the circuit blocks in the system. A system performance estimation method comprising calculating system performance from operation information. 2. A device for estimating system performance for a system in which a plurality of circuit blocks are connected by a bus, wherein a bus information generating device for generating bus information when software is executed; A system comprising: a component library that holds information on bus operations of components for each of the circuit blocks; and a system performance calculation device that calculates system performance from the bus information and the information on the bus operations. Performance estimation device. 3. The system according to claim 3, wherein the combination of the components, a performance estimation value storage device that holds an estimated value of the performance of the system in each combination, and an estimated performance value of the combination of the components are compared. 3. The apparatus according to claim 2, further comprising a performance comparison device for finding a best combination.
The described system performance estimator. 4. The system performance according to claim 2, wherein said bus information includes a type of bus operation, a cycle number, an interrupt generation cycle number, and a flag indicating whether or not an interrupt is being processed. Estimating device. 5. The system performance estimating apparatus according to claim 2, wherein the component information held in the component library includes a bus operation execution time and an interrupt generation cycle number.