JP2633651B2 - Racing check method for simulation equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a racing check method of a simulation device that executes a logic simulation for a circuit model in which a two-stage latch FF is one unit, one of timing simulations handling detailed delay values
For the purpose of high-speed racing check along with logic simulation, the reference value parameters of clock SKEW value generation time, output event generation time, hold time reference value and setup time reference value taking into account the detailed delay value are prepared. When the logic simulation of the circuit model is executed, the time difference obtained by subtracting the clock SKEW value occurrence time from the output event occurrence time is calculated, the racing is determined by comparing the calculated time difference with the hold-up reference value, and the calculation time difference and the setup time are calculated. The configuration is such that delay over or setup abnormality is determined by comparison and determination with a reference value.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a racing check method of a simulation apparatus that executes a logic simulation including a racing check on a circuit model in which a two-stage latch FF is one unit.

CA that performs logical design of hardware such as computers
In the field of E (Computer Aided Enginering), a simulation device is used as a tool for verifying a created logical design model.

In the simulation of such a logic design model, logic simulation and timing simulation dealing with detailed delay values are required, and furthermore, timing simulation in consideration of a racing check between FFs constituting the logic design model is required. Become.

[Prior art] Conventionally, in the simulation of a logic design model created in the field of CAE, a method in which logic simulation dealing with a fixed unit delay value and timing simulation are separately processed is generally used. The logic simulation and the timing simulation considering the mounting state and the delay value of the element etc. are handled simultaneously for each of the basic primitives to be configured, and the timing simulation method for performing the racing check is a separate process for the hardware simulator and / or the software simulator. , Has not been put to practical use.

[Problems to be Solved by the Invention] However, in the conventional logic simulation method using a unit delay value, a detailed delay value corresponding to a mounting state and a delay value of an element when a test pattern of a basic design model is created. Is not taken into account, the logical operation of the logical design model can be verified, but there is a problem that the validity of test pattern creation cannot be verified.

Of course, it is conceivable to add a timing simulation phase that takes into account the detailed delay value to the conventional logic simulation phase, but since the logic simulation and the timing simulation including the racing check are separate processes, a huge amount of time is required for the verification of the logic design model. There was a problem in that it took a long processing time and made development more efficient.

The present invention has been made in view of such a conventional problem, and a racing check method of a simulation apparatus in which a racing check, which is one of timing simulations handling detailed delay values, can be performed at a high speed together with a logic simulation. The purpose is to provide.

[Means for Solving the Problems] FIGS. 1A and 1B are explanatory diagrams of the principle of the present invention. FIG. 1A shows the configuration, FIG. 1B shows a circuit model, and FIG. (D) shows a delay over determination, and (e) shows a timing chart of a setup abnormality determination.

First, the present invention is directed to a simulation apparatus that executes a logic simulation using a circuit model in which at least a first latch FF10 and a second latch FF12 constituting a logic design model are sequentially connected as one unit.

In such a simulation apparatus, in the racing check method of the present invention, first, as a means for storing a reference value parameter, a first configuration of the circuit model 14 is used.
And clock input (CLK1, CLK2) to the second FF10, 12
Clock SKEW value generation time storage unit 16 which stores the generation time of the clock input (CLK2) of the second FF12 as the clock SKEW value generation time (tc) based on the SKEW value defined by the time difference of
And an event occurrence time storage unit storing an event occurrence time (ti) at which the state of the output (Q1) changes after the first and second FFs 10, 12 constituting the circuit model 14 receive the clock input (CLK1). 18; a hold time reference value storage unit 20 storing the hold time reference values (Th) of the first and second FFs 10 and 12 constituting the circuit model 14; Setup time reference value storage unit 2 that stores setup time reference values (Ts) for FF10 and FF12
2;

The reference value parameters stored in these storage units are set as values based on the detailed delay value in consideration of the logical delay of the element and the line length at the time of mounting.

Each time the output event of the target circuit model 14 changes due to the execution of the simulation, the event delay value [CLK
→ D2 (Q1)] Clock SKEW [CLK1 → CLK2] read from clock SKEW value generation time storage unit 16 from generation time (ti)
The value generation time (tc) is subtracted, and the calculation unit 24 calculates the time difference (ΔF) between the SKEW value and the delay time from the clock input to the output event generation of the circuit model 14.

Subsequently, the first comparator 26 compares the calculation time difference (ΔF) of the calculation unit 24 with the hold time reference value (Th) read from the hold time reference value storage unit 20, and sets up the calculation time difference (ΔF). The setup time reference value (Ts) read from the time storage unit 22 is compared with the second comparison unit 28.

Finally, a racing determination is performed by the racing determination processing unit 30 based on the comparison result of the first comparison unit 26, and a delay over determination is performed by the delay over determination processing unit 32 based on the comparison result of the second comparison unit 28. At the same time, the setup abnormality determination processing unit 34 determines a setup abnormality.

Here, the racing determination processing unit 30 calculates the operation time difference (ΔF) between CLK1 constituting the circuit model 14 and the output event (Q2) of the first FF10, that is, the delay value, and the CLK1 and FF12.
ΔF = delay value−
If SKEW is positive and smaller than the hold time reference value (Th2) of the second FF12, that is, if 0 <ΔF <Th, it is determined that racing is performed.

In addition, the delay over determination processing unit 32
, The operation time difference (ΔF) with respect to the output event (D2) of the first FF10, ie, the delay value and the difference between CLK1 and FF12.
ΔF = delay value−SK, which is the calculation time difference SKEW value from CLK2
When EW is negative and its absolute value (| ΔF |) is equal to or greater than the setup time reference value (Ts) of FF12, that is, 0> ΔF and | ΔF | ≧ Ts2, it is determined that the delay is over.

Further, the setup abnormality determination processing unit 34
14 when the operation time difference (ΔF) with respect to the output event of the first FF10 is negative and its absolute value (| ΔF |) is smaller than the setup time reference value (Ts2) of the second FF12, that is, 0> If ΔF and | ΔF | <Ts2, it is determined that the setup is abnormal.

[Operation] In the racing check method of the simulation apparatus according to the present invention having such a configuration, in parallel with the execution of the logic simulation, various reference parameters based on the detailed delay value, that is, the clock SKEW value generation time, CLK1
A high-speed racing check can be performed on circuit models such as FF based on the D2 event occurrence time, hold time reference value, and setup time reference value from
It is possible to perform critical verification for creating an effective test pattern according to a logical design model, improve pattern quality, and improve the yield of LSIs and the like in a manufacturing stage.

[Embodiment] FIG. 2 is a block diagram showing an embodiment of an embodiment of the present invention. The latch shown in FIG. 3 is simultaneously executed with a logic simulation using a circuit model 14 in which FFs 10 and 12 are sequentially connected as one unit. Perform a racing check of the invention.

The circuit model of the embodiment shown in FIG.
In addition to the figures, the check primitives 56 and 58 are added to the latch shown in FIG.
This includes a circuit model that treats 6,58 as a zero delay, and a circuit model that further provides check primitives 56,58 in parallel with the FFs 10,12 as shown in FIG.

Thus, in the embodiment of FIG. 2, the circuit models shown in FIGS. 3, 4, and 5 are to be processed, but in the following embodiment, the circuit model 14 of FIG. To explain.

First, in the embodiment of FIG. 2, CLK1 is used as a memory for storing a reference value parameter for a racing check.
→ Clock SKEW value generation time memory 16, which becomes CLK2, CLK1 →
An event occurrence time memory 18, which is D2, a hold time reference value memory 20, and a setup time reference value memory 22 are provided.

More specifically, first, the clock SKEW value generation time memory 16 stores the reception side clock with respect to the transmission side clock.
The occurrence time based on the SKEW value is stored. That is, the third
Taking the circuit model 14 in the figure as an example, when the clock CLK is received by the circuit model 14, the clock input CLK1
The delay time interval between the clock inputs CLK1 and CLK2 from the rise of the clock FF12 to the rise of the clock input CLK2 of the next FF12 is defined as the SKEW value.Therefore, the clock SKEW value generation time memory 16 stores The generation time (tc) of the clock input CLK2 is stored.

An event occurrence time indicating a change in the state of data to be subjected to a racing check is stored in an event occurrence time memory 18 where CLK1 → D2. In the circuit model 14 shown in FIG. The output event occurrence time (ti) at which the output Q1 changes is stored.

Further, in the hold time reference value memory 20 and the setup time reference value memory 22, for example, reference values of the setup time and the hold time of the FFs 10 and 12 constituting the circuit model 14 of FIG. 3 are stored.

The clock SKEW value generation time memory 16 and the event generation time memory 18 that becomes CLK1 → D2 are accessed by the memory controller 36. The memory controller 36 is provided with a net value number, event occurrence information, and an operation identification code decoded by the decoder 40 from the function code setting unit 38. That is, when an event occurs in the clock net number, the memory controller 36 accesses the clock SKEW value generation time 16 to access the corresponding clock SKEW.
Outputs the EW value generation time (tc). At the same time, the memory controller 36 accesses the event occurrence time memory 18 that stores the data event occurrence times to be subjected to the racing check, and outputs the corresponding event occurrence times (ti).

At this time, the function code of the function code setting unit 38 triggered by the net value for the memory controller 36 is decoded by the decoder 40, and the control conditions of the memory controller 36 are controlled.

In addition to such memory access of the clock SKEW value occurrence time memory 16 and the event occurrence time memory 18, the hold time and setup time reference value memories 20, 22
Is accessed by the memory controller 44.

That is, the clock SKEW value generation time memory 16
The memory controller 44 is triggered by the SKEW value generation time (tc), and read access to the hold time reference value memory 20 and the setup time reference value memory 22 is performed. For the hold time reference value memory 20 and the setup time reference value memory 22, a check event generation control circuit 46 and a check event generation time memory 48 are provided. That is, when the hold time reference value and the setup time reference value are read out to the check event generation control circuit 46 by the read access of the hold time reference value memory 20 and the setup time reference value memory 22 by the memory controller 44, the memory reference Based on the value, the check event generation control circuit 46 sets a check event generation time, for example, a check event after reading out the hold time reference value after the event of CLK1 rises. In addition, a check event is set after the setup reference value is read after the event of D2 is set. The check event generated in this way is
It is written to the check event occurrence time memory 48.

Next, an arithmetic processing system for a racing check will be described.

First, the clock SKEW value generation time (tc) read from the clock SKEW value generation time memory and the event generation time (ti) of the data to be subjected to the racing check read from the event generation time memory 18 are calculated by the arithmetic unit 24. Is input to The calculation unit 24 starts clocking from the event occurrence time (ti).
The time difference (ΔF) is obtained by subtracting the SKEW value generation time (tc).

The time difference (ΔF) calculated by the calculation unit 24 is, for the circuit model 14 in FIG. 3 as an example, based on the delay time from when the FF 10 receives the clock input CLK1 to when the output Q1 is inverted. It indicates the value after subtracting the SKEW value.

The time difference (ΔF) calculated by the calculation unit 24 is stored in the register 42.

The time difference (ΔF) stored in the register 42 is given to the first comparing section 26 and the second comparing section 28, respectively. The other of the first comparing section 26 includes a check event generation control circuit section 46.
3, the hold time reference value stored in the hold time reference value memory 20, that is, the hold time reference value (Th2) of the subsequent FF12 in the circuit model 14 in FIG. The result of comparison between the data and the hold time reference value (Th2) is stored in the register 50, and the racing determination processing unit 30 makes a racing determination based on the result of comparison stored in the register 50.

On the other hand, the other of the second comparison section 28 has the setup time read from the setup time reference value memory 22 via the check event generation control circuit section 46, that is, the third setup time.
The setup time (Ts2) of the subsequent FF12 in the circuit model 14 shown in the figure is input, and the time difference (Δ
The result of comparison with F) is stored in the register 52. register
Based on the comparison result of the second comparison unit 28 stored in 52, the delay over determination processing unit 32 determines the delay over, and the setup abnormality determination processing unit 34 determines the setup abnormality.

Further, an abnormal status register 54 is provided, and when any of a racing determination by the racing determination processing unit 30, a delay over determination by the delay over determination processing unit 32, and a setup abnormality by the setup abnormality determination processing unit 34 is determined, an abnormal status An abnormal flag is set in the register 54.

Here, the determination conditions in the racing delay over and setup abnormality determination processing units 30, 32, and 34 will be described as follows. First, the racing determination condition by the racing determination processing unit 30 is based on the delay time (FF1 → D2 = Q1) of the clock CLK1 from the delay time of the FF10 at the previous stage in the circuit model 14 of FIG.
If the time difference (ΔF) obtained by subtracting the SKEW value of the clock signal CLK2 and the clock signal CLK2 is positive and the time difference (ΔF) is smaller than the hold time reference value (Th2) of the subsequent FF12, it is determined to be racing.

 That is, the racing determination is determined to be racing when 0 <ΔF ≦ Th2.

Next, in the delay over determination by the delay over determination processing unit 32, the time difference (ΔF) has a negative value,
When the absolute value (| ΔF |) of the time difference (ΔF) is equal to or longer than the setup time reference value (Ts2) of the subsequent FF12, it is determined that the delay is over. That is, when 0 <ΔF and | ΔF | ≧ Ts2, it is determined that the delay is over.

Further, in the setup abnormality determination processing unit 34, the setup abnormality determination is performed when the time difference (ΔF) has a negative value and the absolute value (| ΔF |) of the time difference (ΔF)
If it is smaller than the FF12 setup time reference value (Ts2), it is determined that the setup is abnormal. That is, when 0> ΔF and ΔF <Ts2, it is determined that the setup is abnormal.

 Next, the processing operation in the embodiment of FIG. 2 will be described.

First, when an event occurs in the clock net value number, the clock SKEW value generation time memory 16 is accessed by the memory controller 36, and the corresponding clock SKEW value generation time (tc) is read and input to the arithmetic unit 24. The memory controller 36 accesses the event occurrence time memory 18 storing the data event occurrence time of the racing check target, and reads the read event occurrence time (t
i) is input to the calculation unit 24. Function code setting section triggered by the net value number generated at this time
The function code 38 is decoded by the decoder 40 and controls the control conditions of the memory controller 36.

The arithmetic unit 24 calculates the clock SKEW value generation time (t) read from the clock SKEW value generation time memory 16 from the event generation time (ti) read from the event generation time memory 18.
By subtracting c), a time difference ΔF is obtained and stored in the register 42.

On the other hand, triggered by the time reading from the clock SKEW value generation time memory 16, the memory controller 44 sets the hold time and setup time reference value memories 20, 22
And the hold time reference value and the setup time reference value read from the hold time and setup time reference value memories 20 and 22 are given to the check event generation control circuit 46. The check event generation control circuit unit 46 obtains the check event generation time and the state of the generated event by adding the hold time reference value or the setup time reference value to the current time, and writes it to the check event generation time memory 48.

When the simulation time further advances in this state, the check event occurrence control circuit unit 46 accesses the check event occurrence time memory 48 to output the hold time reference value (Th2) to the first comparison unit 26 and perform the second comparison. Part 28
The setup time reference value (Ts2) is output to.

Therefore, the first comparator 26 compares and determines the time difference (ΔF) from the register 42 and the hold time reference value (Th2) from the check event generation control circuit 46, and stores the comparison result in the register 50. , And similarly the second comparison unit
Also at 28, a comparison between the time difference (ΔF) and the setup type reference value (Ts2) is made, and the comparison result is stored in the register 52.

Subsequently, racing determination is performed by the racing determination processing unit 30 based on the comparison result of the register 50. If the above-described racing determination condition is satisfied, an abnormal flag indicating racing is set in the abnormal status register 50.

The delay over determination processing section 32 and the setup abnormality determination processing section 34 perform determination processing based on the comparison result stored in the register 52, respectively. Will be set.

FIG. 6 is an explanatory diagram of processing steps for a racing check in the embodiment of FIG.

In FIG. 6, first, the clock SKEW value, that is, the clock SKEW value generation time (tc) is read at the time, and at the same time, the clock-data delay value, that is, the event generation time (ti) is read at the same time. It is. Subsequently, a time difference (ΔF) is obtained as a difference between the two at the time.
At the same time, the setup time reference value and the hold time reference value are read. Subsequently, a comparison between the time difference (ΔF) and the set-up time is made at the time, a comparison between the time difference (ΔF) and the hold time reference value is made at the same time, and a delay over judgment is made at the same time thereafter. Processing, setup determination processing, and racing determination processing are performed.

FIG. 7 is a process explanatory diagram showing timing conditions and determination conditions in the racing check of the present invention according to the embodiment of FIG. 2 for the circuit modem 14 of FIG.

That is, under the timing conditions of FIG. 7A, the clock input CLK1 to the FF10 at the preceding stage and the clock inputs CLK2 and FF to the FF12 at the subsequent stage in the circuit model 14 of FIG.
Regarding the data input D1 and the output Q1 of the FF10 for the FF10, that is, the data input D2 of the FF12 and the output Q2 of the subsequent FF12,
An abnormal state according to the determination conditions (A), (B), and (C) shown in FIG.

First, in FIG. 7, No. 1 and N
The timing conditions when o.2 is input will be described.

As shown, the clock input CLK2 to the subsequent FF12 has a time delay of SKEW-1 with respect to the clock input CLK1 to the FF10 as shown in the figure. It is detected as the SKEW value occurrence time.

Subsequently, based on the clock CLK1 and the data D1, the time (ti
The output Q1 of the FF10 rises at the timing 1), and this time (ti1) is detected as the event occurrence time. As a result, the time difference (ΔF) used for determining the racing delay over and the setup abnormality is calculated as ΔF = ti1−tc1. At this time, since the time difference (ΔF) has a positive value, the time difference (ΔF) is a target of the racing determination shown in FIG. 7B (A).

Here, the time difference ΔF is equal to the hold time (Ts
2) If it is larger, the output condition Q2 of the FF12 has a timing condition of rising after a predetermined delay after the output Q1 of the latch FF falls as shown in the normal timing.

On the other hand, when the time difference (ΔF) is smaller than the hold time (Ts2) of the FF12, the racing determination condition (A) is satisfied, and the output of the FF12 of the next stage is simultaneously output while the output Q1 of the FF10 is rising. Q2 also starts up Q2
This will cause abnormal racing.

Regarding the clocks of No. N and No. N + 1 on the right side in the timing condition of FIG. 7A, the processing of judging the delay over and the setup abnormality is shown.

That is, SKEW of clocks CLK1 and CLK2 of No.N and No.N + 1
Detects the clock SKEW value generation time (tcn),
On the other hand, the Q1 output of FF, 1 rises with a predetermined delay time from the rise of the clock CLK1 of No. N, and the rising point of this Q1 is detected as the event occurrence time (tin).

In the case of No. N and N + 1 clocks, the event occurrence time (tin) occurs before the occurrence time (tcn) of CLK2 with a delay due to the SKEW value, and as a result, the time difference (ΔF = tin−tcn) ΔF) will have a negative value.

As described above, when the time difference (ΔF) has a negative value, a determination process regarding a delay over determination condition (B) or a setup abnormality determination condition (C) shown in FIG. 7B is performed.

If the absolute value of the time difference (ΔF) having a negative value is FF
If it is more than 12 setup time reference value (Ts2),
The condition (B) for determining the delay over is satisfied, and the output Q2 of the FF12 shown in FIG. 7A is abnormal.

On the other hand, the absolute value of the time difference (ΔF) having a negative value is
If it is shorter than the setup time (Ts2) of FF12, the setup abnormality determination condition (C) is satisfied, and the state of the FF12 Q2 output is included in the timing condition of FIG. 7A as shown by the determination condition (C). A setup error that does not change will occur.

FIG. 8 is an explanatory diagram showing another determination process in the racing check method of the present invention. In this embodiment, it is determined that racing, delay over, and setup abnormalities can be determined only by a flag check. Features.

8, the timing conditions shown in FIG. 8A and the determination conditions shown in FIG. 8B are the same as those in FIG.

In addition to this, in FIG. 8, since the determination conditions of racing, delay over, and setup abnormalities are all checked by flag check, the setup time and hold time check events for clocks CLK1 and CLK are indicated by vertical arrows. As shown in the figure, clock change, data change, and setting / resetting of an abnormal flag are performed. According to the state of these flags, racing, delay over,
Setup errors can be determined.

[Effects of the Invention] As described above, according to the present invention, a racing check on a circuit model such as a latch FF using various reference parameters based on a detailed delay value is performed at high speed in parallel with execution of a logic simulation. This allows critical timing verification of the logic design model to be performed.

In addition, the speed of verification for creating test patterns from the logical design model can be increased, and the timing verification for obtaining effective patterns can be performed, thereby improving the yield of LSIs and the like in the manufacturing process by improving the quality of test patterns. it can.

[Brief description of the drawings]

 1 is a diagram illustrating the principle of the present invention; FIG. 2 is a diagram illustrating the configuration of an embodiment of the present invention; FIGS. 3, 4, and 5 are diagrams illustrating a circuit model to be processed according to the present invention; FIG. FIG. 7 is an explanatory diagram of the process of the present invention; FIG. 8 is an explanatory diagram of another process of the present invention. In the figure, 10, 12: FF 14: circuit model 16: clock SKEW value occurrence time storage unit 18: event occurrence time storage unit 20: hold time reference value storage unit 22: setup time reference value storage unit 24: calculation unit 26: First comparison unit 28: Second comparison unit 30: Racing determination processing unit 32: Delay over determination processing unit 34: Setup abnormality determination processing unit 36, 44: Memory controller 38: Function code setting unit 40: Decoder 42, 50 , 52: Register 46: Check event occurrence control circuit 48: Check event occurrence time memory 54: Abnormal status register 56, 58: Check primitive

Claims (4)

(57) [Claims] At least a first component constituting a logical design model is provided.
A circuit model (14) in which a latch FF (10) and a second latch FF (12) are sequentially connected to each other as a unit to execute a logic simulation, wherein the circuit model (14) is configured. The first and second FFs (1
The generation time of the clock input (CLK2) for the second FF (12) is stored as the clock SKEW value generation time (tc) based on the SKEW value defined by the time difference between the clock inputs (CLK1, CLK2) for (0, 12). A clock SKEW value generation time storage unit (16); and first and second FFs (1) constituting the circuit model (14).
0,12) receives clock input (CLK1) and then outputs (Q1)
An event occurrence time storage unit (18) storing an event occurrence time (ti) at which the state of the circuit model changes; and first and second FFs (1) constituting the circuit model (14).
A hold time reference value storage unit (20) storing a hold time reference value (Th) of (0, 12); and first and second FFs (1) constituting the circuit model (14).
A setup time reference value storage unit (22) storing a setup reference value (Ts) of (0, 12); read out from the event occurrence time storage unit (18) when executing a logic simulation of the circuit model (14); By subtracting the SKEW occurrence time (ts) read from the clock SKEW value occurrence time storage unit (18) from the event occurrence time (ti), the delay time from the clock input to the output event occurrence of the circuit model (14) and the clock A calculation unit (24) for calculating a time difference (ΔF) from the SKEW value; a calculation time difference (ΔF) of the calculation unit (24) and a hold time reference value (Th) read from the hold time reference value (20) And a first comparison unit (26) that compares the calculation time difference (ΔF) of the calculation unit (24) and the setup time reference value (Ts) read from the setup time reference value storage unit (22). Second comparator for compare (2
8) ;; a racing determination processing unit (30) for determining a racing based on the comparison result of the first comparison unit (26); and delay over and setup based on the comparison result of the second comparison unit (28). A racing check method for a simulation device, comprising: a delay over determination processing section (32) for determining abnormality and a setup abnormality determination processing section (34). 2. The racing judging section (30) has a calculation time difference (ΔF) with respect to an output event of a first FF (10) constituting the circuit model (14) which is positive and the second FF ( 2. The racing check method of the simulation apparatus according to claim 1, wherein when the hold time is smaller than the hold time reference value (Th2) of (12), racing is determined. 3. The delay over determination processing section (34).
Means that the operation time difference (ΔF) with respect to the output event of the first FF (10) constituting the circuit model (14) is negative and the absolute value (| ΔF |) of the operation time difference is the second FF
When the setup time reference value (Ts2) of (12) is longer than
2. The method according to claim 1, wherein it is determined that the delay is over.
The racing check method of the simulation device described. 4. The setup abnormality determination processing section (34).
Is that the operation time difference (ΔF) with respect to the output event of the first FF (10) constituting the circuit model (14) is negative and the absolute value (| ΔF |) of the operation time difference is the second FF (1).
2. A setup abnormality is determined when the setup time reference value (Ts2) is smaller than the setup time reference value (Ts2).
The racing check method of the simulation device described.