JP2000013365A - Clock transfer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a long time slip due to jitter in a clock in the vicinity of a slip point. SOLUTION: When a read address of a buffer memory 2 is being deviated from, e.g. a central initially set area and enters a slip point detection area, a detection signal is outputted and the read address is automatically switched to an address in excess of a write address in a deviating direction from the detected address, that is, a point A or C at a lower end address of the area. Or the read address is switched to an area midpoint, that is, a point B at the detection of a first slip point, and switched to the point A or C in the same deviating direction at detection of 2nd slip point. Since the points A, C are selected with a margin to absorb phase jitter in a clock or the like with respect to the write address respectively, that is, to provide a hysteresis, the slip takes place only once and production of a long time slip is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock transfer circuit, and more particularly to a clock transfer circuit for connecting two data signals having different clock frequencies or different clock accuracies.

[0002]

2. Description of the Related Art Generally, when a transmission line for digital signals such as voice data is connected to a transmission device or an exchange,
A clock transfer circuit is used to absorb a difference between both clock frequencies or clock precision. This clock transfer circuit uses a buffer memory capable of simultaneous writing and reading, and writes, for example, a data signal on the transmission line using a clock on the transmission line, and writes the data signal with a predetermined delay phase using a clock on the transmission device side. The data signal is read and output to the transmission device. This buffer memory is also called an elastic memory.

FIG. 4 is a block diagram showing this conventional example. In FIG. 4, transmission of a normal data signal is bidirectional, but one direction will be described as a representative. A serial / parallel conversion circuit 21 for serial / parallel conversion of an input data signal from a transmission path side, and an input clock (not shown) extracted from the input data signal are input, and a write address signal synchronized with the input clock is generated. A write address generating circuit 24 for sequentially writing the parallel-converted input data signals to the buffer memory 22, a buffer memory 22 for temporarily storing the input data signals, and an input data read from the buffer memory 22. A parallel / serial conversion circuit 23 for converting the signal from parallel to serial and outputting the output data signal to the transmission device side; a transmission device side input clock; a read address signal synchronized with the output clock; Read address generation time for sequentially reading input data signals from 22 2
5, a control circuit 26 which receives an input frame signal, an output frame signal, and each clock, and performs timing setting of address signals of the write address signal generating circuit 24 and read address signal generating circuit 25, detection of slip, and the like. It is composed of

The operation of this conventional example is as follows. The storage capacity of the buffer memory 22 is determined by the clock accuracy, the allowable slip time, the number of slips, and the like, but is usually designed to have a capacity to store bits for two frames of the input data signal. Each of the write address generation circuit 24 and the read address generation circuit 25 is composed of a ring counter, and the address signal circulates endlessly from the start point to the end point of the address area of the buffer memory 22.

The input data signal is serial / parallel converted and sequentially stored in a designated address area of the buffer memory 22 in byte units by a write address signal. At the time of the initial setting, the read timing of the read address is read simultaneously with the writing from the phase position delayed by one frame from the designated position of the write address signal. This timing setting is performed under the control of the control circuit 26. Buffer memory 2
2, the input data signal stored in the memory with a delay of one frame by the read timing signal is read and output to the transmission device as an output data signal. In this way, the transfer of blocks between input and output is performed.

As described above, the read timing of the read address signal starts at the read position with a delay phase of one frame, but the write position and the read position may overlap with time due to phase fluctuation between clocks and the like. At this time, slip occurs.

[0007]

As described above, in the conventional example, slip occurs when the read position of the read address signal overlaps the write position of the write address signal due to the phase or frequency fluctuation between the input and output clocks. . This slip occurs when the read position of the read address signal is deviated from the initially set position in the advance direction (toward the write position), and when they overlap, the read data is read twice for two frames and with a lag phase. If they overlap, skip reading for two frames is performed. This slip becomes a data error of the output data signal, and hinders the receiving side.

When the read position of the read address signal continuously changes in the same direction (for example, when there is a frequency difference between input and output clocks), this slip occurs once for every two frames. However, such an amount may not be a major obstacle depending on the transmission equipment on the receiving side. However, when the read position of the read address signal fluctuates back and forth at the slip point (when the phase of the input / output clock temporarily fluctuates back and forth due to jitter or the like), the slip continues during this fluctuation. appear. That is, the slip time may be extremely long due to this cause. Particularly, when the accuracy of both input and output clocks is high, the slip becomes long and the probability of occurrence becomes high. At this time, there is a problem that the transmission equipment on the receiving side is seriously affected.

According to the present invention, the occurrence of slip is detected in advance, and the read position of the read address signal is shifted beyond the write position in the deviating direction and close to the write position (the hysteresis for absorbing the temporary phase fluctuation of the input / output clock). Automatically switch to the position where you took the minute) or detect the occurrence of slip,
After resetting to the initial setting position, this switching occurs multiple times in the same direction, and then automatically switches to a position close to the writing position, thereby preventing long-term slip due to phase jitter etc. It is.

The occurrence of a one-time slip when the readout position continuously changes in the same direction rarely causes a great hindrance to signal restoration on the receiving side. It only appears as slight noise during demodulation.

[0011]

A clock switching circuit according to the present invention comprises a buffer memory for simultaneously performing writing and reading, and a ring counter for writing an input data signal to the buffer memory in synchronization with a clock of the input data signal. A read means using a ring counter which takes a predetermined delay phase from a write position of the write means and reads an output data signal from the buffer memory in synchronization with a clock on the output side. Detecting that the reading position of the reading means has shifted and approaching the writing position of the writing means, that is, detecting the approach of the occurrence of slip, shifting the reading position of the reading means in the shifting direction and changing the writing position of the writing means. Reading position switching means for automatically switching to a predetermined position beyond the predetermined position.

Further, the reading position switching means detects the approach of the occurrence of slip and shifts the reading position of the reading means to a position beyond the writing position of the writing means in the direction of the slip and close to the writing position. The switching may be performed automatically.

The read position switching means detects the approach of the occurrence of a slip, and shifts the read position of the read means to the center of the ring address of the buffer memory beyond the write position of the write means in the direction of the slip. If the switching in the same shear direction is performed a plurality of times in succession, the next time the approach of slip occurs is detected, the read position of the reading means is changed in the writing direction by the writing means. The position may be automatically switched to a position exceeding the insertion position and close to the writing position.

[0014] Further, there may be provided a slip monitoring means for monitoring a switching operation of the reading position switching means and outputting a slip signal for each direction of the reading position of the reading means in synchronism with a slip generated by the switching operation. .

The slip monitoring means may include means for counting the number of occurrences of the slip signal and generating an alarm when the number of occurrences of the slip signal is reached.

Further, the slip monitoring means may include a display means for visually recognizing the slip signal.

[0017]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention, FIG. 2 is a block diagram illustrating the operation of the read position switching control circuit of FIG. 1, and FIG. 3 is a flowchart illustrating the operation of the read position switching control circuit of FIG. It is.

In FIG. 1, this figure shows a clock transfer circuit for connecting a transmission line used for audio data signals and the like to a transmission device, and shows only one of the bidirectional transmission lines as a representative. It is.

A serial / parallel conversion circuit 1 for serial / parallel conversion of an input data signal from the transmission path side;
An input clock (not shown) extracted from the input data signal is input, a write address signal synchronized with the input clock is generated, and a write address for sequentially writing the parallel-converted input data signals to the buffer memory 2 is written. A generating circuit 4, a buffer memory 2 for temporarily storing an input data signal, and a parallel / serial for converting the input data signal read from the buffer memory 2 from parallel to serial and outputting the output data signal to the transmission device side A conversion circuit 3, a readout address generation circuit 5 which receives an output clock on the transmission device side, outputs a readout address signal synchronized with the output clock, and sequentially reads out input data signals from the buffer memory 2, and an input frame signal; An output frame signal and each clock are input, and a write address signal generation circuit 4 and a read address Read position switching control circuit 6 for detecting the timing setting at the time of initial setting of the address signal with the read signal generating circuit 5 and the approach of the slip point, and switching the read position of the read address signal; , And a slip monitoring circuit 7 for displaying a slip alarm and a display at the time of slip.

Next, the operation of FIG. 1 will be described with reference to FIGS. The buffer memory 2 has a capacity to store bits for two frames of the normal input data signal in consideration of the clock accuracy, the allowable slip time or the number of slips.

Each of the write address generation circuit 4 and the read address generation circuit 5 is constituted by a ring counter, and the address signal circulates endlessly from the start point to the end point of the address area of the buffer memory 2.

The input data signal is serial / parallel converted and sequentially stored in a designated address area of the buffer memory 22 in byte units by a write address signal. At the time of initialization, the read timing of the read address is read simultaneously with writing from a position delayed by one frame from the position specified by the write address signal. This timing setting is performed under the control of the reading position switching control circuit 6. The input data signal stored in the buffer memory 2 with a delay of one frame in accordance with the read timing signal is read and output to the transmission device as an output data signal. In this manner, the clock transfer between the input and the output is performed.

As described above, the read timing of the read address signal is started at the read position with a delay phase of one frame. However, the write position and the read position may overlap with time due to phase fluctuation between clocks or the like. At this time, slip occurs.

The operation of the read position switching control circuit 6 at the slip occurrence point will be described with reference to FIGS. In FIG. 2, the buffer memory 2 has an address area for two frames. At the time of initial setting, writing starts from the lower end position of the address area. Return to and continue the ring count. On the other hand, reading is started from the lower end position when writing is started and reaches one frame, that is, when it reaches the center position of the address area, and increments are repeated sequentially in the same manner as writing to continue ring counting. This write / read timing setting is performed by controlling the output timing of the write address generation circuit 4 and the read address generation circuit 5 by the control signal of the read position switching control circuit 6.

As shown in FIG. 2, when the read position moves from the center initial set point in the advancing direction, for example, approaches the write position at the upper end position of the area and enters the slip point detection area shown by oblique lines. A detection signal indicating the approach is output, and the read position is beyond the write position in the leading direction from the detection point;
That is, it automatically switches to the point A at the lower end of the area. Also, when the reading position is shifted from the initial setting point in the delay direction indicated by the dotted line, and enters the slip point detection area at the lower end position of the area, for example, the position where the reading position exceeds the arrival position in the delay direction from the detection point, That is, it automatically switches to the point C at the upper end of the area.

The points A and C are separately set so as to absorb temporal fluctuations such as clock phase jitter with respect to the write position, that is, to provide hysteresis. Also, the slip at the slip point can be prevented only once and the occurrence of the slip for a long time can be prevented.

The switching of the reading position is performed under the control of the reading position switching control circuit 6. That is, the reading position switching control circuit 6 inputs the frame signal and the clock of the input / output data signal, detects the deviation of the reading position and the approach of the slip point based on the phase comparison of the two frame signals and the clock cycle. The address position of point A and C of
The operation is performed by U and a control signal is output to the read address generation circuit 5.

The buffer memory 2 has a capacity of 80 bytes for two frames when a 40-byte capacity is used for one frame of an input / output data signal. If the switching point hysteresis is about 10 bytes, a capacity of 95 bytes is required.

Next, another embodiment will be described with reference to FIG. In the above-described embodiment, the reading position is switched to the point A or the point C by detecting the slip point. However, in other embodiments, the reading position is changed to the center position of the area by detecting the first slip point, that is, Switch to point B, and switch to point A or point C in the same direction when the slip point is detected for the second time. That is, as shown in FIG. 3, when a slip point is detected, it is first discriminated whether the slip direction is a leading direction or a lagging direction. It is point B if it is the first time. If the detection is in the lag direction, the detection is switched to the point C when the detection is performed two or more times, and to the point B if the detection is performed for the first time.

This switching process is performed by the CPU of the read position switching control circuit 6 and is executed by the control signal of the read address generation circuit 5. As described above, by confirming the continuity of the read position in the deviation direction and then switching to the point A or the point C, the phase fluctuation of the clock of the input / output data signal is not continuous in the same direction (frequency difference) but is caused by temperature fluctuation or the like. This has the effect of preventing the occurrence of a long-term slip without shortening the guaranteed time during which the slip does not fluctuate when it fluctuates back and forth in time due to factors.

The slip monitoring circuit 7 monitors the switching operation of the read switching control circuit 6, and outputs a slip signal in synchronism with the slip time accompanying the switching of the reading position for each direction of displacement of the reading position. This slip signal is used for data error correction processing on the receiving side. Also, the number of times of output of the slip signal is counted, and an alarm is generated when a large number of abnormalities are counted per unit time. Further, the indicator light is turned on while the slip signal is being generated, so that the slip can be visually recognized.

[0032]

As described above, the clock transfer circuit of the present invention detects the approach of the occurrence of the slip by the reading position, that is, by the direction of the clock deviation, and detects the position where the reading position exceeds the writing position in the deviation direction. Since the switching is automatically performed, the effect of preventing the occurrence of a long-time slip caused by the clock phase jitter or the like near the slip occurrence point is obtained.

In particular, if the switching is performed after confirming the continuity of the read position in the deviation direction, the slip guarantee time without slip is reduced without shortening the slip even if the clock deviation direction is not one direction but goes back and forth. This has the effect of preventing the occurrence of slips in time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an operation of a read position switching control circuit in FIG. 1;

FIG. 3 is a flowchart for explaining another embodiment of the read position switching control circuit in FIG. 1;

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Serial / parallel conversion circuit 2 Buffer memory 3 Parallel / serial conversion circuit 4 Write address generation circuit 5 Read address generation circuit 6 Read position switching control circuit 7 Slip monitoring circuit

Claims (6)

[Claims] 1. A buffer memory for simultaneously performing writing and reading, writing means using a ring counter for writing an input data signal to the buffer memory in synchronization with a clock of the input data signal, and a clock on an output side. A reading means using a ring counter for taking a predetermined delay phase from a writing position of the writing means and reading an output data signal from the buffer memory in synchronism with the writing means; A read position for automatically switching the read position of the read means to a predetermined position beyond the write position of the write means by detecting the approach of the write means, that is, the approach of the occurrence of slip; A clock transfer circuit comprising switching means. 2. The reading position switching means detects the approach of the occurrence of slip and shifts the reading position of the reading means to a position beyond the writing position of the writing means in the direction of the slip and close to the writing position. 2. The method according to claim 1, wherein the switching is performed automatically.
Clock transfer circuit described 3. The read position switching means detects the approach of the occurrence of slip, and shifts the read position of the read means to the center of the ring address of the buffer memory beyond the write position of the write means in the direction of the slip. If the switching in the same shear direction is performed a plurality of times in succession, the next time the approach of slip occurs is detected, the read position of the reading means is changed in the writing direction by the writing means. 2. The clock transfer circuit according to claim 1, wherein the clock switching circuit automatically switches to a position exceeding the insertion position and close to the writing position. 4. A slip monitoring means for monitoring a switching operation of the reading position switching means and outputting a slip signal for each direction of a shift of a reading position of the reading means in synchronization with a slip generated by the switching operation. Claim 1,
2. The clock transfer circuit according to 2 or 3. 5. The clock transfer circuit according to claim 4, wherein said slip monitoring means includes means for counting the number of occurrences of said slip signal and generating an alarm when the number of occurrences of said slip signal reaches an abnormal number. 6. The clock transfer circuit according to claim 4, wherein said slip monitoring means includes display means for visually recognizing said slip signal.