JP2000013155A - Sample-and-hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by connecting a bias switch to the gate of a current power MOS transistor in an FET operational amplifier, selectively connecting a plurality of bias voltages to the gate with the bias switch and reducing supply current in a holding period when necessary current is comparatively less. SOLUTION: Outputs from the FET operational amplifiers AMP1 and 2 of a sample-and-hold circuit SH1 are fed back to an inverting input terminal. Input switches SW31 and 32 are connected to the noninverting inputs of AMP 1 and 2 and the output of AMP1 is connected to AMP2 through SW32. Input voltage Vi3 is connected so SW31 and it is controlled by a clock Φ 1. Ground capacitance Cg for setting potential when SW is opened is connected to the noninverting inputs of AMP1 and 2. A clock Φ 2 is inputted to AMP, two types of bias voltages B1 and B2 are connected to AMP and they are selected by Φ 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample-and-hold circuit, and more particularly to a FET operational amplifier whose output is fed back to an inverting input, and an input voltage connected to a non-inverting input of the FET operational amplifier. And a sample-and-hold circuit provided with an input switch.

[0002]

2. Description of the Related Art Digital technology in computer science has been remarkably developed with the advance of microfabrication technology, but the amount of capital investment is increasing at an accelerating rate, and at present analog technology and analog / digital mixed technology are being developed. Is attracting attention. Therefore, the applicant has proposed a filter circuit that uses an analog voltage as an input signal and filters the analog voltage as it is (Japanese Patent Application Laid-Open No. 06-1643).
No. 21).

In such a filter circuit, it is necessary to hold a large number of input voltages in time series, and a multi-stage sample-and-hold circuit is indispensable. Have been successful.

However, in view of application to portable information devices and ecology, further power saving has been desired.

SUMMARY OF THE INVENTION The present invention has been made under such a background, and an object of the present invention is to provide a sample and hold circuit consuming less power.

[0005]

In a sample and hold circuit according to the present invention, a bias switch is connected to the gate of a current source MOS transistor in an FET operational amplifier, and a plurality of bias voltages are selectively applied to the gate by the bias switch. This is to reduce the supply current during a hold period in which the required current is relatively small in the sample and hold circuit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the sample and hold circuit according to the present invention will be described with reference to the drawings.

[0007]

FIG. 1 shows a first embodiment of a sample-and-hold circuit. A plurality of sample-and-hold circuits SH1 to SHn are connected in series, and an input voltage Ai is input to a first-stage sample-and-hold circuit SH1. Clocks Φ1, Φ1 ′, and Φ2 are input to each sample and hold circuit, and clocks Φ1
Sets the sample hold timing of each of the sample hold circuits SH1 to SHn, sets the data transfer timing by the clock Φ1 ′, and sets the clock Φ2
Controls the supply current.

In FIG. 3, a sample hold circuit SH
1 has FET operational amplifiers AMP1 and AMP2, the output of which is fed back to the inverting input. Operational amplifier AMP
1. The input switch SW31 is connected to the non-inverting input of AMP2.
SW32 are connected respectively, and the output of AMP1 is SW3
2 is connected to AMP2. Further, an input voltage Vi3 (corresponding to Ai in FIG. 1) is connected to the switch SW31. SH2 to SHn are configured in the same manner as SH1, but Vi3 is the output of the sample-hold circuit in the preceding stage. The input switch SW31 is controlled by the clock Φ1, and a non-inverting input of the operational amplifiers AMP1 and AMP2 is connected to a ground capacitance Cg for setting a potential when SW3 is opened. The clock φ2 is input to the operational amplifier AMP, and the operational amplifier AMP
Are connected to two kinds of bias voltages B1 and B2.
These bias voltages B1 and B2 are selected by Φ2. Vi3 is held by Cg when the SW 31 shifts from the closed state to the open state, and then transferred to the subsequent stage as the output Vo3 of the AMP2 when the SW 32 is closed. At the time of this transfer, it is necessary to open the SW 31 so that the influence of the preceding stage does not affect the transfer output.

FIG. 2 shows a second embodiment in which an input voltage Ai is supplied to a plurality of sample-and-hold circuits SH1'-SH.
n ′, and clocks Φ1 and Φ2 are input to each sample and hold circuit. Clock Φ
1 operates the sample and hold circuit sequentially to execute sampling, and the clock Φ2 controls the supply current in synchronization with the sampling timing. The sample hold SH1 'in the above embodiment is configured as shown in FIG. 4, and the other sample hold circuits are the same.

Referring to FIG. 4, a sample hold circuit SH is provided.
1 'has a FET operational amplifier AMP, the output of which is fed back to the inverting input. An input switch SW4 is connected to the non-inverting input of the operational amplifier, and an input voltage Vi4 is connected to the switch SW4. For SH1 ', Vi4 corresponds to Ai in FIG. 2, and for SH2' to SHn ', similarly, Ai in FIG. 2, but the timing for sampling the input signal is different. The input switch SW4 is controlled by the clock Φ1,
The non-inverting input of the operational amplifier AMP is connected to a ground capacitance Cg for setting a potential when SW4 is opened. The clock Φ2 is input to the operational amplifier AMP, and the operational amplifier AMP has two types of bias voltages B1,
B2 are connected, and these bias voltages B1, B
2 is selected by Φ2.

FIG. 5 shows a circuit showing an operational amplifier AMP, in which a MOS transistor T2 having an inverting input (indicated by a minus sign) connected to a gate and a non-inverting input (indicated by a plus sign) is connected to a gate. The MOS transistor T3 forms a differential amplification pair circuit. T2, T3
Is commonly connected at one terminal to a power supply voltage Vcc via a current source MOS transistor T1, and M
It is connected to a current mirror circuit composed of OS transistors T5 and T6. The outputs of T3 of T2 and T3 are MOS transistors T for inverting the output (Aout).
4 and one terminal of T4 is connected to the power supply voltage Vcc via the current source MOS transistor T2.

A two-input one-output bias switch SW41 is connected to the gate of the transistor T1, and the bias voltages B1 and B2 are input to the SW41. A bias switch SW42 having two inputs and one output is connected to the gate of the transistor T2, and the bias voltages B1 and B2 are input to SW42. SW41 and SW42 are controlled to open and close by the clock Φ2, and the bias voltage B
1, B2 are alternatively applied to the gates of T1, T2.
Needless to say, if the matching of the sizes of T1 and T2 is ensured, the output of one bias switch can be commonly input to T1 and T2 to reduce the circuit scale.

The sample and hold circuit closes SW3 to apply a new input voltage, and requires a current during a period until the output is stabilized, that is, a sampling period, and then requires a current during a holding period during which SW3 is opened. Is slight. Here, the bias voltage B1 is B
Assuming that it is larger than 2, B2 during the sampling period
And B1 is applied during the holding period.

FIG. 6 shows the timings of the clocks Φ1, Φ1 'and Φ2 in the first embodiment (FIG. 1).
In FIG. 1, “S” indicates a sampling period, “H” indicates a holding period, and “T” indicates a data transfer period to a subsequent stage in the clock Φ1 ′. In the clock Φ2, “B1” indicates a period during which the bias voltage B1 is applied, and “B2” indicates a period during which the bias voltage B2 is applied. The period “B2” includes the sampling period “S” and a predetermined period immediately before and immediately after the sampling period, so that a sufficient current is reliably supplied during the sampling period. In addition, the other period “B
In "1", the supply current is minimized, thereby reducing the power consumption of the sample and hold circuit. Further, as described above, when data is transferred, it is necessary to open the switch SW31 and perform a new sample hold after the data transfer is completed. Therefore, Φ1 ′ rises when Φ1 falls. Thereafter, Φ2 rises before Φ1 falls, and Φ2 rises after Φ1 falls.

FIG. 7 shows SH in the second embodiment (FIG. 2).
Clocks Φ1 (1), Φ2 for 1 ′, SH2 ′
(1), Φ1 (2), Φ2 (2) timings,
The meanings of “S”, “H”, “B1”, and “B2” are the same as in FIG. In this embodiment, the sample and hold circuit alternatively performs sampling and holding sequentially,
After the period “S” of (1) and the period “B2” of Φ2 (1) synchronized therewith, Φ1 (1) continuously becomes the period “H” and Φ2 (1) continuously becomes the period “H”. "B1" is obtained. On the other hand, Φ1 (2) and Φ2 (2) correspond to the period “S” of Φ1 (1), the period “H” immediately after the period “B2” of Φ2 (1), and the period “S” from the period “B1”. The period shifts to the period “B2”, and then returns to the period “H” and the period “B1” again.

As in the first embodiment, the power consumption is reduced by controlling the switch by the signal Φ2 in the second embodiment.

The current variable operational amplifier can be applied to optimization of current consumption in applications other than the sample and hold circuit, and a larger number of bias voltages can be applied. Further, precise optimal control can be realized by continuously changing the bias voltage.

FIG. 8 shows a matched filter circuit using the above sample and hold circuit. In the spread spectrum communication, a high-speed correlation operation is required to spread data by a predetermined spreading code and to despread and demodulate the data. Generally, a SAW filter, a sliding correlator, or a matched filter is used for this correlation operation, but the matched filter is superior in the speed of initial synchronization acquisition. However, the matched filter has a large circuit scale and generally consumes a large amount of power.

In the matched filter shown in FIG. 8, the analog input signal Ain is held by two lines of sample-and-hold circuits S11 to S1n and S21 to S2n, so-called double sampling is performed. The sampling of each system is the same frequency clock C shifted by 周期 cycle.
This is performed in synchronization with LK0 and CLK1, and Ain is sequentially taken into one sample and hold circuit. That is, there is only one sample and hold circuit that takes in data at a certain timing, and only this sample and hold circuit requires relatively large current consumption. 1st, 2nd
Corresponding sample and hold circuits S11 and S21 of the system,
S12 and S22,. . . , S1n and S2n are connected to selectors SEL1 to SELn, respectively, so that any one of the sample data is selectively output. The output of each selector is input to multiplexers MUX1 to MUXn controlled by the spreading code sequence PN, and each multiplexer distributes the output to two systems, positive and negative, according to the spreading code. The output of the multiplexer is input to the adder ADD, where the sum of the data of the negative system is subtracted from the sum of the data of the positive system internally, and the analog output A
out is generated.

The spreading code sequence PN is a shift register SRE.
G, and the last stage is fed back to the first stage. The clock CLK0 or CLK
The same clock CLKS as 1 is input, and the spread code sequence is cyclically shifted in synchronization with the data being taken into the register. CLK0 and CLK1 are S11-S1n, S21-S
The data is cyclically fetched into 2n, and the fetched data and the spreading code sequence correspond to each other. When a new spreading code is taken into the shift register, CL is supplied while data is supplied to the data input terminal Din of the first stage.
Enter KS.

In the above matched filter, the number of sample and hold circuits in one system is on the order of several hundreds to several thousands, and the number is double in double sampling, and in proportion to the multiple in the case of higher-order oversampling. Increase. In such a huge number of sample and hold circuits, a relatively large current that satisfies the settling time requirement is supplied only to the sample and hold circuit that only takes in data, and a relatively small current is supplied to the sample and hold circuits in other hold modes. Is supplied, the power consumption can be greatly reduced as compared with the case where a constant current is always supplied to all the sample and hold circuits. This is an essential configuration when applying spread spectrum communication to a portable terminal.

[0022]

As described above, in the sample and hold circuit according to the present invention, a bias switch is connected to the gate of the current source MOS transistor in the FET operational amplifier, and a plurality of bias voltages are selectively applied to the gate by the bias switch. Since the connection and the supply current in the hold period in which the required current is relatively small in the sample-and-hold circuit are reduced, there is an excellent effect that the power consumption is small.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a sample and hold circuit according to the present invention.

FIG. 2 is a block diagram showing a second embodiment.

FIG. 3 is a circuit diagram showing one sample and hold circuit in the first embodiment.

FIG. 4 is a circuit diagram showing one sample and hold circuit in a second embodiment.

FIG. 5 is a circuit diagram showing the operational amplifier in FIG. 3;

FIG. 6 is a timing chart showing the operation of the switch in the first embodiment.

FIG. 7 is a timing chart showing the operation of the switch in the second embodiment.

FIG. 8 is a block diagram showing a matched filter circuit using a sample and hold circuit according to the present invention.

[Explanation of symbols]

SH1 to SHn, SH1 'to SHn', S11 to S1n,
S21 to S2n. . . Sample hold circuit AMP, AMP1, AMP2. . . Operational amplifiers T1 to T6. . . MOS transistors Ai, Vi3. . . Input voltage Ai (t) to Ai (t−n + 1), Vo3. . . Output voltage SW31, SW32, SW4, SW41, SW4
2. . . Switches SEL1 to SELn. . . Selector MUX1 to MUXn. . . Multiplexer ADD. . . Adder circuit SREG. . . Shift register Cg. . . Capacitance B1, B2. . . Bias voltage Φ1, Φ1 ', Φ2, CLK0, CLK1, CLK
S. . . Clock Vcc. . . Power supply voltage PN. . . Spreading code Ain. . . Analog input signal Aout. . . Analog output signal. 1 reference number = YZ19707087A

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J023 CA01 CB01 5J029 AA01 BA05 CA13 EA04 5J066 AA01 AA47 CA36 FA10 HA10 HA29 HA38 KA02 KA06 KA09 KA12 KA19 KA26 KA33 MA11 ND01 ND22 ND23 PD01 SA13 TA01 TA06

Claims (8)

[Claims] 1. A sample-and-hold circuit comprising: a FET operational amplifier having an output fed back to an inverting input; and an input switch connected to an input voltage and connecting the input voltage to a non-inverting input of the FET operational amplifier. , The FE
A bias switch connected to the gate of the current source MOS transistor in the T operational amplifier, the bias switch selectively connecting a plurality of bias voltages to the gate; and reducing a supply current in the hold period from the sample period. Sample and hold circuit. 2. An output of the FET operational amplifier is connected to a second-stage FET operational amplifier via a switch.
2. The sample-and-hold circuit according to claim 1, wherein the output of the FET operational amplifier in the stage is fed back to its inverting input. 3. The sample according to claim 1, wherein the bias switch supplies a sufficient current for a predetermined period immediately before and immediately after the sample period as in the sample period. Hold circuit. 4. A plurality of sample-and-hold circuits according to claim 1, wherein an input voltage is commonly connected to all of the input switches, and the input switches are selectively closed by a control signal. A sample and hold circuit provided with independent bias switches, wherein the bias switches are switched only in the sample and hold circuits in which the input switches are closed among the bias switches. 5. A plurality of sample-hold circuits according to claim 2, which are provided in series, are opened and closed at a common timing by controlling all input switches with a common control signal, and a bias switch of each sample-hold circuit is shared. A sample and hold circuit characterized by switching at a timing. 6. An operational amplifier, wherein a bias switch is connected to a gate of a current source MOS transistor, and the bias switch selectively connects a plurality of bias voltages to the gate. 7. An output of the sample and hold circuit according to claim 4 is connected to a multiplication circuit for multiplying the output by a multiplier, and an output of the multiplication circuit is connected to an addition circuit for calculating the sum of these outputs. A filter circuit connected to the multiplier circuit, the register holding a multiplier of the multiplier circuit and cyclically shifting the held multiplier in synchronization with opening and closing of an input switch. 8. The output of the sample and hold circuit according to claim 5 is connected to a multiplier circuit for multiplying the output by a multiplier, and the output of the multiplier circuit is connected to an adder circuit for calculating the sum of these outputs. A filter circuit, wherein a register for holding a multiplier of the multiplication circuit is connected to the multiplication circuit.