JPH0645892A - Signal delay circuit - Google Patents

Abstract

PURPOSE:To constitute a variable delay circuit where CMOS inverters are used to easily control the delay time and the phase error does not occur. CONSTITUTION:CMOS inverters 10-1 to 10-n in many stages are constituted in an IC 31 to constitute a cascade connecting circuit. The pulse frequency modulation signal or the like which has analog information on the time axis is inputted from an input terminal 13 to the gate of the inverter 10-1 in the first stage and is successively delayed in respective stages and is outputted from an output terminal 15. Control voltages v1 and v2 of MOS-FETs 16 and 18 for delay time control use arranged on the outside of the IC 31 are controlled to control the delay times of CMOS inverters 10-1 to 10-n in respective stages in common.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal delay circuit whose delay time can be easily controlled.

[0002]

2. Description of the Related Art Various delay circuits for electric circuits have been considered in the past. For example, a physical delay line, a distributed constant circuit, a BBD (charge transfer device), a CCD (charge coupled device), and a digital system are shifted. Register or RAM
Widely spread to program control using.

[0003]

By the way, there are various technical fields in which delay time can be arbitrarily changed in a delay circuit, but it is difficult to use a delay line or a distributed constant circuit, and an electrical transfer is required. BB using clock pulse
A general method is to control the frequency of the clock using a D, CCD, shift register or the like. However, since the method of delaying using a BBD, CCD, shift register, etc. transfers a signal using a clock pulse, since the signal is sampled by the clock, the resolution of the time axis is defined by the clock cycle. Is
For example, when a signal such as a pulse frequency modulation signal having analog information on the time axis is delayed, the delayed output has a drawback that a phase error occurs. To solve this, theoretically, the clock should be made extremely fast to improve the resolution. Then, in order to obtain the target delay time, the number of stages of elements such as BBD, CCD, shift register, etc. is increased. It had to be made, and there was a drawback that it became technically difficult.

The present invention is intended to solve the above-mentioned drawbacks of the prior art and to provide a signal delay circuit in which the delay time can be easily controlled and the signal can be delayed without causing a phase error.

[0005]

SUMMARY OF THE INVENTION The present invention comprises a plurality of CMOS gate circuits connected in tandem to input a binary signal having analog information on a time axis and for controlling the time axis, A CMOS gate cascade connection circuit for sequentially delaying and outputting at each stage by utilizing the signal delay characteristics of the CMOS gate circuit itself, and a voltage provided to the power supply path of the CMOS gate circuit and applied to each CMOS gate circuit Is controlled to be a common value and an arbitrary value.
Voltage control means for controlling the signal delay time between the input and output of the gate cascade connection circuit to an arbitrary value to control the time axis of the binarized signal to a desired state. It is characterized in that the connected CMOS gate circuits are formed on the same substrate.

[0006]

According to the means for solving the problems of the present invention, a plurality of CMOS gate circuits are cascade-connected to each other to sequentially delay and output the signals by utilizing the signal delay characteristics of the CMOS gate circuits themselves. The delay time of the CMOS gate circuit is controlled by controlling the applied voltage of the CMOS gate circuit by the voltage control means by utilizing the fact that the delay time changes depending on the applied voltage.

According to this, the delay time can be easily controlled only by controlling the voltage applied to the CMOS gate circuit. Further, since the voltages applied to the CMOS gate circuits of a large number of stages are commonly controlled, the structure of the voltage control means is simple and the control is easy even if the number of stages of the CMOS gate circuits is large. Further, unlike a conventional delay circuit including a BBD, a CCD, a shift register, etc., the original signal is not sampled and transferred with a clock, but the original signal is continuously delayed as it is. A signal such as a pulse frequency modulated signal having analog information can be delayed without causing a phase error.

Further, since the multi-stage CMOS gate circuits are formed on the same substrate, the delay characteristics are well aligned, and the delay time variation characteristics with respect to the power supply voltage variation are also well aligned, so that the management of the variable delay time control is also very important. It will be easy.

[0009]

Embodiments of the present invention will be described below. First, FIG. 2 shows an example of a single CMOS gate circuit. This is a p-channel MOS-FET 12 and an n-channel MO.
Gates and drains of the S-FET 14 are connected to each other, power supply voltages V _DD and V _SS are applied to the sources, signals are input to the gates via the input terminal 13, and input signals to the output terminals 15 from the drains. An inverted signal is output.

In the CMOS inverter (CMOS gate circuit) 10, a delay time occurs between the input and the output. The delay time, as shown in FIG. 3, the power supply voltage V _DD
Depending on the -V _SS, large power supply voltage V _DD -V as _SS small delay time, greater rate of change. This is because the conductance of the element changes depending on the power supply voltage V _DD -V _SS . Therefore, by utilizing this property, the power supply voltage V
An arbitrary delay time can be set by controlling the delay time according to the size of _DD- V _SS . However, a single CM
Since only a small delay time can be obtained in the OS gate circuit, the CMOS inverters 10 are connected in multistage cascade as shown in FIG. 4 to secure a longer delay time. For example, when the power supply voltage V _DD -V _SS is 5 V, about 3.
If a delay of 5 ns is obtained, a delay time of 8000 × 3.5 ns = about 28 μs can be obtained by connecting 8000 stages in series. Further, FIG. 5 shows power supply voltage V _DD -V _SS vs. delay time characteristics when 80 stages are connected in series.

The delay time of the CMOS inverter circuit 10 also depends on the element temperature (the conductance of the element changes depending on the temperature) as shown in FIGS. 3 and 5, and the higher the temperature, the longer the delay time.

The single CMOS gate circuit 10 shown in FIG.
6 shows an example of the configuration in which a voltage control means for controlling the applied voltage is added. This is a delay time control element 16 between the CMOS inverter 10 and its power supply V _DD -V _SS .
18 is inserted. In FIG. 6, the p-channel MOS-FET 12 and the n-channel MOS-FET 14 have their gates and drains connected to each other, and a signal is input from the gate and a signal is output from the drain. Between the source of the p-channel MOS-FET 12 and the power supply V _DD, and between the source of the n-channel MOS-FET 14 and the power supply V _SS , as a delay time control element,
p-channel MOS-FET16, n-channel MOS-F
Each ET18 is inserted. p channel MOS
The control voltages v1 and v2 are input from the terminals 20 and 22 to the gates of the -FET 16 and the n-channel MOS-FET 18, respectively. These control voltages v1 and v2 are the reference potential V _DD
A voltage symmetrical with respect to −V _SS (in other words, V _DD −v1
= V2- _Vss ). The control voltage v1,
By controlling the value of v2, a p-channel MOS-FET 12 and an n-channel M that form a CMOS inverter
The voltage applied to the OS-FET 14 changes, which changes the delay time (if V _DD -v1 = v2-V _SS is small, the p-channel MOS-FET 12 and the n-channel MO
S-FET 14 delay time increases the applied voltage of the CMOS inverter formed by the smaller, also, V _DD
If -v1 = v2- _Vss is large, the voltage applied to the CMOS inverter is small and the delay time is large).

FIG. 7 shows an example of the IC pattern of the circuit of FIG. This IC pattern also facilitates multi-stage connection.

Next, an embodiment of the present invention is shown in FIG.
Multiple-stage CMOS inverter (CMOS gate circuit) 1
0-1 to 10-n are formed on the same substrate in the IC 31, and are connected in cascade so that the drain output of the previous stage is input to the gate of the next stage to form a CMOS gate cascade connection circuit. In the gate of the first stage inverter 10-1,
A pulse frequency modulation signal or the like having analog information on the time axis is input from the input terminal 13, and sequentially delayed at each stage and output from the output terminal 15.

The delay time control element is arranged outside the IC 31. That is, the sources of the CMOS inverters 10-1 to 10-n that form the CMOS cascade connection circuit are connected to the power supply terminals 32 and 34, and the p-channel MOS-FETs 16 and n that form the voltage control means at the power supply terminals.
The channel MOS-FETs 18 are connected to each other, and the control voltages v1 and v2 are applied to their gates.
-Power supply V _DD , V _SS is CMOS through FET16,18
It is applied to the inverters 10-1 to 10-n.

According to this structure, the control voltage v1,
By controlling the delay time control MOS-FETs 16 and 18 with v2, the delay time of each stage can be controlled in common. As a result, the total delay time of the CMOS inverters 10-1 to 10-n is obtained between the input terminal 13 and the output terminal 15.

Also, a large number of CMOS inverters 10-
Since 1 to 10-n are formed on the same substrate in the IC 31, the delay characteristics are well aligned, and the delay time variation characteristics with respect to the applied voltage variation are also well aligned. Therefore, it is very easy to manage the variable delay time control. Become. That is, one C
In the MOS inverter, the delay time Tr of rising of the input signal is slightly different from the delay time Td of falling, but the CMOS inverters connected in multiple stages in the same IC 31 have the same Tr and Td, respectively. Fall (“H” →
The input signal of "L" is the first CMOS inverter 10
-1 delays Td, and the next CMOS inverter 10-2 delays Td.
r delay, and Td + Tr delay in total. Further, the rising (“L” → “H”) input signal is delayed by Tr in the first CMOS inverter 10-1, and the next CMOS inverter 1
Td is delayed by 0-2, and Tr + Td is also delayed. In this way, the front and rear CMOS inverters compensate for the uneven duty. Since the delay time change characteristics with respect to the power supply voltage are also uniform, the delay control can be easily managed. If the characteristics of the CMOS inverters are different, the delay time is different at each place of the cascade connection, and the delay time change characteristics with respect to the power supply voltage are also different, which makes it very difficult to manage even if variably controlled. However, such a problem can be solved by configuring them in the same IC 31.

By the way, in addition to the voltage control means described above, various configurations described below are conceivable.
In the following description, the CMOS gate circuit is shown as a single stage for convenience of description, but in reality, a plurality of stages are IC31.
Within the same substrate.

The voltage control means shown in FIG. 8 is provided with two delay time control elements. That is, the p-channel MOS-FET 16 and the n-channel MOS-FET 18 in the circuit of FIG.
The n-channel MOS-FETs 26 are connected in parallel. The gates of the p-channel MOS-FET 24 and the n-channel MOS-FET 26 are connected to terminals 28 and 30.
To control voltages v3 and v4, respectively. The control voltages v3 and v4 are input by a separate system by providing a manual operation or a control voltage generating circuit separately. As a result, the terminal 2
The delay times can be controlled in two systems by the voltages v1 and v2 input to 0 and 22 and the voltages v3 and v4 input to the terminals 28 and 30. This can be used, for example, when a coarse control signal is input to the terminals 20 and 22 and a dense control signal is input to the terminals 28 and 30 to control the delay time. Further, it can be used when one system performs control for stabilizing the delay time with respect to fluctuations in the power supply voltages V _DD and V _SS and element temperature change, and the other system performs variable control of the delay time.

The voltage control means of FIG. 9 is a p-channel MOS.
-FET16 and n-channel MOS-FET18 and p
Channel MOS-FET 24 and n-channel MOS-FE
Each T26 is connected in series. Also in this case, as in the embodiment of FIG. 8, the voltages v1 and v2 input to the terminals 20 and 22 and the voltages v3 and v input to the terminals 28 and 30 are used.
4, the delay time can be controlled by the two systems.

In the above voltage control means, the example in which the control elements are provided on both sides of the power supply has been shown, but the same effect can be expected on one side. The embodiment shown in FIG. 10 shows an example of such a configuration. This is p in the circuit of FIG.
Corresponds to the removal of the channel MOS-FET16,
The delay time control is performed only by the n-channel MOS-FET 18. Similarly, the n-channel MOS-FET 18 in the circuit of FIG. 6 can be deleted.

In the above embodiment, the control element is a CMO.
Although it is provided outside the S inverter, it may be provided inside. FIG. 11 shows an example of the p-channel MO.
C with S-FET 12 and n-channel MOS-FET 14
A MOS inverter is configured, and a p-channel MOS-FET 16 and an n-channel MOS-
The FET 18 is installed.

In the embodiment of FIG. 12, the circuit of FIG. 11 is connected in a plurality of stages, and a p-channel MOS-type MOS transistor for delay time control is further provided outside.
The FET 36 and the n-channel MOS-FET 38 are connected. In this circuit, MOS-FET16,18
Voltage v1, v2 applied to the gate of the
2 of the voltages v5 and v6 applied to the gates of T36 and 38
Delay time is controlled by the grid.

In the above embodiment, the control elements are connected in series to the MOS-FETs 12 and 14 which form the CMOS inverter, but they may be connected in parallel. FIG. 13 shows an example of the p-channel MO which constitutes a CMOS inverter.
The sources of the S-FET 12 and the n-channel MOS-FET 14 are connected to the power supplies V _DD and V _SS via the resistors R1 and R2, respectively, and the delay time controlling n-channel MOS-FET 16 is connected.
P-channel MOS-FET12, n-channel MOS-
The FET 14 and the resistor R2 are connected in parallel, and the delay time controlling p-channel MOS-FET 18 is connected in parallel to the resistor R1, the p-channel MOS-FET 12, and the n-channel MOS-FET 14. n-channel MOS-FET
The delay time is controlled by the voltages v2 and v1 input to the gates of the 16 and p-channel MOS-FETs 18, respectively. However, in this case, the relationship between the increase / decrease in the control voltages v1 and v2 and the increase / decrease in the delay time is opposite to that in FIG.

[0025]

As described above, according to the present invention, the CMOS gate has a delay time between input and output, and the delay time changes depending on the power supply voltage of the CMOS gate. Since the gate circuits are connected in cascade in plural stages and the voltage control means is provided in the power supply path of these CMOS gates and the voltage applied to the CMOS gates is controlled by this voltage control means, the delay time can be easily controlled. it can. Further, since the voltages applied to the CMOS gate circuits of a plurality of stages are commonly controlled, even if the number of stages of the CMOS gate circuits is large, the structure of the voltage control means is simple and the control is easy. In addition, conventional BBD, CCD,
Unlike a delay circuit such as a shift register that does not transfer the original signal by sampling it with a clock, the original signal is continuously delayed as it is. Therefore, for example, a pulse frequency modulated signal having analog information on the time axis It is possible to delay such a signal without causing a phase error.

Further, the frequency band of a single CMOS gate circuit is wide, and it is possible to follow an input signal having a considerably high frequency band with a margin. This is still usable at a high frequency even if a delay circuit having a relatively long delay time is formed by connecting multiple stages as in the present invention. Normally, the bandwidth of one-stage CMOS gate circuit is 100MH
Since the video signal is used at around 10 MHz, it can be used in a region where the frequency characteristic is not distorted even when used for delaying the video signal.

Further, since the signal delay circuit of the present invention does not use a capacitor, it is easy to integrate, and when the multistage connection circuit of CMOS gate circuits is integrated, the characteristics of each CMOS gate circuit become uniform, so that it is easy to manage. Become. Moreover, since there is no influence of stray capacitance as in the case of using a capacitor, the delay time can be controlled with high accuracy.

Furthermore, the CMOS gate circuit has the p-channel MOS-FET and the n-channel MOS-F as described above.
Although it is composed of ET, it is difficult to manufacture the ones having the opposite characteristics at the time of manufacture, and the delay time differs depending on whether the input signal is positive or negative. However, in the multi-stage connection of the CMOS gate circuits, the non-uniformity of the duty of the delayed CMOS gate circuits compensates for each other at the time of the pulse inversion, so that the difference in the delay time is not accumulated, and therefore, the distortion in the delay process of the signal does not occur. Phase error can be suppressed low.

Further, since the multistage CMOS gate circuits are formed on the same substrate, the delay characteristics are well aligned and the delay time variation characteristics with respect to the power supply voltage variation are also well aligned, so that the control of the variable delay time control is also performed. It will be very easy.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a CMOS gate circuit.

3 is a characteristic diagram showing a power supply voltage-delay time characteristic in the CMOS gate circuit of FIG.

FIG. 4 is a circuit diagram showing a state in which the CMOS inverters 10 of FIG. 2 are connected in cascade in a plurality of stages to obtain a long delay time.

5 is a characteristic diagram showing power supply voltage-delay time characteristics when the CMOS inverters 10 in FIG. 2 are connected in cascade in 80 stages.

FIG. 6 is a circuit diagram showing a configuration example in which voltage control means is added to a single CMOS gate circuit.

7 is an example of an IC pattern of the circuit of FIG.

FIG. 8 is a circuit diagram showing another embodiment of the voltage control means.

FIG. 9 is a circuit diagram showing another embodiment of the voltage control means.

FIG. 10 is a circuit diagram showing another embodiment of the voltage control means.

FIG. 11 is a circuit diagram showing another embodiment of the voltage control means.

FIG. 12 is a circuit diagram showing another embodiment of the voltage control means.

FIG. 13 is a circuit diagram showing another embodiment of the voltage control means.

[Explanation of symbols]

10-1 to 10-n CMOS gate cascade connection circuit 12 p-channel MOS constituting a CMOS gate circuit
-FET 13 input terminal 14 n-channel MOS forming a CMOS gate circuit
-FET 15 output terminals 16, 24, 36 p-channel MOS for delay time control-
FET (voltage control means) 18, 26, 38 n-channel MOS for delay time control-
FET (voltage control means) 20, 22 Delay time control voltage input terminal 31 IC (same substrate)

Claims (1)

[Claims] 1. A signal delay characteristic of a CMOS gate circuit itself, which is constituted by connecting a plurality of CMOS gate circuits in tandem, inputs a binary signal having analog information on the time axis and for controlling the time axis. And a CMOS gate cascade connection circuit for sequentially delaying and outputting at each stage, and a voltage applied to each CMOS gate circuit provided in the power supply path of the CMOS gate circuit to a common and arbitrary value. A voltage control means for controlling the signal delay time between the input and output of the CMOS gate cascade connection circuit to an arbitrary value by controlling, and controlling the time axis of the binarized signal to a desired state. A signal delay circuit, wherein the multi-stage cascade-connected CMOS gate circuits are formed on the same substrate.