JP2000012821A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device which is capable of being made high in integration and high in sensitivity by a method, wherein the capacity of the transmitted signal charge from photodiodes is reduced by making smaller the unit cell containing the photodiodes which include photosides. SOLUTION: A photoelectric converter arranged in two dimensinal matrix mode on a semiconductor substrate comprises first and second photoelectric conversion means containing photodiodes 1-1-1, 1-2-1, 1-1-2, 1-2-2 and transfer transistors 2-1-1, 2-2-1, 2-2-2, 2-2-2 for transferring the detection signals from these photodiodes and amplifying transistors amplifying the detection signals. Then, a perpendicular selecting transistor 4-1-1 for selecting the first an the second photoelectric converting means as well as a drain line connected to the drains of reset transistors 5-1-1, 5-1-2 are commonly used for reading out the detection signals of the first and second photoelectric converting means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state imaging device using an amplification type MOS image sensor.

[0002]

2. Description of the Related Art In recent years, as one of solid-state imaging devices, a solid-state imaging device using an amplification type MOS image sensor has been proposed (for example, Japanese Patent Application No. 8-53220). FIG. 3 is a circuit diagram showing a configuration of a conventional solid-state imaging device using an amplification type MOS image sensor.

As shown in FIG. 3, a conventional solid-state imaging device has photodiodes 21 arranged vertically adjacent to each other.
-1-1, 21-2-1, transfer transistors 22-1-1, 22-2- that transfer detection signals detected by these photodiodes
1, an amplification transistor 23-1-1 that amplifies the detection signal transferred by these transfer transistors, a vertical selection transistor 24-1-1 that selects a line for reading the detection signal amplified by the amplification transistor, Reset transistor 25-1-1 that resets the charge of the detection signal
Are arranged.

Similarly, as shown in FIG. 3, photodiodes 21-1-2, 21-2-2,..., 21-3-3, 21-4-3, transfer transistors 22-1-2, 22-. 2-2, ..., 22-3-3, 22-4-3, amplifying transistor 23-1-2, ..., 23-2-3, vertical selection transistor 24-1
-2, ..., 24-2-3 and reset transistor 25-1-2,
, 25-2-3 form a plurality of unit cells, and these unit cells are arranged in a two-dimensional matrix.

In FIG. 3, the unit cell is 2 (row).
× 3 (columns), that is, photodiodes are 4 (rows) ×
Although the case where three (rows) are arranged is shown, actually more unit cells are arranged.

The horizontal address lines 27-1, 27-2 wired in the horizontal direction from the vertical shift register 26 are connected to the vertical selection transistors 24-1-1, 24-1-2,. 3 is connected to the gate and determines the line from which the detection signal is read.
Similarly, reset lines 28-1 and 28-2 wired in the horizontal direction from the vertical shift register 26 are connected to the gates of the reset transistors 25-1-1, 25-1-2,..., 25-2-3. It is connected.

The amplification transistors 23-1-1, 23-1-2,
…, The source of 23-2-3 is a vertical signal line wired in the vertical direction
The load transistors 30-1, 30-2, and 30-3 are provided at one end of the vertical signal line. Further, the transfer transistors 22-1-1, 22-1-2,.
Transfer lines 31-1, 31-2, 31-3, and 31-4 are connected to the gate of 22-4-3. Further, the vertical signal lines 29-1, 29-2,
The other end of 29-3 has a horizontal selection transistor 33 driven by a selection pulse supplied from the horizontal shift register 32.
The horizontal signal line 34 is connected via -1, 33-2, and 33-3.

The vertical selection transistors 24-1-1 and 24--1-
2, ..., 24-2-3 and reset transistors 25-1-1,25-
1-2, ..., 25-2-3 drain line 35-
1, 35-2 and 35-3 are connected. Normally, a noise canceller circuit (not shown) is provided at the other end of each of the transfer lines 31-1, 31-2,..., 31-4.

As described above, in the conventional solid-state imaging device shown in FIG.
, 21-2-1 and the associated transfer transistor 22-1-
1, 22-2-1 as one unit, and amplifying transistor 23-
1-1, the vertical selection transistor 24-1-1, and the reset transistor 25-1-1 are shared to increase the degree of integration. That is, two photodiodes are provided in one unit cell, five transistors, and a vertical signal line.
9-1 and a drain line 15-1 are provided.

[0010]

The problem of the above-described conventional solid-state imaging device will be described with reference to FIG. FIG.
FIG. 2 is a diagram showing a layout of one unit cell in a conventional solid-state imaging device. In FIG. 4, the same components as those in FIG. 3 are denoted by the same reference numerals, and the symbols in parentheses after the reference symbols mean S: source, D: drain, and G: gate.

[0011] Between the photodiodes 21-1-1 and 21-2-1 forming a photodiode pair, transfer transistors 22-1-1 and 21-1-1 are disposed.
Gates 22-1-1 (G) and 22-2-1 (G) of 22-2-1 are arranged, and between these gates 22-1-1 (G) and 22-2-1 (G). Have common drains 22-1-1 (D) and 22-2-1 (D). Further, the pair of photodiodes (21-1-1, 21-2-1) and the pair of photodiodes (21-1-2, 21-21) adjacent in the horizontal direction are arranged.
-2-2), the amplification transistors 23-1-1 (G) and 23-1
-1 (S), 23-1-1 (D), vertical select transistor 24-1-1 (G)
, 24-1-1 (S), 24-1-1 (D) and reset transistors 25-1-1 (G), 25-1-1 (S), 25-1-1 (D) Have been.

Therefore, the photodiode pair (21-1-
1, 21-2-1) and two horizontally adjacent photodiode pairs (21-1-2, 21-2-2) require two element isolation regions. That is, the pitch Ph between the photodiodes in the horizontal direction is Ph ≒ WPD + 2WISO + WG (3) where WPD is the photodiode width, WISO is the element isolation region width, and WG is the transistor gate width. The pitch Ph is roughly determined. The width WISO of the element isolation region is usually about 1.0 μm,
The necessity of an area twice as large as the element isolation region width is disadvantageous in terms of high integration of elements.

In the layout shown in FIG. 4, the capacitance Ct of the signal charge transferred from the photodiodes 21-1-1 and 21-2-1 which determines the amplification factor is Ct ≒ CFJ + CG + CRS. (S) + C (FJ-G) + C (FJ-RS) (4) where CFJ is the capacitance of the common drain of the transfer transistors 22-1-1 and 22-2-1, and CG is the amplifying transistor 23-1. -1
The gate capacitance of CRS (S) is the reset transistor 25-1
-1 source capacitance, C (FJ-G) is transfer transistor 22-1-
1, amplifying transistor 23-1-1 from common drain of 22-2-1
C (FJ-RS) is the wiring capacitance from the common drain of the transfer transistors 22-1-1 and 22-2-1 to the source of the reset transistor 25-1-1.

When the capacitance Ct increases, the amount of potential fluctuation decreases when the amount of signal charge transferred from the photodiodes 21-1-1 and 21-2-1 is constant. C with only one place inside and large room for optimization
Compared with a solid-state imaging device of the CD type, it is not possible to increase the sensitivity, which is a significant disadvantage.

In view of the above, the present invention has been made in view of the above-mentioned problems, and in a solid-state imaging device using an amplification type MOS image sensor, a unit cell including a photodiode is reduced in size and a signal transferred from the photodiode is reduced. It is an object of the present invention to provide a solid-state imaging device capable of high integration and high sensitivity by reducing the capacity of a charge transfer destination.

[0016]

In order to achieve the above object, a solid-state imaging device according to the present invention is an amplifying type solid-state imaging device comprising unit cells each having a photoelectric conversion unit arranged two-dimensionally in a matrix on a semiconductor substrate. Wherein the photoelectric conversion unit includes a photodiode, a transfer transistor for transferring a detection signal of the photodiode, and an amplification transistor for amplifying the detection signal. A first and a second photoelectric conversion means, which are connected to a drain of a vertical selection transistor and a reset transistor for selecting the first and the second photoelectric conversion means in a row direction, and which are connected to the first and the second photoelectric conversion means; And a drain line commonly used for reading out the detection signal of the photoelectric conversion means.

The solid-state imaging device according to the present invention is a solid-state imaging device using an amplification type MOS image sensor in which unit cells each having a photoelectric conversion unit are arranged two-dimensionally in a matrix on a semiconductor substrate. The photoelectric conversion unit comprises first and second photoelectric conversion means including a photodiode, a transfer transistor for transferring a detection signal of the photodiode, and an amplification transistor for amplifying the detection signal. Vertical selecting means for selecting a row for performing the operation, a plurality of vertical signal lines arranged in a column direction for reading out a detection signal of the photoelectric conversion means corresponding to the row selected by the vertical selecting means, and the vertical selecting means Vertical selection transistor and reset transistor for reading out detection signals of the first and second photoelectric conversion means corresponding to a row selected by A drain line connected to a drain, and a horizontal selection transistor for sequentially reading out the detection signal from the vertical signal line to a horizontal signal line arranged in a row direction, wherein the drain line includes the first and second drain lines. One is provided for each of the two photoelectric conversion units, and is commonly used for reading out the detection signals of the first photoelectric conversion unit and the second photoelectric conversion unit.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a solid-state imaging device using a MOS image sensor according to an embodiment of the present invention.

As shown in FIG. 1, the solid-state image pickup device has photodiodes 1-2 arranged vertically adjacent to each other.
1-1, 1-2-1, transfer transistors 2-1-1, 2--1, which transfer detection signals photoelectrically converted by these photodiodes
2-1; an amplification transistor 3-1-1 for amplifying the detection signal transferred by these transfer transistors; and a vertical selection transistor 4-1-1 for selecting a line for reading the detection signal amplified by the amplification transistor. A reset transistor 5-1 for resetting the charge of the detection signal.
A unit cell consisting of 1s is arranged.

Similarly, as shown in FIG. 1, photodiodes 1-1-2, 1-2-2,..., 1-3-4, 1-4-4, transfer transistors 2-1-2, 2-1-2. 2-2, ..., 2-3-4,2-4-4, amplifying transistor 3-1-2, ..., 3-2-4, vertical selection transistor 4-1-1
2, ..., 4-2-2, and the reset transistor 5-1-2,
, 5-2-4 form a plurality of unit cells, and these unit cells are arranged in a two-dimensional matrix.

In FIG. 1, the unit cell is 2 (row).
× 4 (columns), that is, the photodiode is 4 (rows) ×
Although the case where four (row) cells are arranged is shown, actually more unit cells are arranged.

A horizontal address line 7-1 wired in the horizontal direction from the vertical shift register 6 is connected to the gates of the vertical selection transistors 4-1-1 and 4-1-2. 2 is the vertical select transistors 4-2-1, 4-2-2
Connected to gate 2 The horizontal address line 7-1
, 7-2 determine the line from which the detection signal is read. Similarly, the reset line 8-1 wired in the horizontal direction from the vertical shift register 6 is connected to the reset transistor 5
-1-1, 5-1-2, 5-1-3, 5-1-4
The reset line 8-2 is connected to the reset transistors 5-2-1 and 5-2-1.
Connected to gates 2-2, 5-2-3, 5-2-4.

The sources of the amplifying transistors 3-1-1 and 3-2-1 are connected to a vertical signal line 9-1 wired in the vertical direction, and one end of the vertical signal line 9-1 is connected to a load transistor 10-1.
-1 is provided. Amplification transistors 3-1-2, 3-2-2
The source of the vertical signal line 9-2 is connected to the vertical signal line 9-2.
10-2 is provided. Similarly, the amplification transistors 3-1-3,
The source of 3-2-3 is a vertical signal line 9-3 wired in the vertical direction.
A load transistor 10-3 is provided at one end of the vertical signal line 9-3. Furthermore, the amplification transistor 3-
The sources of 1-4 and 3-2-4 are connected to a vertical signal line 9-4 wired in the vertical direction, and a load transistor 10-4 is provided at one end of the vertical signal line 9-4.

The transfer transistors 2-1-1, 2-1-2, 2-
Transfer lines 11-1 are connected to the gates 1-3 and 2-1-4. Similarly, transfer transistors 2-2-1, 2-2-2, 2-2-3
, 2-2-4 are connected to the transfer line 11-2, and are transferred to the gates of the transfer transistors 2-3-1, 2-3-2, 2-3-3, and 2-3-4. Line 11-3 is connected, and transfer transistor 2-
The transfer lines 11-4 are connected to the gates of 4-1, 2-4-2, 2-4-3 and 2-4-4.
Is connected.

Further, the vertical signal lines 9-1, 9-2, 9-3
, 9-4, a horizontal selection transistor driven by a selection pulse supplied from the horizontal shift register 12.
The horizontal signal lines 14 are connected through 13-1, 13-2, 13-3, and 13-4, respectively.

The vertical selection transistors 4-1-1 and 4-2-1
Drain and reset transistor 5-1-1, 5-1-2
, 5-2-1 and 5-2-2 are connected to a drain line 15-1. Similarly, the vertical selection transistor 4-1-2
, 4-2-2 drain and reset transistor 5-1-3
, 5-1-4, 5-2-3, and 5-2-4 are connected to a drain line 15-2.

Further, the drains of the amplification transistors 3-1-1 and 3-1-2 are connected to the source of the vertical selection transistor 4-1-1. Similarly, the source of the vertical selection transistor 4-1-2 is connected to the source of the vertical selection transistor 4-1-2. The drains of the amplification transistors 3-1-3 and 3-1-4 are connected to the source of the vertical selection transistor 4-2-1. The drains of the amplification transistors 3-2-1 and 3-2-2 are connected to the vertical selection transistor.
The drain of amplifier transistors 3-2-3 and 3-2-4 is connected to the source of 4-2-2. Normally, a noise canceller circuit (not shown) is provided at the other end of each of the transfer lines 11-1, 11-2, 11-3, and 11-4.

Next, the operation of the solid-state imaging device using the MOS image sensor of this embodiment will be described.
When a low level is applied to the gates of the transfer transistors 2-1-1, 2-1-2,..., 2-4-4, and the transfer transistors are turned on, the photodiodes 1-1-1 and 1-1-1 are subjected to photoelectric conversion. -1-2
, ..., 1-4-4, the signal charges accumulated in the diffusion layers are reset to a constant voltage in advance by reset transistors 5-1-1, 5-1-2, ..., 5-2-4. To change the potential. When this potential changes, the vertical selection transistor 4-
If you turn on 1-1, 4-1-2, ..., 4-2-2, the vertical signal line 9-
Load transistors 10- at the ends of 1, 9-2, 9-3, 9-4
A source follower circuit can be made in combination with 1, 10-2, 10-3, and 10-4.

The amplification transistors 3-1-1, 3-1-2,
.., The potential change of the source section of 3-2-4 is determined by sequentially turning on the horizontal selection transistors 13-1, 13-2, 13-3 and 13-4,
4 to sequentially read all signals of the two-dimensional photodiodes 1-1-1, 1-1-2,..., 1-4-4.

The configuration of this solid-state image pickup device is such that the vertically adjacent photodiodes are paired, the right and left adjacent photodiode pairs are combined, and the drain line is not provided between each pixel column, but is provided every other pixel. It is characterized in that it is provided between pixel columns, that is, one drain line is provided for two diode pairs, and the drain line is commonly used by two photodiode pairs.

FIG. 2 is a diagram showing a part of a layout that embodies the circuit configuration shown in FIG. In FIG. 2, FIG.
The same reference numerals are given to those in common with, and the symbols in parentheses after the symbols mean S: source, D: drain, G: gate.

Between the photodiodes 1-1-1 and 1-2-1 forming a photodiode pair, transfer transistors 2-1-1 and
2-2-1 gates 2-1-1 (G) and 2-2-1 (G) are arranged, and between these gates 2-1-1 (G) and 2-2-1 (G). Is the common drain
1 (D) and 2-2-1 (D) are arranged.

Further, the common drains 2-1-1 (D), 2-1-1 (D)
Reset transistors 5-1-1 and 5-1-2 are on the left side of 2-1 (D).
Gates 5-1-1 (G) and 5-1-2 (G) are arranged, and this gate 5-
The reset transistor is on the left side of 1-1 (G) and 5-1-2 (G)
5-1-1 and 5-1-2 drains 5-1-1 (D) and 5-1-2 (D) are arranged.

The photodiode pair (1-1-1,
1-2-1) and a pair of photodiodes (1-1-2, 1-2-2) adjacent in the horizontal direction, an amplifying transistor 3-
1-1 and 3-1-2, and a vertical selection transistor 4-1-1 are arranged.

As described above, the four photodiodes, the transfer transistors 2-1-1 and 2-2-1 and the amplification transistor 3-1-1
1, 3-1-2, vertical selection transistor 4-1-1, reset transistors 5-1-1, 5-1-2, and vertical signal lines 9-1, 9-
2. A unit cell (unit cell) is constituted by the drain line 15-1.

With the above configuration, the drains of the reset transistors 5-1-1 and 5-1-2 and the drain of the vertical selection transistor 4-1-1 connected to the drain line form the left and right pixel columns. Can be shared by the left and right photodiode pairs.

The effect of the present embodiment having such a configuration will be described below. Pitch PH between horizontal photodiodes in the solid-state imaging device according to the present embodiment
Is as follows: PH ≒ WPD + 1.5WISO + 0.5WG (1) Here, WPD is the photodiode width, WISO is the element isolation region width, and WG is the transistor gate width.
Normally, WISO and WG are approximately 1 μm, so that the pitch PH can be reduced by about 1.0 μm in the horizontal direction as compared with the pitch Ph between the photodiodes obtained by the above equation (3). 1/4 "optical system 330,000 pixel VGA
In a compatible camera, the pitch PH between the photodiodes in the horizontal direction is usually 5.6 μm, so that the effect of this reduction is great.

The capacitance CT to be charged of the signal charge transferred from the photodiode is as follows: CT ≒ CFJ + CG + C (FJ-G) (2) Here, CFJ is the transfer transistor 2-1-1, 2-2-2
1, the common drain capacitance, CG is the amplification transistor
The gate capacitance of 1 and C (FJ-G) are the transfer transistor 2-1-1
, 2-2-1 from the common drain of the amplification transistor 3-1-1
Is the wiring capacitance up to the gate. Therefore, this capacitance CT can be reduced as compared with the capacitance Ct obtained by the above-mentioned equation (4), and higher sensitivity can be achieved.

Normally, CFJ ≒ CGGCRS (S) = A, C (FJ-
G) ≒ C (FJ-RS) = B and A >> B or A ≒ B
Therefore, the capacity can be reduced by about 30%, and the same high sensitivity can be achieved.

As described above, according to this embodiment, by providing one drain line for two pixel columns, it is possible to reduce the unit cell size and achieve high integration. Further, the number of element isolations in a unit cell composed of two pixel columns is three, which is 1.5 pixels per pixel column, which is 75% smaller than the conventional two. Further, the capacity of the transfer destination of the signal charge from the photodiode can be reduced, and high sensitivity can be realized.

Although the above embodiment has been described based on an example in which photodiodes adjacent to each other are paired up and down, the present invention can be applied to a structure in which photodiodes are not paired. Can be.

[0042]

As described above, according to the present invention, in a solid-state imaging device using an amplifying MOS image sensor, a unit cell including a photodiode is reduced in size to transfer a signal charge transferred from the photodiode. By reducing the above capacitance, a solid-state imaging device capable of high integration and high sensitivity can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a layout that embodies the configuration shown in FIG. 1;

FIG. 3 is a circuit diagram illustrating a configuration of a conventional solid-state imaging device.

FIG. 4 is a diagram showing a layout that embodies the configuration shown in FIG. 3;

[Explanation of symbols]

1-1-1, 1-2-1, 1-1-2, 1-2-2,…, 1-3-4, 1-4-4
... Photodiodes 2-1-1, 2-2-1, 2-1-2, 2-2-2, ..., 2-3-4, 2-4-4
… Transfer transistors 3-1-1, 3-1-2,…, 3-2-4… Amplification transistors 4-1-1, 4-1-2,…, 4-2-2… Vertical selection transistors 5- 1-1, 5-1-2, ..., 5-2-4 ... reset transistor 6 ... vertical shift register 7-1, 7-2 ... horizontal address line 8-1, 8-2 ... reset line 9-1, 9-2, 9-3, 9-4 ... vertical signal lines 10-1, 10-2, 10-3, 10-4 ... load transistors 11-1, 11-2, 11-3, 11-4 ... transfer Line 12: Horizontal shift register 13-1, 13-2, 13-3, 13-4: Horizontal selection transistor 14: Horizontal signal line 15-1, 15-2: Drain line

Claims (3)

[Claims] 1. A solid-state imaging device using an amplification type MOS image sensor in which unit cells each having a photoelectric conversion unit are arranged in a matrix two-dimensionally on a semiconductor substrate, wherein the photoelectric conversion unit includes a photodiode and A transfer transistor for transferring the detection signal of the photodiode,
A first and second photoelectric conversion means including an amplifying transistor for amplifying the detection signal, and a drain for a vertical selection transistor and a reset transistor for selecting the first and second photoelectric conversion means in a row direction. A solid-state imaging device, comprising: a drain line that is connected and commonly used to read out the detection signals of the first photoelectric conversion unit and the second photoelectric conversion unit. 2. A solid-state imaging device using an amplifying MOS image sensor in which unit cells each having a photoelectric conversion unit are arranged in a two-dimensional matrix on a semiconductor substrate, wherein the photoelectric conversion unit includes a photodiode and A transfer transistor for transferring the detection signal of the photodiode,
First and second photoelectric conversion means including an amplifying transistor for amplifying the detection signal, a vertical selection means for selecting a row to be read, and the photoelectric conversion means corresponding to the row selected by the vertical selection means. A plurality of vertical signal lines arranged in a column direction for reading a detection signal of the conversion means, and a detection signal of the first and second photoelectric conversion means corresponding to a row selected by the vertical selection means are read. A drain line connected to the drains of the vertical selection transistor and the reset transistor, and a horizontal selection transistor for sequentially reading the detection signal from the vertical signal line to a horizontal signal line arranged in a row direction, One drain line is provided for each of the first and second photoelectric conversion units, and is provided in front of the first and second photoelectric conversion units. A solid-state imaging device characterized in that it is utilized in common in order to read the detection signal. 3. The first and second photoelectric conversion means each include two sets of photodiodes, a transfer transistor for transferring a detection signal of the photodiode, and an amplification transistor for amplifying the detection signal. The solid-state imaging device according to claim 1, wherein: