CN217470115U - Pixel array and image sensor - Google Patents

Abstract

The utility model relates to a pixel array and image sensor, through six pixel sharing structures and its specific layout mode, can effectively improve the occupation ratio of photodiode area in the pixel, thereby promote the photoelectric conversion quantum efficiency of pixel, and first source is followed the intermediate position that the transistor is located two parts of first floating diffusion active area, the second source is followed the intermediate position that the transistor is located two parts of second floating diffusion active area, so that first, second floating diffusion active area respectively with first, the second source is followed the metal connecting wire of transistor grid shorter, metal relevant part parasitic capacitance is lower, thereby effectively reduce the parasitic capacitance of floating diffusion active area in the pixel, improve the photoelectric conversion gain of pixel, the image quality that promotes image sensor collection.

Description

Pixel array and image sensor

Technical Field

The present application relates to the field of image sensor technology, and in particular, to a pixel array and an image sensor.

Background

Image sensors are widely used in a variety of electronic devices to capture and identify image information of a person or scene, such as video surveillance systems, smart phones, digital cameras, medical devices, drones, intelligent AI, and face recognition applications. Especially, the rapid development of the technology for manufacturing CMOS (complementary metal oxide semiconductor) image sensors has made higher demands on the output image quality of the image sensors.

An image sensor is a semiconductor-based sensor that generates an electrical signal in response to light, and as an important component of a digital camera, it can convert an incident light signal into an electric charge signal, then convert the electric charge signal into a voltage or current signal, and finally output the converted electrical signal. The image sensor comprises a photosensitive pixel array, wherein the photosensitive pixel array is used for collecting optical signal information of the image array so as to convert the optical signal information into image array electrical signal data for a terminal to use. In an image sensor pixel array, transistor device layouts may be different between pixels, for example, pixels laid out in a sharing structure manner, a plurality of pixels share a floating diffusion active region, a source follower transistor, a reset transistor, and the like, and specific types of the existing pixel layouts include two-pixel sharing, four-pixel sharing, and even eight-pixel sharing. The pixels are distributed in a sharing structure mode, so that the number of transistors in the pixels can be reduced, the area occupancy rate of the photodiodes in the pixels is increased, and the light sensing efficiency of the pixels is improved.

In the image sensor pixel array adopting the shared structure, due to different specific types, the device layout structures of adjacent pixels of the pixel array in the vertical or horizontal or diagonal direction are different. The area occupancy and other electrical characteristics corresponding to different sharing types and different layout structures are also different.

The foregoing description is provided for general background information and is not admitted to be prior art.

SUMMERY OF THE UTILITY MODEL

In view of this, an object of the present invention is to provide a pixel array and an image sensor, which can effectively increase the occupancy rate of the photodiode area in the pixel, thereby increasing the photoelectric conversion quantum efficiency of the pixel, and can also effectively reduce the parasitic capacitance in the pixel, increase the photoelectric conversion gain of the pixel, increase the image quality acquired by the image sensor, and increase the product competitiveness.

In order to achieve the above object, embodiments of the present application provide a pixel array, optionally, the pixel array includes a plurality of pixel groups arranged in an array, each of the pixel groups includes six pixels, the six pixels include six photosensitive pixel units, and a first sharing structure and a second sharing structure connected, each of the photosensitive pixel units includes a photodiode and a transfer transistor connected to each other, wherein,

first, second and third of the six light-sensitive pixel units share the first shared structure; a fourth, fifth and sixth of the six light-sensitive pixel units share the second shared structure; the first, fourth and fifth photosensitive pixel units are positioned on the mth row of the pixel array and are sequentially arranged from left to right, and the second, third and sixth photosensitive pixel units are positioned on the m +1 th row of the pixel array and are sequentially arranged from left to right; the grid electrode of the transmission transistor of the third photosensitive pixel unit is connected with the grid electrode of the transmission transistor of the fourth photosensitive pixel unit;

the first sharing structure comprises a first floating diffusion active area, and a first reset transistor and a first source follower transistor which are connected, wherein the first floating diffusion active area comprises a first part and a second part which are connected, the first source follower transistor is positioned at the vertex angle junction of the photodiodes of the first, second, third and fourth photosensitive pixel units, the first reset transistor is positioned between the photodiodes of the first and second photosensitive pixel units, and the first part and the second part of the first floating diffusion active area are respectively positioned at two sides of the first source follower transistor along the row direction; and/or the second sharing structure comprises a second floating diffusion active region, a second reset transistor and a second source following transistor which are connected, the second floating diffusion active region comprises a first part and a second part which are connected, the second source following transistor is positioned at the corner junction of the photodiodes of the third, fourth, fifth and sixth photosensitive pixel units, the second reset transistor is positioned between the photodiodes of the fifth and sixth photosensitive pixel units, and the first part and the second part of the second floating diffusion active region are respectively positioned at two sides of the second source following transistor along the row direction.

Optionally, the six photosensitive pixel units are in a two-row three-column rectangular arrangement structure; the first photosensitive pixel units and the second photosensitive pixel units are arranged in a mirror image mode along the row direction, and the second photosensitive pixel units and the third photosensitive pixel units are arranged in a mirror image mode along the column direction; the fourth photosensitive pixel unit and the fifth photosensitive pixel unit are arranged in a mirror image mode along the column direction, and the fifth photosensitive pixel unit and the sixth photosensitive pixel unit are arranged in a mirror image mode along the row direction.

Optionally, the transfer transistor in the third photosensitive pixel unit is located at a corner of the corresponding photodiode, the transfer transistor in the fourth photosensitive pixel unit is located at a corner of the corresponding photodiode, and the transfer transistor in the third photosensitive pixel unit and the transfer transistor in the fourth photosensitive pixel unit are in central symmetry with a central point of the corresponding pixel group.

Optionally, the transfer transistors in the first, second, and third photosensitive pixel units are respectively located at a lower right corner, an upper right corner, and an upper left corner of the corresponding photodiode; the transmission transistors in the fourth, fifth and sixth photosensitive pixel units are respectively located at the lower right corner, the lower left corner and the upper left corner of the corresponding photodiode.

Optionally, a source of the first reset transistor, a gate of the first source follower transistor, and a drain of the transfer transistor of the corresponding photosensitive pixel cell are respectively connected to the first floating diffusion active region, a drain of the first reset transistor and a drain of the first source follower transistor are connected to the corresponding power signal line, and a source of the first source follower transistor is connected to the corresponding signal output line; and/or the source of the second reset transistor, the gate of the second source follower transistor and the drain of the transfer transistor of the corresponding photosensitive pixel cell are connected to the second floating diffusion active region, respectively, the drain of the second reset transistor and the drain of the second source follower transistor are connected to the corresponding power signal lines, and the source of the second source follower transistor is connected to the corresponding signal output lines.

Optionally, the first source follower transistor is disposed at a middle position of a connection line of the two portions of the first floating diffusion active region, and/or the connection line of the first reset transistor and the first floating diffusion active region is disposed along a row direction; and/or the second source follower transistor is arranged at the middle position of the connecting line of the two parts of the second floating diffusion active region, and/or the connecting line of the second reset transistor and the second floating diffusion active region is arranged along the row direction.

Optionally, the pixel array further includes a plurality of first metal routing groups, each first metal routing group corresponds to one row of the pixel groups, one row of the pixel groups corresponds to two rows of pixels of the pixel array, and each first metal routing group includes: the first metal routing, the second metal routing, the third metal routing and the fourth metal routing; wherein the content of the first and second substances,

the first metal wire is used for providing transmission control signals for the transmission transistors of the first and fifth photosensitive pixel units in the pixel group of the corresponding line;

the second metal routing is used for providing transmission control signals for the transmission transistors of the third and fourth photosensitive pixel units in the pixel group of the corresponding row;

the third metal wire is used for providing transmission control signals for the transmission transistors of the second and sixth photosensitive pixel units in the pixel group of the corresponding line;

the fourth metal routing is used for providing reset signals for the first reset transistor and the second reset transistor in the pixel group of the corresponding row.

Optionally, the first sharing structure further includes a first pixel selection transistor, a drain of the first pixel selection transistor is connected to a source of the first source follower transistor, and a source of the first pixel selection transistor is connected to a corresponding signal output line; and/or the second sharing structure further comprises a second pixel selection transistor, the drain of the second pixel selection transistor is connected with the source of the second source follower transistor, and the source of the second pixel selection transistor is connected with a corresponding signal output line.

Optionally, the first pixel selection transistor is located at one side of the first source follower transistor in a column direction; and/or the second pixel selection transistor is located on one side of the second source follower transistor in the column direction.

Optionally, the first metal routing group further includes a fifth metal routing for providing a pixel selection signal for the first pixel selection transistor and/or the second pixel selection transistor in the pixel group of the corresponding row.

Optionally, the pixel array further includes a plurality of sixth metal traces for outputting signals; each column of pixel group corresponds to two sixth metal wires, and the two sixth metal wires corresponding to each column of pixel group are respectively connected with the source electrodes of the first source follower transistor and the second source follower transistor in the corresponding column of pixel group.

Optionally, the pixel array further includes a plurality of seventh metal traces extending in the column direction, and configured to provide a power signal; and each two rows of pixel groups correspond to seven seventh metal wires, and two sides of each row of pixels are respectively and correspondingly provided with one seventh metal wire.

Optionally, the gate of the transfer transistor of the third photosensitive pixel unit is connected to the gate of the transfer transistor of the fourth photosensitive pixel unit through gate polysilicon; the first and second portions of the first floating diffusion active region are connected by a metal line, and the first and second portions of the second floating diffusion active region are connected by a metal line.

Based on the same inventive concept, the present application provides an image sensor including the pixel array according to any one of the above embodiments.

Based on the same inventive concept, the present application further provides a control method of an image sensor, which is applied to the image sensor described in any of the above embodiments, optionally, pixels corresponding to a third photosensitive pixel unit and a fourth photosensitive pixel unit in the image sensor are all first-type pixels, and pixels corresponding to other photosensitive pixel units in the image sensor are all second-type pixels; the method comprises the following steps of acquiring image information of each row of pixels in a rolling exposure mode within a frame time sequence of the image sensor, and specifically comprises the following steps:

carrying out first reset operation on the second type of pixels in the mth row through a reset metal wiring line which corresponds to the pixels in the mth row and the (m + 1) th row in common so as to clear charges in the photodiodes of the second type of pixels in the mth row;

exposing the second type of pixels in the mth row;

carrying out first reset operation on first-class pixels in an mth row and an m +1 th row through reset metal routing wires which are commonly corresponding to the mth row and the m +1 th row of pixels so as to clear charges in photodiodes of the first-class pixels in the mth row and the m +1 th row;

and exposing the first type pixels in the mth row and the m +1 th row.

Carrying out first reset operation on the second type of pixels in the m +1 th row through a reset metal wiring line which corresponds to the m +1 th row of pixels in common so as to clear charges in the photodiodes of the second type of pixels in the m +1 th row;

exposing the second type of pixels in the m +1 th row;

carrying out second reset operation on the second type of pixels in the mth row through a reset metal wiring line which corresponds to the pixels in the mth row and the (m + 1) th row in common so as to eliminate the charges in the first floating diffusion active region in the first sharing structure and the charges in the second floating diffusion active region in the second sharing structure;

reading reset signals of the second type of pixels in the mth row;

ending the exposure of the second type of pixels in the mth row and transferring the charge in the photodiodes of the second type of pixels in the mth row to the first and second floating diffusion active regions;

reading initial photoelectric signals of pixels of a second type in the mth row;

carrying out second reset operation on the first type of pixels in the mth row and the (m + 1) th row through reset metal routing wires which are corresponding to the mth row and the (m + 1) th row of pixels together so as to eliminate the charges in the first floating diffusion active region and the charges in the second floating diffusion active region;

reading reset signals of first type pixels in the mth row and the m +1 th row;

ending the exposure of the first type pixels in the m-th row and the m + 1-th row and transferring the charges in the photodiodes of the first type pixels in the m-th row and the m + 1-th row to the first floating diffusion active region and the second floating diffusion active region;

reading initial photoelectric signals of first pixels in the mth row and the m +1 th row;

and carrying out second reset operation on the second type of pixels in the m +1 th row through the reset metal wiring lines corresponding to the m-th row and the m +1 th row of pixels together so as to clear the charges in the first floating diffusion active region and the second floating diffusion active region.

Reading reset signals of the second type of pixels in the (m + 1) th row;

ending the exposure of the second type pixels in the m +1 th row and transferring the charges in the photodiodes of the second type pixels in the m +1 th row to the first floating diffusion active region and the second floating diffusion active region;

and reading to obtain an initial photoelectric signal of the second type of pixels in the m +1 th row.

Optionally, an expression of the photoelectric signal collected by the second type of pixel in the mth row is: siga (m, y) ═ ma _ r (y) -ma _ s (y), wherein Siga (m, y) is a photoelectric signal collected by the second type of pixels in the mth row, ma _ r (y) is a reset signal read out from the second type of pixels in the mth row, ma _ s (y) is an initial photoelectric signal read out from the second type of pixels in the mth row, and y is the column position where the pixels are located;

the expression of the photoelectric signals collected by the first type of pixels in the mth row and the m +1 th row is as follows: sigb (m, y) & < m +1> b _ r (y) -mb & < m +1> b _ r (y) is a photoelectric signal collected from the first type pixels in the m-th and m + 1-th rows, mb & < m +1> b _ r (y) is a reset signal read out from the first type pixels in the m-th and m + 1-th rows, mb & < m +1> b _ s (y) is an initial photoelectric signal read out from the first type pixels in the m-th and m + 1-th rows, and y is a column position where the pixels are located;

the expression of the photoelectric signal collected by the second type of pixels in the (m + 1) th row is as follows: siga (m +1, y) < m +1> a _ r (y) < m +1> a _ s (y), where Siga (m +1, y) is the photoelectric signal collected by the second type of pixel in the m +1 th row, < m +1> a _ r (y) is the reset signal read out from the second type of pixel in the m +1 th row, < m +1> a _ s (y) is the initial photoelectric signal read out from the second type of pixel in the m +1 th row, and y is the column position where the pixel is located.

To sum up, the pixel array provided in the embodiment of the present application, through the six-pixel sharing structure and the specific layout thereof, can effectively improve the occupancy of the photodiode area in the pixel, thereby improving the photoelectric conversion quantum efficiency of the pixel, and the first source follower transistor is located in the middle of the two portions of the first floating diffusion active region, and the second source follower transistor is located in the middle of the two portions of the second floating diffusion active region, so that the metal connection lines of the first and second floating diffusion active regions with the gates of the first and second source follower transistors are shorter, and the parasitic capacitance of the metal-related portion is lower, thereby effectively reducing the parasitic capacitance of the floating diffusion active region in the pixel, improving the photoelectric conversion gain of the pixel, and improving the image quality acquired by the image sensor.

The image sensor and the control method of the image sensor belong to the same inventive concept as the pixel array provided by the application, and therefore have the same beneficial effects.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a circuit diagram of a pixel group in a pixel array according to an embodiment of the present disclosure.

Fig. 2 is a layout schematic diagram of a pixel group in a pixel array according to an embodiment of the present application.

Fig. 3 is an array layout schematic diagram of a pixel array according to an embodiment of the present application.

Fig. 4 is a schematic control timing diagram of an image sensor according to an embodiment of the present disclosure.

The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings. With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the concepts of the application by those skilled in the art with reference to specific embodiments.

Detailed Description

In order to make those skilled in the art better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the described embodiments are merely exemplary of some, and not all, of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without inventive step, shall fall within the scope of protection of the present application.

It should be noted that the terms "first," "second," and the like in the description, the claims, and the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in other sequences than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As used herein, an element, port, component or section "connected" to another element, port, component or section may be understood as a direct electrical connection, or may be understood as an indirect electrical connection with an intervening element. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

First, in the present patent document, the X direction in the drawing is a row direction or a horizontal direction, and the Y direction is a column direction or a vertical direction. Although some embodiments of the disclosed technology show the X and Y directions as row and column directions, respectively. It should be noted that the disclosed technology is not limited to this, that is, the X direction may be a column direction, and the Y direction may be a row direction, which are defined differently only by the row and column, and both are within the scope of the present application, for example, one pixel group may be distributed in two rows and three columns in fig. 1, or may be distributed in three rows and two columns.

The following description mainly takes the first row and the first column of the pixel group, i.e. the first to the second row of the pixels, and the first to the third column of the pixels in the pixel array as an example.

Fig. 1 is a circuit diagram of a pixel group in a pixel array according to an embodiment of the present disclosure. Fig. 2 is a layout schematic diagram of a pixel group in a pixel array according to an embodiment of the present application. As shown in fig. 1 and 2, the pixel array includes pixel groups (only one is shown in fig. 1) arranged in an array, each of the pixel groups including six pixels each including six photosensitive pixel units each including a photodiode and a transfer transistor connected to each other, and first and second sharing structures connected to each other.

Specifically, the first photosensitive pixel cell includes a corresponding photodiode 101 and a corresponding transfer transistor 107, the second photosensitive pixel cell includes a corresponding photodiode 102 and a corresponding transfer transistor 108, the third photosensitive pixel cell includes a corresponding photodiode 103 and a corresponding transfer transistor 109, the fourth photosensitive pixel cell includes a corresponding photodiode 104 and a corresponding transfer transistor 110, the fifth photosensitive pixel cell includes a corresponding photodiode 105 and a corresponding transfer transistor 111, and the sixth photosensitive pixel cell includes a corresponding photodiode 106 and a corresponding transfer transistor 112.

The first, second and third photosensitive pixel units in the six photosensitive pixel units share the first sharing structure. The fourth, fifth and sixth of the six photosensitive pixel cells share a second shared structure. The first, fourth and fifth photosensitive pixel units are positioned on the mth row of the pixel array and are sequentially arranged from left to right, and the second, third and sixth photosensitive pixel units are positioned on the m +1 th row of the pixel array and are sequentially arranged from left to right, wherein m is a natural number greater than 0. The gate of the transfer transistor 109 of the third photosensitive pixel unit is connected to the gate of the transfer transistor 110 of the fourth photosensitive pixel unit.

As shown in fig. 2, the first shared structure includes a first floating diffusion active region FD1 and a first source follower transistor 113 and a first reset transistor 115 connected to each other, the first floating diffusion active region FD1 includes a first portion and a second portion connected to each other, the first source follower transistor 113 is located at a corner boundary of photodiodes (101, 102, 103, and 104) of first, second, third, and fourth photosensitive pixel units, the first reset transistor 115 is located between the photodiodes (101, 102) of the first and second photosensitive pixel units, and the first portion and the second portion of the first floating diffusion active region FD1 are located at two sides of the first source follower transistor 113 along a row direction, respectively; and/or the second shared structure includes a second floating diffusion active region FD2 and a second source follower transistor 114 and a second reset transistor 116 connected, the second floating diffusion active region FD2 includes a first portion and a second portion connected, the second source follower transistor 114 is located at a photodiode vertex angle (103, 104, 105, 106) boundary of the third, fourth, fifth, and sixth photosensitive pixel cells, the second reset transistor 116 is located between photodiodes (105, 106) of the fifth and sixth photosensitive pixel cells, and the first portion and the second portion of the second floating diffusion active region FD2 are respectively located at both sides of the second source follower transistor 114 in the row direction.

The pixel array provided by the embodiment of the application can effectively improve the occupancy of the area of a photodiode in a pixel through a six-pixel sharing structure and a specific layout mode thereof, thereby improving the photoelectric conversion quantum efficiency of the pixel, a first source following transistor is positioned in the middle of two parts of a first floating diffusion active area, a second source following transistor is positioned in the middle of two parts of a second floating diffusion active area, so that the first floating diffusion active area and the second floating diffusion active area are respectively shorter than metal connecting wires of a grid electrode of the first source following transistor and a grid electrode of the second source following transistor, and the parasitic capacitance of the metal related part is lower, thereby effectively reducing the parasitic capacitance of the floating diffusion active area in the pixel, improving the photoelectric conversion gain of the pixel and improving the image quality acquired by an image sensor.

It should be noted that, in the following description, each row of pixel group corresponds to two rows of pixels, and each column of pixel group corresponds to three columns of pixels.

In one embodiment, as shown in fig. 2, the six photosensitive pixel units are arranged in a rectangular structure with two rows and three columns. The first photosensitive pixel unit and the second photosensitive pixel unit are arranged in a mirror image mode along the row direction, and the second photosensitive pixel unit and the third photosensitive pixel unit are arranged in a mirror image mode along the column direction; the fourth light-sensitive pixel unit and the fifth light-sensitive pixel unit are arranged in a mirror image mode along the column direction, and the fifth light-sensitive pixel unit and the sixth light-sensitive pixel unit are arranged in a mirror image mode along the row direction.

Note that, for example, the first photosensitive pixel unit and the second photosensitive pixel unit are arranged in a mirror image in the row direction, which means that each structure (including a photodiode and a transfer transistor) in the first photosensitive pixel unit and each structure in the second photosensitive pixel unit are arranged in a mirror image in the row direction.

In one embodiment, the transfer transistors in the third photosensitive pixel unit are located at the corners of the corresponding photodiodes, the transfer transistors in the fourth photosensitive pixel unit are located at the corners of the corresponding photodiodes, and the transfer transistors in the third photosensitive pixel unit and the transfer transistors in the fourth photosensitive pixel unit are in central symmetry with respect to the center point of the corresponding pixel group.

Specifically, as shown in fig. 2, fig. 2 shows an embodiment in which the transfer transistor 109 in the third photosensitive pixel unit and the transfer transistor 110 in the fourth photosensitive pixel unit are centrosymmetric with respect to the center point of the corresponding pixel group, and in other embodiments, for example, the transfer transistor 109 in the third photosensitive pixel unit may be disposed at the upper right corner of the photodiode 104 of the third photosensitive pixel unit, and the transfer transistor 110 in the fourth photosensitive pixel unit may be disposed at the lower left corner of the photodiode 104 of the fourth photosensitive pixel unit.

In one embodiment, as shown in fig. 2, the transfer transistors (107, 108, and 109) in the first, second, and third photosensitive pixel units are respectively located at the lower right corner, the upper right corner, and the upper left corner of the corresponding photodiode. The transfer transistors (110, 111, and 112) in the fourth, fifth, and sixth photosensitive pixel cells are located at the lower right corner, lower left corner, and upper left corner of the corresponding photodiode, respectively.

As shown in fig. 1, in one embodiment, the gate of the first source follower transistor 113, the source of the first reset transistor 115, and the drain of the transfer transistor of the corresponding photosensitive pixel cell are connected to the first floating diffusion active region FD1, respectively, the drain of the first source follower transistor 113 and the drain of the first reset transistor 115 are connected to the corresponding power signal line, and the source of the first source follower transistor 113 is connected to the corresponding signal output line; and/or the source of the second reset transistor 116, the gate of the second source follower transistor 114, and the drain of the transfer transistor of the corresponding photosensitive pixel cell are connected to the second floating diffusion active region FD2, respectively, the drain of the second reset transistor 116 and the drain of the second source follower transistor 114 are connected to the corresponding power signal lines, and the source of the second source follower transistor 114 is connected to the corresponding signal output line.

Specifically, one end of each of the photodiodes (101, 102, and 103) in the first, second, and third photosensitive pixel units is grounded, the other end is connected to the source of the corresponding transfer transistor (107, 108, and 109), the drains of the transfer transistors (107, 108, and 109), the gate of the first source follower transistor 113, and the source of the first reset transistor 115 in the first, second, and third photosensitive pixel units are connected to the first floating diffusion active region FD1, respectively, the drain of the first source follower transistor 113 and the drain of the first reset transistor 115 are connected to the corresponding power signal line, and the source of the first source follower transistor 113 is connected to the corresponding signal output line. And/or one end of each of the photodiodes (104, 105 and 106) in the fourth, fifth and sixth photosensitive pixel units is grounded, the other end is connected to the source of the corresponding transfer transistor (110, 111 and 112), the drains of the transfer transistors (110, 111 and 112), the gates of the second source follower transistors 114 and the sources of the second reset transistors 116 in the fourth, fifth and sixth photosensitive pixel units are respectively connected to the second floating diffusion active region FD2, the drains of the second source follower transistors 114 and the drains of the second reset transistors 116 are connected to the corresponding power signal lines, and the sources of the second source follower transistors 114 are connected to the corresponding signal output lines.

As shown in fig. 2, in an embodiment, the first source follower transistor 113 is disposed at a middle position of a connection line of two portions of the first floating diffusion active region FD1, and/or a connection line of the first reset transistor 115 and the first floating diffusion active region FD1 is disposed in a row direction; and/or the second source follower transistor 114 is disposed at an intermediate position of the connection line of the two portions of the second floating diffusion active region FD2, and/or the connection line of the second reset transistor 116 and the second floating diffusion active region FD2 is disposed in the row direction.

As shown in fig. 2, in an embodiment, the pixel array further includes a plurality of first metal routing groups, each of the first metal routing groups corresponds to one row of pixel groups, one row of pixel groups corresponds to two rows of pixels of the pixel array, and each of the first metal routing groups includes a first metal routing TXa1, a second metal routing TXb, a third metal routing TXa2, and a fourth metal routing RST. The first metal trace Txa1 is used for providing transmission control signals for the transmission transistors (107, 111) of the first and fifth light-sensitive pixel units in the pixel group of the corresponding row. The second metal trace TXb is used for providing transmission control signals for the transmission transistors (109, 110) of the third and fourth light-sensitive pixel units in the pixel groups of the corresponding row. The third metal trace Txa2 is used for providing transmission control signals for the transmission transistors (108, 112) of the second and sixth light-sensitive pixel units in the pixel group of the corresponding row. The fourth metal trace RST is used for providing reset signals for the first reset transistor 115 and the second reset transistor 116 in the pixel group of the corresponding row.

Specifically, each metal line serves as a timing control line for controlling the gate potential of each corresponding device in the pixel group to control the state of each transistor.

As shown in fig. 1, in one embodiment, the first sharing structure further includes a first pixel selection transistor 117, a drain of the first pixel selection transistor 117 is connected to a source of the first source follower transistor 113, and a source of the first pixel selection transistor 117 is connected to a corresponding signal output line; and/or the second shared structure further comprises a second pixel selection transistor 118, the drain of the second pixel selection transistor 118 being connected to the source of the second source follower transistor 114, the source of the second pixel selection transistor 118 being connected to a corresponding signal output line.

As shown in fig. 2, in one embodiment, the first pixel selection transistor 117 is located on one side of the first source follower transistor 113 in the column direction; and/or the second pixel selection transistor 118 is located on one side of the second source follower transistor 114 in the column direction.

As shown in fig. 2, in an embodiment, the first metal routing group further includes a fifth metal routing RS for providing a pixel selection signal to the first pixel selection transistor 117 and/or the second pixel selection transistor 118 in the pixel group of the corresponding row.

In an embodiment, the first metal trace Txa1, the second metal trace TXb, the third metal trace Txa2, the fourth metal trace RST and the fifth metal trace RS are disposed on a same metal layer.

It should be noted that, only the first row of pixel groups, i.e., the first row to the second row of pixels, of the pixel array is taken as an example for description, that is, each row of metal traces in the first metal trace group corresponding to each row of pixel groups are located in the same metal layer.

As shown in fig. 2, in an embodiment, the pixel array further includes a plurality of sixth metal traces (only two sixth metal traces Sa <1> & Sb <2> and Sa <3> & Sb <2> corresponding to one column of pixel groups are shown in the figure) for reading signals. Each column of pixel group corresponds to two sixth metal wires, and the two sixth metal wires corresponding to each column of pixel group are respectively connected with the sources of the first source follower transistor 113 and the second source follower transistor 114 in the corresponding column of pixel group.

Specifically, the connection between the two sixth metal wirings corresponding to each column of pixel group and the source of the first source follower transistor 113 and the source of the second source follower transistor 114 in the corresponding column of pixel group respectively includes direct connection and indirect connection, and for example, when a pixel selection transistor is provided, the sixth metal wirings are connected with the corresponding source follower transistors through the corresponding pixel selection transistors.

As shown in fig. 2, in an embodiment, the pixel array further includes a plurality of seventh metal traces VDD extending along the column direction for providing power signals. Wherein, every two rows of pixel groups correspond to seven seventh metal routing wires, and two sides of every row of pixels are respectively and correspondingly provided with one seventh metal routing wire.

Optionally, the sixth metal trace (Sa <1> & Sb <2> and Sa <3> & Sb <2>) and the seventh metal trace VDD are disposed on the same metal layer, and are different from the first metal trace Txa1, the second metal trace TXb, the third metal trace Txa2, the fourth metal trace RST, the fifth metal trace RS1, the sixth metal trace RS2, and the eighth metal trace VDD 1.

In one embodiment, the gate of the transfer transistor 109 of the third photosensitive pixel cell is connected to the gate of the transfer transistor 110 of the fourth photosensitive pixel cell by gate polysilicon; and/or the first portion and the second portion of the first floating diffusion active region are connected by a metal line and the first portion and the second portion of the second floating diffusion active region are connected by a metal line.

For a more detailed description of the pixel array of the present application, please refer to fig. 3. Fig. 3 is an array layout schematic diagram of a pixel array according to an embodiment of the present application. As shown in fig. 3, fig. 3 shows a 6 × 6 pixel array portion in a pixel array, where pixel rows are labeled m, m +1, m +2, m +3, m +4, m +5, and pixel columns are labeled n, n +1, n +2, n +3, n +4, n +5, where m is a natural number greater than 0 and n is a natural number greater than 0. For convenience of description, the pixels corresponding to the third photosensitive pixel unit and the fourth photosensitive pixel unit in the pixel array are all the first type pixels or b-type pixels, and the pixels corresponding to the other photosensitive pixel units are all the second type pixels or a-type pixels.

The gates of the transmission transistors of the second type pixels in the x-th row are connected with metal tracks TXA < x > (x is m, m +1, m +2, m +3, m +4, m +5), and the gates of the transmission transistors of the first type pixels in the x-th row and the x +1 row are connected with metal tracks TXB < x, x +1> (x is m, m +2, m + 4). The metal wires connected with the grid of the corresponding reset transistor are marked as RST < m, m +1>, RST < m +2, m +3>, RST < m +4, m +5 >; the metal wiring marks connected with the grid electrode of the corresponding pixel selection transistor are RS < m, m +1>, RS < m +2, m +3>, RS < m +4 and m +5 >; the power signal lines are labeled Vdd (including Vdd1 and Vdd2 as described in the above embodiments). In the pixel array shown in fig. 3, the column signal output lines are respectively labeled from left to right as Sa < n > & Sb < n +1>, Sa < n +2> & Sb < n +1>, Sa < n +3> & Sb < n +4>, Sa < n +5> & Sb < n +4>, where Sa < y > represents the signal of the second type of pixel outputting the y-th column of pixels through the column signal output line, and Sb < y > represents the signal of the first type of pixel outputting the y-th column of pixels through the column signal output line.

It should be noted that the pixel group in the pixel array of the image sensor of the present application may be a structure formed by performing the following operations on any one of the pixel groups: the horizontal center line of the pixel group is turned over by 180 degrees up and down, the vertical center line of the pixel group is turned over by 180 degrees left and right, the center of the pixel group is rotated by 180 degrees clockwise, and the center of the pixel group is rotated by 180 degrees anticlockwise.

Therefore, the pixel array provided by the embodiment of the application can effectively improve the occupancy rate of the area of the photodiode in the pixel through the six-pixel sharing structure and the specific layout mode thereof, so as to improve the photoelectric conversion quantum efficiency of the pixel, the first source follower transistor is located in the middle of the two parts of the first floating diffusion active region, and the second source follower transistor is located in the middle of the two parts of the second floating diffusion active region, so that the metal connecting lines of the first floating diffusion active region and the second floating diffusion active region with the gates of the first source follower transistor and the second source follower transistor are shorter, and the parasitic capacitance of the metal-related part is lower, so that the parasitic capacitance of the floating diffusion active region in the pixel is effectively reduced, the photoelectric conversion gain of the pixel is improved, and the image quality acquired by the image sensor is improved.

Based on the same inventive concept, the embodiment of the present application further provides an image sensor, which includes the pixel array of any of the above embodiments.

In an embodiment, the image sensor further includes a decoder timing circuit and a column signal readout circuit, and the decoder timing circuit is connected to each metal trace in the first metal trace group for performing timing control. The column signal readout circuit is connected to a column signal output line (i.e., the sixth metal trace) for performing signal reading processing.

Based on the same inventive concept, the application also provides a control method of the image sensor, which is applied to the image sensor of any one of the above embodiments. The timing of the m and m +1 rows of pixels in the image sensor is described in detail below, and the timing of the other rows of pixels can be implemented sequentially in the timing of the m and m +1 rows of pixels. Referring to fig. 3 and fig. 4 in combination, fig. 4 is a schematic diagram of a control timing of an image sensor according to an embodiment of the present application. In the sequence shown in fig. 4, a high potential indicates that the transistor is turned on, a low potential indicates that the transistor is turned off, and a high potential pulse of the read sequence indicates that the pixel outputs a signal through the column signal readout line, and the signal is read by the column signal circuit and processed in the next step.

As shown in fig. 4, the control method includes collecting image information for each row of pixels by using a row rolling exposure within a frame time sequence of the image sensor. Pixels corresponding to the third photosensitive pixel unit and the fourth photosensitive pixel unit in the pixel array are all first-type pixels or b-type pixels, and pixels corresponding to other photosensitive pixel units are all second-type pixels or a-type pixels. Specifically, the control method comprises the following steps:

carrying out first reset operation on the second type of pixels in the mth row through a reset metal wiring line which corresponds to the pixels in the mth row and the (m + 1) th row in common so as to clear charges in the photodiodes of the second type of pixels in the mth row; specifically, TXA < m > high-potential pulse operation and RST < m, m +1> high-potential pulse operation are given to the metal routing line corresponding to the second type pixels of the mth row.

Exposing the second type of pixels in the mth row; specifically, after the charge in the photodiode of the second type pixel in the mth row is cleared, the pixel starts to be exposed.

Carrying out first reset operation on the first type pixels in the mth row and the m +1 th row through a reset metal wiring line which is corresponding to the mth row and the m +1 th row of pixels together so as to clear the charges in the photodiodes of the first type pixels in the mth row and the m +1 th row; specifically, the metal trace TXb < m, m +1> high-potential pulse operation and RST < m, m +1> high-potential pulse operation are given to the first type of pixels in the mth row and the m +1 th row.

And exposing the first type pixels in the mth row and the m +1 th row.

Carrying out first reset operation on the second type of pixels in the m +1 th row through a reset metal wiring line which corresponds to the m +1 th row of pixels in common so as to clear charges in the photodiodes of the second type of pixels in the m +1 th row; specifically, the metal trace TXA < m +1> high-potential pulse operation and RST < m, m +1> high-potential pulse operation are given to the second type pixels of the m +1 th row.

And exposing the second type of pixels in the (m + 1) th row.

Carrying out second reset operation on the second type of pixels in the mth row through a reset metal wiring line which corresponds to the pixels in the mth row and the (m + 1) th row in common so as to eliminate the charges in the first floating diffusion active region in the first sharing structure and the charges in the second floating diffusion active region in the second sharing structure; specifically, the metal trace RS < m, m +1> is set to a high potential, and the metal trace RST < m, m +1> is given a high potential pulse operation.

And reading the reset signals of the second type pixels in the mth row. After the second-time reset of the second-type pixels in the mth row, specifically, the metal trace RS < m, m +1> is kept in a high-potential state, and a reset signal is output through a signal output line Sa < y >, which is denoted as ma _ R < y >, and is received and read by an external column signal reading circuit.

Ending the exposure of the second type pixels in the mth row and transferring the charges in the photodiodes of the second type pixels in the mth row to the first and second floating diffusion active regions; specifically, the metal trace RS < m, m +1> is kept in a high potential state, the metal trace TXa < m > of the second type pixel in the mth row is subjected to high potential pulse operation, the pixel exposure is finished, and the exposure period is recorded as T.

And reading initial photoelectric signals of the second type pixels in the mth row. Specifically, after the charge transfer of the second type pixels in the mth row, the step outputs an initial photoelectric signal, denoted as ma _ S < y >, through the signal output line Sa < y > by keeping the metal trace RS < m, m +1> in a high state, and the initial photoelectric signal is received and read by the external column signal reading circuit.

Carrying out second reset operation on the first type of pixels in the mth row and the m +1 th row through a reset metal wiring line which corresponds to the pixels in the mth row and the m +1 th row in common so as to eliminate the charges in the first floating diffusion active region and the charges in the second floating diffusion active region; specifically, the metal trace RS < m, m +1> is kept in a high potential state, and the metal trace RST < m, m +1> is given a high potential pulse operation.

And reading the reset signals of the first type pixels in the mth row and the m +1 th row. After the first-type pixels in the mth row and the (m + 1) th row are reset for the second time, specifically, the metal wires RS < m, m +1> are kept in a high potential state, a reset signal is output through the signal output line Sb < y >, which is recorded as mb & < m +1> b _ R < y >, and is received and read by the external column signal reading circuit.

And ending the exposure of the first-type pixels in the mth row and the m +1 th row, and transferring the charges in the photodiodes of the first-type pixels in the mth row and the m +1 th row to the first floating diffusion active region and the second floating diffusion active region. Specifically, the metal trace RS < m, m +1> is kept in a high potential state, the metal trace TXb < m, m +1> of the first type pixel in the mth row and the m +1 th row is subjected to high potential pulse operation, the pixel exposure is finished, and the exposure period is marked as T.

And reading initial photoelectric signals of the first type pixels in the mth row and the m +1 th row. Specifically, this step is performed after the charge transfer of the first type pixels in the mth row and the m +1 th row, by keeping the metal wirings RS < m, m +1> in a high potential state, and outputting an initial photoelectric signal, denoted as mb & < m +1> b _ S < y >, through the signal output line Sb < y >, to be received by the external column circuit for reading.

And carrying out second reset operation on the second type of pixels in the m +1 th row through the reset metal wiring lines which correspond to the m & ltth & gt row and the m +1 & ltth & gt row of pixels together so as to clear the charges in the first floating diffusion active region and the second floating diffusion active region. Specifically, the metal trace RS < m, m +1> is set to a high potential, and the metal trace RST < m, m +1> is given a high potential pulse operation.

And reading the reset signals of the second type pixels in the (m + 1) th row. Specifically, after the second-type pixels in the (m + 1) th row are reset for the second time, the reset signal is output through the signal output line Sa < y > by keeping the metal trace RS < m, m +1> in a high-potential state, and is recorded as < m +1> a _ R < y >, which is received and read by the external column signal reading circuit.

The exposure of the second type pixels in the m +1 th row is ended, and the charges in the photodiodes of the second type pixels in the m +1 th row are transferred to the first floating diffusion active region and the second floating diffusion active region. Specifically, the metal trace RS < m, m +1> is kept in a high-potential state, the metal trace TXa < m +1> of the second-type pixel in the (m + 1) th row is subjected to high-potential pulse operation, the pixel exposure is finished, and the exposure period is recorded as T.

And reading to obtain an initial photoelectric signal of the second type of pixels in the m +1 th row. Specifically, after the charge transfer of the second type pixel in the (m + 1) th row, the step outputs an initial photoelectric signal through the signal output line Sa < y > by keeping the metal trace RS < m, m +1> in a high potential state, which is denoted as < m +1> a _ S < y >, and the initial photoelectric signal is received and read by the external column signal reading circuit.

Optionally, the expression of the photoelectric signal collected by the second type of pixel in the mth row is: siga (m, y) ═ ma _ r (y) — ma _ s (y), where Siga (m, y) is the photoelectric signal collected by the second type of pixels in the mth row, ma _ r (y) is the reset signal read out from the second type of pixels in the mth row, ma _ s (y) is the initial photoelectric signal read out from the second type of pixels in the mth row, and y is the column position where the pixels are located.

Optionally, the expression of the photoelectric signal collected by the first type of pixel in the mth row and the m +1 th row is: sigb (m, y) & < m +1> b _ r (y) -mb & < m +1> b _ s (y), where Sigb (m, y) is a photoelectric signal collected from the first type pixels in the m-th and m + 1-th rows, mb & < m +1> b _ r (y) is a reset signal read out from the first type pixels in the m-th and m + 1-th rows, mb & < m +1> b _ s (y) is an initial photoelectric signal read out from the first type pixels in the m-th and m + 1-th rows, and y is a column position where the pixels are located.

Optionally, the expression of the photoelectric signal collected by the second type of pixel in the m +1 th row is: siga (m +1, y) < m +1> a _ r (y) < m +1> a _ s (y), where Siga (m +1, y) is the photoelectric signal collected by the second type of pixel in the m +1 th row, < m +1> a _ r (y) is the reset signal read out from the second type of pixel in the m +1 th row, < m +1> a _ s (y) is the initial photoelectric signal read out from the second type of pixel in the m +1 th row, and y is the column position where the pixel is located.

It should be noted that, where the embodiments of the method are not described or detailed, please refer to the description of the foregoing embodiments, and detailed description is omitted here.

The pixel array provided by the embodiment of the application can effectively improve the occupancy of the area of a photodiode in a pixel through a six-pixel sharing structure and a specific layout mode thereof, thereby improving the photoelectric conversion quantum efficiency of the pixel, a first source following transistor is positioned in the middle of two parts of a first floating diffusion active area, a second source following transistor is positioned in the middle of two parts of a second floating diffusion active area, so that the first floating diffusion active area and the second floating diffusion active area are respectively shorter than metal connecting wires of a grid electrode of the first source following transistor and a grid electrode of the second source following transistor, and the parasitic capacitance of the metal related part is lower, thereby effectively reducing the parasitic capacitance of the floating diffusion active area in the pixel, improving the photoelectric conversion gain of the pixel and improving the image quality acquired by an image sensor. .

In the description herein, references to the description of terms such as "an embodiment," "an implementation," "an example" or "a specific example" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment, implementation, or example is included in at least one embodiment, implementation, or example of the application. In this specification, a schematic representation of the above terms does not necessarily refer to the same embodiment, implementation, or example. And the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, various embodiments, implementations, or examples described in this specification can be combined and combined by one skilled in the art.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

Claims (14)

1. A pixel array comprising a plurality of pixel groups arranged in an array, each of the pixel groups comprising six pixels including six photosensitive pixel units each including a photodiode and a transfer transistor connected to each other and first and second sharing structures connected to each other, wherein,

first, second and third of the six light-sensitive pixel units share the first shared structure; a fourth, fifth and sixth of the six light-sensitive pixel units share the second shared structure; the first, fourth and fifth light-sensitive pixel units are positioned on the m-th row of the pixel array and are sequentially arranged from left to right, and the second, third and sixth light-sensitive pixel units are positioned on the m + 1-th row of the pixel array and are sequentially arranged from left to right; the grid electrode of the transmission transistor of the third photosensitive pixel unit is connected with the grid electrode of the transmission transistor of the fourth photosensitive pixel unit;

the first sharing structure comprises a first floating diffusion active area, a first reset transistor and a first source follower transistor, wherein the first floating diffusion active area is connected with the first reset transistor and the first source follower transistor, the first floating diffusion active area comprises a first part and a second part which are connected with each other, the first source follower transistor is positioned at the junction of the vertex angles of the photodiodes of the first photosensitive pixel unit, the second floating diffusion active area is positioned between the photodiodes of the first photosensitive pixel unit and the second photosensitive pixel unit, and the first part and the second part of the first floating diffusion active area are respectively positioned at two sides of the first source follower transistor along the row direction; and/or the second sharing structure comprises a second floating diffusion active region, a second reset transistor and a second source following transistor which are connected, the second floating diffusion active region comprises a first part and a second part which are connected, the second source following transistor is positioned at the corner junction of the photodiodes of the third, fourth, fifth and sixth photosensitive pixel units, the second reset transistor is positioned between the photodiodes of the fifth and sixth photosensitive pixel units, and the first part and the second part of the second floating diffusion active region are respectively positioned at two sides of the second source following transistor along the row direction.

2. The pixel array of claim 1, wherein the six photosensitive pixel cells are arranged in a rectangular arrangement of two rows and three columns; wherein the content of the first and second substances,

the first photosensitive pixel unit and the second photosensitive pixel unit are arranged in a mirror image mode along the row direction, and the second photosensitive pixel unit and the third photosensitive pixel unit are arranged in a mirror image mode along the column direction; the fourth photosensitive pixel unit and the fifth photosensitive pixel unit are arranged in a mirror image mode along the column direction, and the fifth photosensitive pixel unit and the sixth photosensitive pixel unit are arranged in a mirror image mode along the row direction.

3. The pixel array of claim 2, wherein the transfer transistors in the third photosensitive pixel cell are located at corners of the corresponding photodiodes, the transfer transistors in the fourth photosensitive pixel cell are located at corners of the corresponding photodiodes, and the transfer transistors in the third photosensitive pixel cell and the transfer transistors in the fourth photosensitive pixel cell are centered symmetrically with respect to a center point of the corresponding pixel group.

4. The pixel array of claim 3, wherein the transfer transistors in the first, second and third light-sensitive pixel cells are located at a lower right corner, an upper right corner and an upper left corner of the corresponding photodiode, respectively; the transmission transistors in the fourth, fifth and sixth photosensitive pixel units are respectively located at the lower right corner, the lower left corner and the upper left corner of the corresponding photodiode.

5. The pixel array according to claim 2, wherein a source of the first reset transistor, a gate of the first source follower transistor, and a drain of a transfer transistor of a corresponding photosensitive pixel cell are respectively connected to the first floating diffusion active region, a drain of the first reset transistor and a drain of the first source follower transistor are connected to corresponding power signal lines, and a source of the first source follower transistor is connected to a corresponding signal output line; and/or the presence of a gas in the gas,

the source electrode of the second reset transistor, the gate electrode of the second source follower transistor and the drain electrode of the transmission transistor of the corresponding photosensitive pixel unit are respectively connected with the second floating diffusion active region, the drain electrode of the second reset transistor and the drain electrode of the second source follower transistor are connected with the corresponding power signal line, and the source electrode of the second source follower transistor is connected with the corresponding signal output line.

6. The pixel array according to claim 5, wherein the first source follower transistor is disposed at a middle position of a connection line of the two portions of the first floating diffusion active region, and/or the connection line of the first reset transistor and the first floating diffusion active region is disposed along a row direction; and/or the presence of a gas in the gas,

the second source follower transistor is arranged in the middle of a connecting line of the two parts of the second floating diffusion active region, and/or the second reset transistor and the connecting line of the second floating diffusion active region are arranged along the row direction.

7. The pixel array of claim 5, wherein the pixel array further comprises a plurality of first metal routing groups, each first metal routing group corresponding to a row of the pixel groups, a row of the pixel groups corresponding to two rows of pixels of the pixel array, each first metal routing group comprising: the first metal routing, the second metal routing, the third metal routing and the fourth metal routing; wherein, the first and the second end of the pipe are connected with each other,

the first metal wire is used for providing transmission control signals for the transmission transistors of the first and fifth photosensitive pixel units in the pixel group of the corresponding line;

the second metal routing is used for providing transmission control signals for the transmission transistors of the third and fourth photosensitive pixel units in the pixel group of the corresponding row;

the third metal wire is used for providing transmission control signals for the transmission transistors of the second and sixth photosensitive pixel units in the pixel group of the corresponding line;

the fourth metal routing is used for providing reset signals for the first reset transistor and the second reset transistor in the pixel group of the corresponding row.

8. The pixel array of claim 7, wherein the first sharing structure further comprises a first pixel selection transistor, a drain of the first pixel selection transistor being connected to a source of the first source follower transistor, a source of the first pixel selection transistor being connected to a corresponding signal output line; and/or the presence of a gas in the gas,

the second sharing structure further includes a second pixel selection transistor, a drain of the second pixel selection transistor is connected to a source of the second source follower transistor, and a source of the second pixel selection transistor is connected to a corresponding signal output line.

9. The pixel array according to claim 8, wherein the first pixel selection transistor is located on one side of the first source follower transistor in a column direction; and/or the presence of a gas in the gas,

the second pixel selection transistor is located on one side of the second source follower transistor in a column direction.

10. The pixel array of claim 8, wherein the first metal routing group further comprises a fifth metal routing for providing a pixel selection signal for the first pixel selection transistor and/or the second pixel selection transistor in the pixel group of the corresponding row.

11. The pixel array of claim 7, further comprising a plurality of sixth metal traces for outputting signals; each column of pixel group corresponds to two sixth metal wires, and the two sixth metal wires corresponding to each column of pixel group are respectively connected with the source electrodes of the first source follower transistor and the second source follower transistor in the corresponding column of pixel group.

12. The pixel array of claim 7, further comprising a plurality of seventh metal traces extending in the column direction for providing power signals; and each two rows of pixel groups correspond to seven seventh metal wires, and two sides of each row of pixels are respectively and correspondingly provided with one seventh metal wire.

13. The pixel array of claim 1, wherein a gate of the transfer transistor of the third photosensitive pixel cell is connected to a gate of the transfer transistor of the fourth photosensitive pixel cell by gate polysilicon; the first and second portions of the first floating diffusion active region are connected by a metal line, and the first and second portions of the second floating diffusion active region are connected by a metal line.

14. An image sensor, comprising: a pixel array as claimed in any one of claims 1 to 13.

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