JP2000012791A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an MFS-type field effect transistor which is superior in characteristics. SOLUTION: A method of manufacturing an MFS-type field effect transistor comprises a first process, in which a buffer insulating film 102 is formed on a semiconductor board 101, a second process where insulating films 103 and 104 provided with an opening 105 are provided on the buffer insulating film 102, a third process where a conductor film is epitaxially grown in the opening 105 for the formation of a gate electrode 106 inside the opening 105. a fourth process where a ferroelectric film is epitaxially grown as a gate insulating film 107 on the gate electrode 106, and a fifth process where a semiconductor film 108 is formed on the gate insulating film 107.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device using a ferroelectric film as a gate insulating film and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a semiconductor memory element that has recently attracted attention, an FeRAM (FeRAM) that performs an information storage operation by combining a transistor, a capacitor, and a ferroelectric capacitor is known.
rroelectric random access read / write memory), and application to an RF-ID card or the like is considered. As such a capacitor dielectric film for FeRAM, P
bZr _x Ti _1-x O ₃ (PZT) film or SrBi ₂ Ta ₂
O ₉ (SBT) films and the like are being actively studied. FeRAM using polarization reversal of ferroelectric film as memory effect
Can rewrite information by injecting electrons through a conventional oxide film because polarization inversion can be performed at a relatively low voltage and the reversal speed is high by devising the material of the ferroelectric film and reducing the film thickness. E ² PROM (Electrically Erasable
As compared with Random Access Memory, there is an advantage that low-voltage and high-speed operation can be performed.

However, in the FeRAM, since a memory cell is formed by combining a transistor and a ferroelectric capacitor, it is disadvantageous for high integration as compared with an E ² PROM in which a memory cell is formed by one transistor. It is. Also, in order to stabilize operation against problems such as variations in characteristics of the high dielectric film, there is a method of configuring one cell using two transistors and capacitors, but from the viewpoint of high integration. Further disadvantages.

Further, it is known that such a ferroelectric capacitor has a problem of film fatigue such that the amount of polarization is reduced due to the polarization reversal of the film. In a normal FeRAM, not only rewriting but also reading involves polarization reversal of the ferroelectric film, so that film fatigue is a serious problem. It has been reported that in the case of a PZT film, film fatigue occurs when the polarization is inverted less than 10 ¹² times. Future D
If FeRAM is used for the same purpose as RAM, 1
It is required that the fatigue phenomenon does not occur even when the polarization is inverted more than ¹⁵ times, but it is not easy to satisfy this requirement.

On the other hand, memory devices using a ferroelectric material include:
MFS (Metal) using a ferroelectric film as a gate dielectric film
An element using a field effect transistor of the (ferroelectric semiconductor) type has been proposed from an early stage, and the study thereof has been advanced from a basic stage to a practical stage.

However, in the case of an MFS transistor, more stable characteristics are required as compared with a case where a ferroelectric film is used for a capacitor. That is, electrical instability due to the movement of charge traps and charged defects caused by defects in the ferroelectric film, or deterioration of various characteristics caused by reactions at the interface between the ferroelectric film and Si becomes a problem.
It is a factor that hinders practical application. Conventionally, Si
That a SiO ₂ film is generated at the interface between the ferroelectric film and
It is known that interdiffusion occurs between an element constituting the ferroelectric film and Si, and it is difficult to sufficiently suppress these. In particular, in the case of a PZT film or an SBT film as described above, Pb or Bi diffuses into Si,
There is a problem such as deterioration of polarization reversal characteristics due to the formation of the SiO ₂ film on the Si surface. For this reason, conventionally proposed MFS transistors have insufficient characteristics.

On the other hand, it is important to form source / drain regions in a self-aligned manner from the viewpoint of integration and minimizing variations in the characteristics of fine transistors. In the manufacturing process, a thermal process at 800 ° C. or higher is performed after the gate insulating film is formed to form source / drain regions, and a thermal process after the formation of the ferroelectric film is inevitable. Therefore, the characteristic deterioration of the ferroelectric film described above is further accelerated. Therefore, it has been difficult to form a fine transistor while maintaining good ferroelectric characteristics.

Further, there is a problem that the ferroelectric film itself generally loses ferroelectricity as the film is made thinner, and therefore, it has been difficult to realize a fine MFS which necessarily requires a thinner film.

On the other hand, epitaxial Ba _x Sr
It is known that _1-x TiO ₃ (BST) films exhibit good ferroelectricity up to a thickness of 20 nm or less. In this case, the ferroelectricity of the epitaxial BST film is considered to be due to the lattice constant extending in the C-axis (the film thickness direction). However, a report example in which an epitaxial BST film is usually formed on a Si surface. Never before. As described above, although the epitaxial BST film is suitable for miniaturization and thinning, it is expected that it will be very difficult to actually apply it to an MFS transistor.

[0010]

As described above, in an MFS type field effect transistor in which a ferroelectric film is applied to a gate insulating film, formation of a silicon oxide film at an interface between silicon and the ferroelectric film is prevented. In addition, it is difficult to sufficiently suppress the interdiffusion between the element constituting the ferroelectric film and silicon, and there is a problem that satisfactory characteristics cannot be obtained. Further, there is also a problem that the ferroelectric film generally loses ferroelectricity due to thinning. Although it is known that an epitaxial BST film shows ferroelectricity even when it is made thin, it is difficult to form an epitaxial BST film on a silicon surface, and it is difficult to manufacture a good MFS type field effect transistor. difficult. As described above, the MFS type field effect transistor is a promising storage element, but has many problems in reality.

An object of the present invention is to provide a semiconductor device such as an MFS type field effect transistor having excellent characteristics and a method of manufacturing the same, which has been made to solve the above-mentioned conventional problems.

[0012]

According to the present invention, there is provided a semiconductor device comprising: a gate electrode formed of an epitaxial film formed on a crystalline base; and a gate insulating film formed of an epitaxial film formed on the gate electrode. And a semiconductor film formed on the gate insulating film (claim 1).

According to the method of manufacturing a semiconductor device of the present invention, a step of epitaxially growing a conductive film to be a gate electrode on a crystalline base, a step of epitaxially growing a gate insulating film on the conductive film, Forming a semiconductor film on the gate insulating film (claim 5).

As the underlayer having the crystallinity, a substrate in which a buffer insulating film made of an epitaxial film is formed on a single crystal semiconductor substrate can be used. Further, the semiconductor film formed on the gate insulating film is preferably formed by epitaxial growth.

The gate insulating film composed of the epitaxial film may be a ferroelectric film (claim 3), and the ferroelectric film may be a film having a perovskite crystal structure. 4).
Further, as the conductor film serving as the gate electrode, a film having a perovskite crystal structure can be given.

In the present invention, a gate insulating film formed by epitaxial growth is formed on a conductor film (gate electrode) formed by epitaxial growth, and a semiconductor film forming a channel is formed thereon. Accordingly, a single crystal or a gate insulating film having excellent ferroelectric characteristics with excellent crystallinity can be used, and the stability of the interface between the gate insulating film and the semiconductor film can be significantly improved, and the characteristics are excellent. Thus, an MFS type field effect transistor can be obtained. In addition, by using a gate insulating film formed by epitaxial growth, a leak current caused by a crystal grain boundary (a leak current between a gate electrode and a semiconductor film)
Therefore, the present invention is effective not only for the MFS type field effect transistor but also for a normal MIS type field effect transistor not using a ferroelectric film for the gate electrode.

In the present invention, since epitaxial growth is performed sequentially from the lower layer side, it is necessary to select a substrate material or a material to be grown thereon from such a viewpoint. In general, it is assumed that the epitaxial growth becomes easier as the crystal form and the lattice constant are equivalent (however, there are many examples in which epitaxial growth is possible in other cases). For example, using a SrTiO ₃ substrate, a SrRuO ₃ film that becomes an electrode in sequence and a Ba _x Sr film that becomes a ferroelectric film are used.
_{If a 1-x} TiO ₃ film is formed, epitaxial growth easily occurs in terms of crystal form and lattice constant. In addition, Mg
Similar effects can be obtained for an O substrate.

Considering application to a semiconductor integrated circuit, it is desirable to use silicon as a substrate material. It is known that, for example, a CaF ₂ film, a CeO ₂ film, or the like is epitaxially grown on a silicon substrate (the same applies to a GaAs substrate).
It has been reported that an rTiO ₃ film grows epitaxially (LSHung, et al., J. Appl. Phys. 74 (2), (1993) p
p1366-1375, QXJia et al., Thin Solid Films 299, p
p115-118 (1997)). Thus, a desired material can be epitaxially grown on the silicon substrate via the epitaxial film serving as a buffer. Also, SrT
It has also been reported that an iO ₃ film can be epitaxially grown directly on silicon (Bum Ki Moon et al., JPN.J. App.
l. Phys., 33, (1994) pp1472-1477), and using this as a buffer, it is possible to sequentially epitaxially grow a desired material.

In the Ba _x Sr _{1 -x} TiO ₃ film, the lattice constant extends in the c-axis direction (thickness direction) when epitaxially grown on a crystal film having a slightly smaller lattice constant. Has been reported, and high dielectric properties are maintained despite thinning (K. Abe et a
l., JPN. J. Appl. Phys., 36 (1997) pp5575-5579). In this case, good characteristics can be obtained by using, for example, an SrRuO ₃ film as the underlying gate electrode. From such a viewpoint, a ferroelectric film serving as a gate insulating film and a conductive film serving as a gate electrode having a perovskite crystal structure are used, and the lattice constant of the ferroelectric film is reduced by the lattice of the conductive film serving as the gate electrode. It is preferable to set the value slightly larger than the constant.

In the MFS type field effect transistor, controlling the interface between the ferroelectric film and the semiconductor (particularly, silicon) has been a major problem. That is, conventionally, there is a possibility that the film quality of the ferroelectric film is deteriorated and the electrical characteristics are deteriorated due to a natural oxide film that grows on the silicon surface or interdiffusion at an interface caused by a subsequent thermal process. . According to the present invention, such a problem can be avoided since the semiconductor film is formed after the ferroelectric film. Normally, for example, LP-CVD using silane gas is widely used for forming a silicon film.
Since Ba _x Sr _1-x TiO ₃ film is in a normal CVD film formation temperature is not reduced even under silane atmosphere, Ba _x S
LP-CV is used for forming a silicon film on the r _1-x TiO ₃ film.
It is also possible to use the D method.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming an insulating film having an opening on a base having crystallinity, and a step of forming a conductor on the base having crystallinity exposed in the opening are provided. A step of forming a gate electrode made of the conductive film in the opening by epitaxially growing the film, a step of epitaxially growing a gate insulating film on the gate electrode, and a step of forming a semiconductor film on the gate insulating film (Chart 6).

Further, the method of manufacturing a semiconductor device according to the present invention includes the steps of epitaxially growing a conductive film on a base having crystallinity and processing the same to form a gate electrode;
A step of forming an insulating film having an opening on the base on which the gate electrode is formed, a step of epitaxially growing a gate insulating film on the gate electrode exposed in the opening, and a step of forming a semiconductor film on the gate insulating film. And a step of forming (claim 7).

In the case where the above-mentioned manufacturing method is used, at least a surface region of the insulating film having the opening is made to contain a dopant which is an impurity in advance, and the dopant is diffused from the dopant, thereby being self-aligned with the gate electrode. It is also possible to form source / drain regions in a specific manner, which reduces variations in transistor characteristics and facilitates miniaturization of the transistor.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) The first embodiment of the present invention relates to (100)
After forming an epitaxial SrRuO ₃ film serving as a gate electrode on a Si substrate via an epitaxial film, an epitaxial BST film serving as a gate insulating film is formed, and a Si film is further formed thereon to form a ferroelectric transistor. It was made. Hereinafter, FIGS. 1A to 1
The manufacturing process will be described with reference to FIG.

First, as shown in FIG.
0Ωcm (100) p-type single crystal silicon substrate 101
An SrT film having a thickness of about 50 nm serving as a buffer insulating film
The iO ₃ film 102 is grown epitaxially. afterwards,
A CVD-SiO ₂ film 103 having a thickness of about 100 nm and a PSG film or BSG film 104 having a thickness of about 50 nm are deposited. PSG film for n-ch transistor, p
A CMOS structure can be formed by separately depositing BSG films for the -ch transistors. Thereafter, an opening 105 is formed by ordinary photolithography and reactive ion etching to form Sr.
The surface of the TiO ₃ film 102 is exposed.

Next, as shown in FIG. 1B, SrRu
Sr exposing O ₃ film 106 at the bottom of opening 105
A 200 nm-thick film is deposited on the TiO ₃ film 102 so as to grow epitaxially, and the epitaxial SrRuO ₃ film 106 is buried in the opening 105. Thereafter, the epitaxial SrRuO is formed by a chemical mechanical polishing method (CMP method).
_The flattening is performed so that the ₃ film 106 remains only inside the opening 105, and then the epitaxial SrRuO ₃ film 1
06 receded by about 50 nm to form a gate electrode.

Further, as shown in FIG. 1C, a 15-nm-thick Ba _0.75 Sr _0.25 TiO ₃ film serving as a gate insulating film is formed.
A film 107 is deposited on the entire surface by sputtering at 600 ° C.
Epitaxial growth is performed on the SrRuO ₃ film 106. The Ba _0.75 Sr _0.25 TiO ₃ film 107 is made of SrRu
By epitaxial growth on the O ₃ film 106, its lattice constant extends in the film thickness direction, so that ferroelectricity is exhibited even though the film thickness is small. After that, Ba _0.75
100 nm thick S is deposited on the entire surface of the Sr _0.25 TiO ₃ film 107.
LP-CVD using silane gas, for example,
It is deposited by the method. After that, planarization is performed by the CMP method. At this time, Ba _0.75
The Sr _0.25 TiO ₃ film 107 and the Si film 108 are left.

Next, as shown in FIG.
A Si film 109 having a thickness of 0 nm is deposited, and is patterned by ordinary photolithography and reactive ion etching. Subsequently, the RTP is performed in an N ₂ atmosphere at 800 ° C.
To diffuse phosphorus or boron from the PSG film or the BSG film 104 into a predetermined region of the Si film 109 to form a source / drain region 110. After that, a CVD-SiO ₂ film 111 serving as an interlayer film is deposited, and then a contact hole is formed by ordinary photolithography and reactive ion etching. Next, the W plug 112 is embedded in the contact hole, and
13 is formed. Thereafter, several Al wirings are formed to complete the ferroelectric memory device.

In this embodiment, an epitaxial SrTiO ₃ film is formed on a Si substrate, but other than this, for example, a CeO ₂ film, a CaF ₂ film, a YSZ film, a YBCO film, etc.
It is also possible to use an epitaxial film such as a film. It is also possible to use a material having an equivalent lattice constant other than the SrRuO ₃ film as an electrode material. Further, a Ba _0.75 Sr _0.25 TiO ₃ film is used as the ferroelectric film, but the composition ratio of Ba and Sr can be changed as appropriate. Further, the Si film can be formed by, for example, a sputtering method or the like other than the LP-CVD method.

(Embodiment 2) In a second embodiment of the present invention, an epitaxial SrRuO ₃ film serving as a gate electrode is formed on a (100) Si substrate via an epitaxial film, and then an epitaxial BST film is formed. Further, a ferroelectric transistor was produced by forming a Si film thereon. Hereinafter, FIGS. 2A to 2D
The manufacturing process will be described with reference to FIG.

First, as shown in FIG.
0Ωcm (100) p-type single crystal silicon substrate 201
A CeO ₂ film 202 having a thickness of about 50 nm is epitaxially grown thereon. After that, a 200 nm thick SrRuO
_{The 3} film 203 is epitaxially grown on the CeO ₂ film 202, and the SrRuO ₃ film 203 is patterned by a normal photolithography method and a reactive ion etching method to form a gate electrode.

Next, as shown in FIG. 2B, a PSG film or BSG film 204 having a thickness of 250 nm is deposited on the entire surface, and then the opening 205 is formed by ordinary photolithography and reactive ion etching. Form. Subsequently, Ba _0.75 Sr with a thickness of 15 nm is used as a gate insulating film.
_{A 0.25} TiO ₃ film 206 is deposited on the entire surface by a sputtering method at 600 ° C., and a patterned SrRuO ₃ film 203
Epitaxial growth is performed on the upper exposed portion.
As in the case of the first embodiment, Ba _0.75 Sr _0.25 TiO
_Since the lattice constant of the ₃ film 206 is extended in the thickness direction by epitaxial growth on the SrRuO ₃ film 203, the ₃ film 206 exhibits ferroelectricity despite its small thickness.

Next, as shown in FIG. 2C, a Si film 207 having a thickness of 100 nm is deposited on the entire surface and flattened by the CMP method. At this time, only the region of the opening 205 is formed. The Ba _0.75 Sr _0.25 TiO ₃ film 206 and the Si film 207 are left.

After that, as shown in FIG. 2D, a Si film 208 having a thickness of 100 nm is further deposited, and is patterned by ordinary photolithography and reactive ion etching. Subsequently, heat treatment is performed by RTP in an N ₂ atmosphere at 800 ° C. to diffuse phosphorus or boron from the PSG film or the BSG film 204 into a predetermined region of the Si film 208 to form a source / drain region 209. Thereafter, a CVD-SiO ₂ film 2 serving as an interlayer film is formed on the entire surface.
After depositing 10, a contact hole is formed by ordinary photolithography and reactive ion etching.
Next, a W plug 211 is embedded in the contact hole, and an Al wiring 212 is formed. Thereafter, several Al wirings are formed to complete the ferroelectric memory device.

Although an epitaxial CeO ₂ film is formed on Si in this embodiment, an epitaxial SrTiO ₃ film may be used as in the first embodiment, or a CaF ₂ film, a YSZ film, It is also possible to use an epitaxial film such as a YBCO film. S as electrode material
In addition to the rRuO ₃ film, it is also possible to use a material having the same lattice constant as that of Ba _0.75 Sr to be a ferroelectric film.
_{Also for the 0.25} TiO ₃ film, the composition ratio of Ba and Sr can be appropriately changed.

(Embodiment 3) In the third embodiment, as in the first embodiment, an epitaxial BST film is formed as a gate insulating film on an epitaxial gate electrode, and a Si film is further formed thereon. However, the process is more simplified than in the first embodiment. Hereinafter, the manufacturing process will be described with reference to FIGS. 3 (a) to 3 (d).

First, as shown in FIG.
0Ωcm (100) p-type single crystal silicon substrate 301
An SrTiO ₃ film 302 having a thickness of about 50 nm is epitaxially grown thereon. After that, C having a thickness of about 100 nm
A VD-SiO ₂ film 303 and a PSG film or BSG film 304 having a thickness of about 50 nm are deposited. After that, an opening 305 is formed by ordinary photolithography and reactive ion etching.

Next, as shown in FIG. 3B, SrRu
Sr exposing O ₃ film 306 at the bottom of opening 305
A 200 nm-thick film is deposited on the TiO ₃ film 302 so as to grow epitaxially, and the epitaxial SrRuO ₃ film 306 is embedded in the opening 305. After that, planarization is performed by a CMP method so that the epitaxial SrRuO ₃ film 306 remains only inside the opening 305 to form a gate electrode.

Further, as shown in FIG.
A 5 nm Ba _0.75 Sr _0.25 TiO ₃ film 307 is deposited on the entire surface by a CVD method, and is epitaxially grown on the SrRuO ₃ film 306. Ba _0.75 Sr _0.25 TiO ₃
The film 307 is epitaxially grown on the SrRuO ₃ film 306, so that its lattice constant extends in the film thickness direction. After that, a Si film 308 having a thickness of 100 nm is deposited on the whole surface of the Ba _0.75 Sr _0.25 TiO ₃ film 307, and is patterned by ordinary photolithography and reactive ion etching.

Next, as shown in FIG. 3D, after depositing a CVD-SiO ₂ film 310 as an interlayer film, a contact hole is formed by a usual photolithography method and a reactive ion etching method. A source / drain region 309 is formed by an implantation method and a heat treatment using RTP. Next, a W plug 311 is embedded in the contact hole, and an Al wiring 312 is formed. After this,
Several Al wirings are formed to complete a ferroelectric memory device.

In this embodiment, an epitaxial SrTiO ₃ film is formed on Si, but other materials can be used as in the first embodiment.
Similarly, as the electrode material, other than the SrRuO ₃ film, a material having an equivalent lattice constant can be used, and the composition ratio of the ferroelectric film can be appropriately changed.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention.

[0043]

According to the present invention, a gate insulating film having excellent ferroelectric characteristics by epitaxial growth can be used, and the stability of the interface between the gate insulating film and the semiconductor film can be greatly improved. An MFS type field effect transistor having excellent characteristics can be obtained. In addition, by using a gate insulating film formed by epitaxial growth, leakage current due to crystal grain boundaries can be suppressed, so that excellent characteristics can be obtained not only in an MFS type field effect transistor but also in a normal MIS type field effect transistor. Can be.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing a manufacturing process according to a second embodiment of the present invention.

FIG. 3 is a process cross-sectional view showing a manufacturing process according to a third embodiment of the present invention.

[Explanation of symbols]

101, 201, 301 silicon substrate 102, 302 SrTiO ₃ film 103, 303 SiO ₂ film 104, 204, 304 PSG or BSG film 105, 205, 305 opening 106, 203, 306 SrRuO ₃ film 107 _{, 206,307 ... Ba 0.75 Sr 0.25 TiO} 3 film 108,109,207,208,308 ... silicon film 110,209,309 ... source and drain regions 111,210,310 ... SiO ₂ film 112,211,311 ... W Plugs 113, 212, 312: Al wiring 202: CeO ₂ film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/788 29/792 (72) Inventor Mitsuaki Dewa 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Pref. F-term in Toshiba Yokohama Office (reference) 5F001 AA17 AG26 AG32 5F045 AA06 AC01 AE01 CA05 5F083 FR05 JA14 JA43 PR21 PR25 PR40

Claims (7)

[Claims] A gate electrode comprising an epitaxial film formed on a base having crystallinity; a gate insulating film comprising an epitaxial film formed on the gate electrode;
And a semiconductor film formed on the gate insulating film. 2. The semiconductor device according to claim 1, wherein the base having crystallinity is a single crystal semiconductor substrate on which a buffer insulating film made of an epitaxial film is formed. 3. The gate insulating film comprising an epitaxial film is a ferroelectric film.
3. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 3, wherein said ferroelectric film has a perovskite crystal structure. 5. A step of epitaxially growing a conductive film to be a gate electrode on a crystalline base, a step of epitaxially growing a gate insulating film on the conductive film, and forming a semiconductor film on the gate insulating film. And a method of manufacturing a semiconductor device. 6. A step of forming an insulating film having an opening on a base having crystallinity, and epitaxially growing a conductive film on the base having crystallinity exposed in the opening, and forming the conductive film in the opening. A method of manufacturing a semiconductor device, comprising: a step of forming a gate electrode comprising: a step of epitaxially growing a gate insulating film on the gate electrode; and a step of forming a semiconductor film on the gate insulating film. 7. A step of epitaxially growing a conductive film on a base having crystallinity and processing it to form a gate electrode, and forming an insulating film having an opening on the base on which the gate electrode is formed. A method of manufacturing a semiconductor device, comprising the steps of: epitaxially growing a gate insulating film on a gate electrode exposed in an opening; and forming a semiconductor film on the gate insulating film.