JP2000010817A - Program development support system, program-type arithmetic processor, and program development support device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a program development support device system which allows a microcomputer to execute a specific instruction code with a desired timing. SOLUTION: Once an address match detecting circuit 22 detects an address that an instruction decoder 13 indicates matching a jamming address, a jamming request signal S72 outputted to a selector 61 of the microcomputer 52 through a communication cable 33 is switched from a logical value '1' to '0' and a selector 61 selects a specific instruction code stored in a specific instruction code memory 62, so that it is outputted to an instruction decoder 13 through an instruction prefetch circuit 11 and a selector 12. The instruction decoder 13 executes the specific instruction code to stop a logical operation circuit 14 from operating.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a program development support system, a microcomputer, and a program development support device.

[0002]

2. Description of the Related Art Electronic devices, such as video cameras and CD (Compact Disk) players, incorporate microcomputers for controlling processing in the electronic devices. Such a microcomputer has a ROM (Read Only M
emory) and operates based on a control program read from the ROM. In the process of developing a control program stored in a ROM built in such a microcomputer, for example, a program development support device called an ICE (in-circuit emulator) is used.

FIG. 4 is a diagram for explaining a conventional microcomputer 2 and a program development support device (ICE) 4. As shown in FIG. 4, the microcomputer 2 has a configuration in which a ROM 10, an instruction prefetch circuit 11, a selector 12, an instruction decoder 13, a logical operation circuit 14, a program counter 15, and a data bus 16 are incorporated in one chip. . The program development support device 4 includes a jamming address memory 21, an address coincidence detection circuit 22, a specific instruction code memory 23, a selector 24, a memory 25, a monitor 26, an input unit 27, and a control circuit 28.

[0004] The microcomputer 2 and the program development support device 4 can be detachably connected via communication cables 30, 31 and 32. Microcomputer 2
Has an external terminal 30 connected to the communication cable 30.
₁ and an external terminal 31 connected to the communication cable 31
₁ and an external terminal 32 ₁ connected to the communication cable 32. The program development supporting apparatus 4, an external terminal 30 ₂ connected to the communication cable 30,
An external terminal 31 ₂ connected to the communication cable 31, and the external terminal 32 ₂ is provided which is connected to the communication cable 32.

A microcomputer 2 shown in FIG.
The microcomputer 2 and the program development support device 4 when debugging the control program in the development stage of the control program stored in the ROM 10 built in
Will be described. Here, the operation in the case where the selector 12 selects the instruction code from the instruction prefetch circuit 11 based on the selector signal S40 and outputs the instruction code to the instruction decoder 13 will be described.

First, the ROM 1 of the microcomputer 2
For example, at the stage of developing a control program to be stored in the microcontroller 0, the microcomputer 2 and the program development support device 4 mutually communicate via the communication cables 30, 31, 32 when debugging the developed control program. Connected.

[0007] The control program under development is stored in the memory 25 via the input unit 27 of the program development support device 4.
Is stored. In addition, the selector 2 is configured to select the specific instruction code read from the specific instruction code memory 23.
The jamming address, which is the address indicated by the program counter 15 when switching 4, is stored in the jamming address memory 21 via the input unit 27.

Then, the instruction code of the control program read from the address on the memory 25 indicated by the program counter 15 of the microcomputer 2 is transmitted to the microcomputer 2 via the selector 24, the communication cable 30 and the data bus 16. To the instruction prefetch circuit 11. The instruction code is stored in the prefetch register of the instruction prefetch circuit 11, and then output to the instruction decoder 13 via the selector 12. Then, the instruction code is decoded by the instruction decoder 13, and a control signal S13a corresponding to the decoding result is obtained.
Is output to the logical operation circuit 14. The logical operation circuit 14 performs an operation using necessary data based on the control signal S13a. At this time, the intermediate and final results of the operation in the logical operation circuit
Is temporarily stored in a register.

When decoding is performed in the instruction decoder 13, the address indicated by the program counter 15 is incremented by a predetermined number, and the incremented address is transmitted via the communication cable 31.
It is output to the memory 25 of the program development support device 4.
Then, the instruction code of the incremented address of the program counter 15 is read from the memory 25, and the above-described processing is repeated.

Thereafter, when the address match detection circuit 22 detects that the address indicated by the program counter 15 matches the jamming address stored in the jamming address memory 21, the address match detection circuit 22 outputs the same to the selector 24. Selector signal S22
Switches from the logical value “1” to “0”, for example. Thereby, the specific instruction code stored in the specific instruction code memory 23 is transferred to the instruction prefetch circuit 11 via the selector 24, the communication cable 30, and the data bus 16.
Is output to

After the specific instruction code is stored in the prefetch register of the instruction prefetch circuit 11, the specific instruction code is output to the instruction decoder 13 via the selector 12 and decoded. By the decoding, the control signal S13 instructing to suspend the operation of the logical operation circuit 14
is output to the logical operation circuit 14, and the operation of the logical operation circuit 14 is interrupted. Next, under the control of the control circuit 28 of the program development support device 4, the data stored in a predetermined register in the logical operation circuit 14 of the microcomputer 2 is transferred via the communication cable 32 to the program development support device. 4 is output to the monitor 26 and displayed. The program developer checks whether or not the logical operation circuit 14 is performing a desired operation in accordance with the control program stored in the memory 25 while watching the data displayed on the monitor 26. Can be determined.

[0012]

The microcomputer 2 and the program development support device 4 shown in FIG.
Then, the program development support device 4 includes a specific instruction code memory 23. Therefore, the address match detection circuit 22 detects a match between the address indicated by the program counter 15 and the jamming address stored in the jamming address memory 21, and then supplies the specific instruction code to the instruction prefetch circuit 11 and the selector 12. By the time, the communication cable 30 and the data bus 16
It is necessary to transmit a specific instruction code via the PC. here,
Normally, various circuits are connected to the data bus 16, and depending on a use state, a load of data transmission increases, and transmission of a specific instruction code via the data bus 16 may be delayed. In this case, the time lag from when the address match is detected by the address match detection circuit 22 to when the processing corresponding to the specific instruction code is executed in the logical operation circuit 14 becomes large, and at the timing expected by the developer. There is a problem that the specific instruction code cannot be executed and the operation of the control program cannot be accurately grasped.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and enables a program-based arithmetic processing device such as a microcomputer to execute a specific instruction code at a desired timing. It is an object of the present invention to provide a program development support device system, a program-based arithmetic processing device, and a program development support device that enable accurate grasp.

[0014]

In order to solve the above-mentioned problems of the prior art and achieve the above object, a program development support system according to the present invention comprises a program-type arithmetic processing device and a program development support device. A program development support system connected via a communication cable for use in developing a control program for controlling the programmable arithmetic processing device, wherein the program development support device is an operation check target in a development stage A first control program storage circuit for storing a control program, and determining whether an address of the control program being executed by the programmed arithmetic processing device matches a predetermined address. When it is determined, the first instruction code used for confirming the operation of the control program is replaced with the program-type operation. An address match detection circuit that outputs an execution instruction signal instructing execution by the processing device to the programmed arithmetic processing device via a second communication line; and the control program executed by the programmed arithmetic processing device. And a control circuit for reading out a second instruction code of the control program from the first control program storage circuit based on the first address and outputting the second instruction code to the programmable arithmetic processing device via a first communication line. Further, the program-type arithmetic processing device, at the stage of developing a signal transmission line for transmitting an instruction code and the control program,
The execution instruction signal input via the second communication line is
Selecting the first instruction code when instructing to execute the first instruction code, and selecting the signal transmission line when not instructing to execute the first instruction code; A selection circuit that selects a second instruction code of the control program input through the first communication line that transmits the instruction code, an execution circuit that executes a process corresponding to the selected instruction code, After the control program has been developed, a second memory for storing the developed control program
And a control program storage circuit.

In the program development support system of the present invention, the control circuit of the program development support device stores the development program in the development stage from the first control program storage circuit based on the address of the control program being executed by the programmable arithmetic processing device. A second instruction code of the control program is read, and the read instruction code is output to the programmed arithmetic processing device via a first communication line. Then, in the programmed arithmetic processing device, the second instruction code input through the first communication line and transmitting the signal transmission line is selected by the selection circuit, and is executed by the execution circuit.

In the address match detection circuit of the program development support device, when it is determined that the address of the control program being executed by the programmed arithmetic processing device matches a predetermined address,
An execution instruction signal for instructing execution of a first instruction code is output from the address coincidence detection circuit to the programmed arithmetic processing unit. Then, in the programmed arithmetic processing device, the first instruction code is selected in the selection circuit, and the selected first instruction code is executed in the execution circuit. Then, for example, the operation of the execution circuit is monitored by a developer, and it is determined whether or not the programmed arithmetic processing device is performing a desired operation according to the control program. Based on the determination result, the control program Modified as necessary. When the control program is finally completed, the completed control program is stored in the second control program storage circuit of the programmable arithmetic processing device.

Further, a program-type arithmetic processing device according to the present invention is a program-type arithmetic processing device for performing processing based on a control program, and has developed a signal transmission line for transmitting an instruction code and the control program. In the step, when the execution instruction signal input from the outside indicates that the first instruction code used for confirming the operation of the control program is to be executed, the first instruction code is selected;
A selection circuit for selecting a second instruction code of an externally input control program, which is transmitted from the outside and transmits the signal transmission line, when not instructing to execute the first instruction code; And an execution circuit for executing a process according to the selected instruction code, and a control program storage circuit for storing the developed control program after the control program has been developed.

In the program type arithmetic processing device of the present invention,
For example, at the stage of developing the control program, input the execution instruction signal output from the program development support device,
In the selection circuit, when the input execution instruction signal indicates that the first instruction code is to be executed, the first instruction code is selected and the first instruction code is executed. Is not specified, the second instruction code input from the program development support apparatus transmitting the signal transmission line is selected. And
In the execution circuit, processing according to the selected instruction code is executed. Then, for example, the operation of the execution circuit is monitored by a developer, and it is determined whether or not the programmed arithmetic processing device is performing a desired operation according to the control program. Based on the determination result, the control program Modified as necessary. When the control program is finally completed, the completed control program is stored in the control program storage circuit of the programmable arithmetic processing device.

Preferably, the programmed arithmetic processing device of the present invention has an external terminal for inputting the execution instruction signal, separately from the external terminal for inputting the second instruction code. That is, the execution instruction signal is not transmitted via the signal transmission line in the program-type arithmetic processing device, but is output directly to the selection circuit.

Further, the program development support device of the present invention is a program development support device used for confirming the operation of a control program executed by a program type arithmetic processing unit, and is an operation confirmation target in a development stage. A control program storage circuit for storing a control program, and determining whether an address of the control program being executed by the programmed arithmetic processing device matches a predetermined address, and determining that the address matches. An address match detection circuit that outputs to the programmed arithmetic processing device an execution instruction signal for instructing the programmed arithmetic processing device to execute a first instruction code used for checking the operation of the control program; The control is executed based on the address of the control program executed by the programmed arithmetic processing unit. And a control circuit for outputting the programmed processing unit from the program memory circuit reads out the second instruction code of the control program.

The program development support device of the present invention is connected to a program-type arithmetic processing device during operation. Then, the control circuit reads the second instruction code of the control program in the development stage from the control program storage circuit based on the address of the control program being executed by the programmable arithmetic processing device, and reads the second instruction code. The issued second instruction code is output to the programmed arithmetic processing device. Further, an address of the control program executed by the programmed arithmetic processing device is input to an address match detection circuit, and the address match detection circuit compares the address with a predetermined address to determine whether or not the address matches. You. As a result, when it is determined that they match, the execution instruction signal for instructing the programmed arithmetic processing unit to execute a first instruction code used for operation confirmation from the address match detection circuit. Is output.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A program development support system according to an embodiment of the present invention will be described below. First Embodiment FIG. 1 shows a program development support system 51 according to the first embodiment .
FIG. As shown in FIG. 1, the program development support system 51 includes a ROM of a microcomputer 52.
At the stage of developing the control program stored in the microcomputer 10, the microcomputer 52 is connected via the communication cables 30 to 33.
And the program development support device 54 are detachably connected.

[0023] That is, the microcomputer 52 includes an external terminal 30 ₁ connected to the communication cable 30,
An external terminal 31 ₁ connected to the communication cable 31, an external terminal 32 ₁ connected to the communication cable 32, and the external terminal 33 ₁ connected to the communication cable 33 is provided. The program development supporting apparatus 54, an external terminal 30 ₂ connected to the communication cable 30, an external terminal 31 ₂ connected to the communication cable 31, the communication cable 32
An external terminal 32 ₂ connected, and 33 ₂ connected to the communication cable 33 is provided with. The communication cables 30 and 33 shown in FIG. 1 correspond to the first communication line and the second communication line of the program development support system of the present invention, respectively. Further, the microcomputer 52 corresponds to the programmed arithmetic processing device of the present invention.

[Microcomputer 52] As shown in FIG. 1, the microcomputer 52 comprises a ROM 10, an instruction prefetch circuit 11, a selector 12, an instruction decoder 13, a logical operation circuit 14, a program counter 15, a data bus 16, a selector 60, 61 and a specific instruction code memory 62 are incorporated in a single integrated circuit (chip). Here, the ROM 10, the instruction prefetch circuit 11, the selector 12, the instruction decoder 13, the logical operation circuit 14, the program counter 15, and the data bus 16 are the same as those of the microcomputer 2 described with reference to FIG. Is the same. The microcomputer 52 is, for example, a video camera or a C
This is a simple computer that is built in a D player or the like and does not have advanced functions such as a debug function.

The selectors 60 and 61 correspond to the selection circuit of the present invention, and the selectors 60 and 61 correspond to the second selection circuit and the first selection circuit, respectively. The instruction decoder 13 and the logical operation circuit 14 correspond to the execution circuit of the present invention, and the data bus 16 corresponds to the signal transmission line of the present invention. Further, the specific instruction code memory 62 corresponds to the instruction code storage circuit of the present invention. Further, the ROM 10 corresponds to a second control program storage circuit of the microcomputer of the present invention.

The ROM 10 stores a control program for the microcomputer 52 developed using the program development support device 54 at the time of shipment.

The specific instruction code memory 62 stores, for example, a specific instruction code (first instruction code of the present invention) for instructing to suspend the operation of the logical operation circuit 14. The specific instruction code is a logical operation circuit 14
The operation necessary for debugging the control program, other than the one indicating that the operation of
It is possible to use various instruction codes that are effective to cause the second instruction code to be executed.

The selector 61 receives the instruction code from the data bus 16 (the second instruction code of the present invention) inputted to the first input terminal and the specific instruction code memory 62 inputted to the second input terminal. One of the read specific instruction codes is selected according to the jamming request signal S72, and the selected instruction code is stored in the instruction prefetch circuit 1.
Output to 1. Specifically, the jamming request signal S72
Is a logical value “1”, that is, when the address match detection circuit 22 has not detected an address match,
Is output to the instruction prefetch circuit 11, and when the jamming request signal S72 has the logical value "0", that is, when the address match detection circuit 22 detects the match of the address, the second Output to the instruction prefetch circuit 11.

The selector 60 determines whether the instruction code from the data bus 16 input to the first input terminal or the specific instruction code read from the specific instruction code memory 62 input to the second input terminal. One of them is selected according to the jamming request signal S72, and the selected instruction code is output to the second input terminal of the selector 12. In particular,
When the jamming request signal S72 has the logical value "1", the instruction code input to the first input terminal is output to the second input terminal of the selector 12, and when the jamming request signal S72 has the logical value "0". Then, the specific instruction code input to the second input terminal is output to the second input terminal of the selector 12.

The instruction prefetch circuit 11 includes, for example, a plurality of prefetch registers. The instruction prefetch circuit 11 stores the instruction code input from the selector 61 in the prefetch register, and then stores the instruction code in the first in first out (FIFO) system. Output to the input terminal.

When the selector signal S40 has the logical value "1", the selector 12 outputs the instruction code input to the first input terminal to the instruction decoder 13, and outputs the selector signal S4
When 0 is a logical value “0”, the instruction code input to the second input terminal is output to the instruction decoder 13. The selector signal S40 is, for example, generated in the instruction prefetch circuit 11, and becomes a logical value “0” when the instruction code is not stored in the prefetch register of the instruction prefetch circuit 11, for example. It is used to directly output the specific instruction code stored in the specific instruction code memory 62 to the instruction decoder 13 without passing through the instruction prefetch circuit 11.

The instruction decoder 13 decodes the instruction code input from the selector 12, generates a control signal S13a for controlling the logical operation circuit 14 according to the decoding result, and sends the control signal S13a to the logical operation circuit 14. Output to control the logical operation circuit 14. The instruction decoder 13 outputs an increment signal S13b to the program counter 15 every time the instruction code is decoded.

The logical operation circuit 14 performs an operation using necessary data based on the control signal S13a. At this time, the intermediate result and the final result of the operation in the logical operation circuit 14 are temporarily stored in a register in the logical operation circuit 14.

The program counter 15 indicates an address in the memory 25 when connected to the program development support device 54, and indicates an address in the ROM 10 when the program development support device 54 is not connected. Further, the program counter 15 increases the value of the indicated address by a predetermined number based on the increment signal S13b.

[Program Development Support Apparatus 54] As shown in FIG. 1, the program development support apparatus 54 has a jamming address memory 21, an address coincidence detection circuit 22, a memory 25, a monitor 26, an input unit 27, and a control circuit 70. . The memory 25 corresponds to the second control program storage circuit of the present invention.

The memory 25 inputs and stores the control program under development via the input unit 27. After the development, the control program of R
This is stored in the OM 10. The control program under development stored in the memory 25 may be created by the developer on the program development support device 54 by operating the keyboard of the input unit 27, or may be created by using another computer. You may.

The jamming address memory 21 stores, via the input unit 27, a jamming address, which is an address indicated by the program counter 15 when the address coincidence detection circuit 22 outputs the jamming request signal 72, via the input unit 27. The jamming request signal S72 corresponds to the execution instruction signal of the present invention.

The address coincidence detecting circuit 22 compares the address indicated by the program counter 15 input via the communication cable 31 with the jamming address stored in the jamming address memory 21. A jamming request signal S72 indicating "1" and indicating a logical value "0" when they match is generated, and the jamming request signal S72 is transmitted to the selectors 60 and 6 of the microcomputer 52 via the communication cable 33.
Output to 1.

The control circuit 70 generates a control signal for comprehensively managing the processing in the program development support device 54 and outputs the control signal to each component in the program development support device 54 as needed.

The monitor 26 inputs data stored in the register of the logical operation circuit 14 via the communication cable 32 in response to a control signal from the control circuit 70, and displays the input data.

The microcomputer 5 shown in FIG.
ROM1 using the program 2 and the program development support device 54
The operation at the time of debugging performed when developing a control program to be stored in 0 will be described. In the following description, when the selector signal S40 has the logical value “1”,
That is, the operation when the instruction code from the instruction prefetch circuit 11 is output to the instruction decoder 13 in the selector 12 is illustrated.

First, the ROM of the microcomputer 52
At the stage of developing a control program to be stored in the memory 10, for example, when debugging a control program being developed, the microcomputer 52 and the program development support device 54 are interconnected via the communication cables 30 to 33. Is done.

The control program under development is stored in the memory 2 via the input unit 27 of the program development support device 54.
5 is stored. Further, the jamming address is stored in the jamming address memory 21 via the input unit 27. In the initial state, the jamming request signal S72 output from the address match detection circuit 22 indicates a logical value “1”, that is, a mismatch of addresses.

The instruction code of the control program read from the address on the memory 25 indicated by the program counter 15 of the microcomputer 52 is:
Selector 24, communication cable 30 and data bus 16
Is output to the first input terminal of the selector 61 of the microcomputer 52 via the. In the selector 61, the instruction code input from the data bus 16 is output to the instruction prefetch circuit 11 based on the jamming request signal S72 having the logical value “1”.

The instruction code is stored in the prefetch register of the instruction prefetch circuit 11 and then output to the instruction decoder 13 via the selector 12 and decoded by the instruction decoder 13 to generate a control signal S13a corresponding to the result of the decoding. Output to the logical operation circuit 14. The logical operation circuit 14 performs an operation using necessary data based on the control signal S13a. At this time, the intermediate result and the final result of the operation in the logical operation circuit 14 are temporarily stored in a register in the logical operation circuit 14.

When the instruction decoder 13 performs decoding, the address indicated by the program counter 15 is incremented by a predetermined number, and the incremented address is transmitted via the communication cable 31.
It is output to the memory 25 of the program development support device 54. Then, the instruction code of the incremented address of the program counter 15 is read from the memory 25, and the above-described processing is repeated.

Thereafter, when the address match detection circuit 22 detects that the address indicated by the program counter 15 and the jamming address stored in the jamming address memory 21 match, the address match detection circuit 22 outputs the same to the selector 61. The 1-bit jamming request signal S72 is switched from, for example, a logical value “1” to “0”. Thus, in the microcomputer 52, the specific instruction code stored in the specific instruction code memory 62 is output to the instruction prefetch circuit 11 via the selector 61.

After the specific instruction code is stored in the prefetch register of the instruction prefetch circuit 11, the specific instruction code is output to the instruction decoder 13 via the selector 12 and decoded. By the decoding, the control signal S13 instructing to suspend the operation of the logical operation circuit 14
is output to the logical operation circuit 14, and the operation of the logical operation circuit 14 is interrupted. Next, under the control of the control circuit 70 of the program development support device 54, the data stored in a predetermined register in the logical operation circuit 14 of the microcomputer 52 is transferred via the communication cable 32 to the program development support device. The data is output to the monitor 26 and displayed. The program developer determines whether or not the microcomputer 52 is performing a desired operation based on the control program stored in the memory 25 while looking at the data displayed on the monitor 26, and based on the determination result, It can be determined whether or not a bug exists in the control program under development stored in the memory 25.

Hereinafter, the microcomputer 52 after shipment will be described.
Will be described. When the development of the control program described above is completed, the ROM 1
After storing the developed control program at 0, the microcomputer 52 is shipped. At this time, the level of the terminal to which the jamming request signal S72 of the selectors 60 and 61 is input is fixed to the logical value "1", and the selectors 60 and 61 are set so as to always output the instruction code from the data bus 16. .

Then, in the microcomputer 52,
ROM 1 pointed to by program counter 15
Instruction codes are sequentially read from the address in 0 and output to the selector 61 via the data bus 16. Next, when the selector signal S40 has the logical value “1”, the instruction code is output to the instruction decoder 13 via the instruction prefetch circuit 11 and the selector 12, and is decoded. Then, the logical operation circuit 14 operates based on the control signal S13a from the instruction decoder 13.

In the operation of the microcomputer 52 and the program development support device 54 described above, the case where the selector signal S40 has the logical value "1" has been exemplified. However, when the selector signal S40 has the logical value "0", Based on the jamming request signal S72, the selector 60 sets the data bus 16
And the specific instruction code from the specific instruction code memory 62 is selected, and the selected instruction code is transmitted to the instruction decoder 13 via the selector 12.
The operation is the same as described above, except that

As described above, according to the program development support system 51, the R of the microcomputer 52
At the time of the debugging operation at the development stage of the control program stored in the OM 10, the jamming request signal S72 is transmitted from the program development support device 54 to the microcomputer 52 through the communication cable 33, and the microcomputer 52
The specific instruction code stored in the specific instruction code memory 62 is read out based on the jamming request signal S72 and output to the selectors 60 and 61.

As described above, the jamming request signal S72
To the dedicated communication cable 3 without passing through the data bus 16.
3, the selector 60 of the microcomputer 52
4 are directly output to the selectors 60 and 61, and the time from when the address match detection circuit 22 of the program development support device 54 detects the address match to when the jamming request signal S72 is input to the selectors 60 and 61 is shown in FIG. It can be shortened on the order of nanoseconds compared to conventional systems. Further, since the specific instruction code memory 62 is incorporated in the chip of the microcomputer 52, the specific instruction code can be read from the specific instruction code memory 62 to the selectors 60 and 61 at high speed. As a result, FIG.
According to the program development support system 51 shown in FIG. 4, the time from when the address match is detected by the address match detection circuit 22 until the microcomputer 52 executes the specific instruction code is compared with the conventional case shown in FIG. Therefore, it can be shortened on the order of several nanoseconds. As a result, the logic operation circuit 14 of the microcomputer 52 is not affected by the load on the data bus 16 and at the timing desired by the developer.
Can be stopped and the operation of the control program under development can be checked.

Further, according to the program development support device 54, compared to the program development support device 4 shown in FIG. 4, the specific instruction code memory 23 and the selector 24 are not provided, so that the size and the price can be reduced. .

Second Embodiment FIG. 2 shows a program development support system 81 of this embodiment .
FIG. As shown in FIG. 2, the program development support system 81 includes a ROM
At the stage of developing a control program stored in the microcomputer 10, the microcomputer 82 is connected via the communication cables 30 to 33.
And the program development support device 54 are detachably connected. 2, the program development support device 54 is the same as the program development support device 54 of the first embodiment described above with reference to FIG.

Hereinafter, the microcomputer 82 will be described in detail. As shown in FIG. 2, the ROM 10, the selector 12, the instruction decoder 13, the logical operation circuit 14, the program counter 15, the data bus 16, and the instruction prefetch circuit 80 are incorporated in a single integrated circuit (chip). . The instruction prefetch circuit 80 corresponds to the selection circuit of the present invention. ROM 1 shown in FIG.
0, selector 12, instruction decoder 13, logical operation circuit 1
4. The program counter 15 and the data bus 16
The same reference numerals as in FIG. 1 denote the same components as those described in the first embodiment. That is, the microcomputer 82 has a configuration in which the selectors 60 and 61 and the specific instruction code memory 62 are removed from the microcomputer 52 shown in FIG. 1, and the instruction prefetch circuit 11 is replaced with an instruction prefetch circuit 80.

Hereinafter, the instruction prefetch circuit 80 will be described in detail. FIG. 3 is a configuration diagram of the instruction prefetch circuit 80. As shown in FIG. 3, the instruction prefetch circuit 80 includes prefetch registers 85 ₁ , 85 ₂ , 85
₃ , 85 ₄ , a control circuit 86 and a specific instruction code setting circuit 87. Prefetch registers 85 _{1 to} 85 ₄
Is based on the control from the control circuit 86,
st In First Out) Functions as memory. That is, sequentially writes the instruction code input from the data bus 16 shown in FIG. 2 in the pre-fetch register 85 _{1-85 4,}
The written instruction codes are read out in the order of writing and output to the first input terminal of the selector 12. Further, the prefetch registers 85 _{1 to} 85 ₄ respectively output the specific instruction code set signal S8 from the specific instruction code setting circuit 87.
If you enter 7 ₁ ~S87 _4, replacing the stored contents to a specific opcode.

The control circuit 86 controls the prefetch register 8
5 _1-85 including control of the write and read operations of the instruction code with respect to _2, carried out overall control of the instruction prefetch circuit 80.

The specific instruction code setting circuit 87 inputs the jamming request signal S72 from the program development support device 54 via the communication cable 33, and the jamming request signal S72 switches from the logical value “1” to “0”. when the, the prefetch register 85 _{1-85 4} instructed by the control circuit 86, a specific instruction code set signal S87
And outputs a _{1 ~S87 4.} The control circuit 86 is, for example, one of the prefetch registers predetermined one of the prefetch registers 85 ₁ to 85 _4, which specifies the output of the specific instruction code set signal.

The microcomputer 8 shown in FIG.
2 and the operation of the program development support device 54 at the time of debugging in the development stage will be described. In the following description, when the selector signal S40 has the logical value “1”, that is, in the selector 12, the instruction prefetch circuit 11
The operation when the instruction code from is output to the instruction decoder 13 is illustrated.

First, the ROM of the microcomputer 82
At the stage of developing a control program to be stored in the memory 10, for example, when performing a debugging process of the control program under development, the microcomputer 82 and the program development support device 54 are interconnected via the communication cables 30 to 33. Is done.

The control program under development is stored in the memory 2 via the input unit 27 of the program development support device 54.
5 is stored. Further, a jamming address, which is an address of the program counter 15 for interrupting the processing of the control program in the microcomputer 52 in order to confirm the operation of the control program, is stored in the jamming address memory 21 via the input unit 27. Is done. In the initial state, the jamming request signal S72 output from the address match detection circuit 22 indicates a logical value “1”, that is, a mismatch of addresses.

The instruction code of the control program read from the address on the memory 25 indicated by the program counter 15 of the microcomputer 82 is
Selector 24, communication cable 30 and data bus 16
Are output to the instruction prefetch circuit 80 of the microcomputer 82 and the second input terminal of the selector 12 via the

The instruction code is stored in the prefetch registers 85 _{1 to} 85 _{4 of the} instruction prefetch circuit 80 shown in FIG.
After being read out by the FIFO method,
The signal is output to the instruction decoder 13 via the selector 12, decoded by the instruction decoder 13, and a control signal S 13 a corresponding to the decoding result is output to the logical operation circuit 14. The logical operation circuit 14 performs an operation using necessary data based on the control signal S13a. At this time,
The intermediate result and the final result of the operation in the logical operation circuit 14 are temporarily stored in a register in the logical operation circuit 14.

When decoding is performed in the instruction decoder 13, the address indicated by the program counter 15 is incremented by a predetermined number, and the incremented address is transmitted via the communication cable 31.
It is output to the memory 25 of the program development support device 54. Then, the instruction code of the incremented address of the program counter 15 is read from the memory 25, and the above-described processing is repeated.

Thereafter, when the address match detection circuit 22 detects that the address indicated by the program counter 15 matches the jamming address stored in the jamming address memory 21, the communication cable 3
3, a jamming request signal S72 output from the address coincidence detection circuit 22 to the instruction prefetch circuit 80.
Switches from the logical value “1” to “0”, for example. Thus, in the instruction prefetch circuit 80 of the microcomputer 82 shown in FIG. 3, the specific instruction code set signal S87 ₁ from a specific instruction code setting circuit 87, for example, is output to the prefetch register 85 _1, the stored contents of prefetch register 85 ₁ It is replaced with a specific instruction code.

Then, the specific instruction code stored in the prefetch register 85 ₁
In accordance with the control of O, the signal is output to the instruction decoder 13 via the first input terminal of the selector 12 and decoded. As a result of the decoding, a control signal S13a instructing to suspend the operation of the logical operation circuit 14 is output to the logical operation circuit 14, and the operation of the logical operation circuit 14 is suspended. next,
In response to control from the control circuit 70 of the program development support device 54, the logical operation circuit 1 of the microcomputer 82
4 is output to the monitor 26 of the program development support device 54 via the communication cable 32 and displayed. The program developer determines whether or not the microcomputer 52 is performing a desired operation based on the control program stored in the memory 25 while looking at the data displayed on the monitor 26, and based on the determination result, It can be determined whether or not a bug exists in the control program under development stored in the memory 25.

Hereinafter, the microcomputer 82 after shipment will be described.
Will be described. When the development of the control program described above is completed, the ROM 1
After storing the developed control program at 0, the microcomputer 52 is shipped. At this time, the level of the terminal to which the jamming request signal S72 of the selectors 60 and 61 is input is fixed to the logical value “1”, and the specific instruction code setting circuit 87 outputs the prefetch registers 85 ₁ to 851.
85 ₄ specific instruction code set signal in S87 ₁ ~S87
₄ is not output. Therefore, the prefetch register 8
5 _{1-85 4} under control of the control circuit 86, F
It functions only as an IFO memory.

Then, in the microcomputer 82,
ROM 1 pointed to by program counter 15
Instruction codes are sequentially read from the address in 0 and output to the selector 61 via the data bus 16. Next, when the selector signal S40 has the logical value “1”, the instruction code is output to the instruction decoder 13 via the instruction prefetch circuit 80 and the selector 12, and is decoded. Then, the logical operation circuit 14 operates based on the control signal S13a from the instruction decoder 13.

As described above, according to the program development support system 81, as in the case of the above-described first embodiment, after the address match is detected by the address match detection circuit 22, the microcomputer 82 The time required to execute a specific instruction code can be reduced on the order of several nanoseconds as compared with the conventional case shown in FIG. As a result, the operation of the logical operation circuit 14 of the microcomputer 52 can be stopped at the timing desired by the developer without being affected by the load on the data bus 16, and the operation of the control program under development can be confirmed.

Further, according to the program development support device 54, compared to the program development support device 4 shown in FIG. 4, the specific instruction code memory 23 and the selector 24 are not provided, so that the size and the price can be reduced. .

Further, according to the microcomputer 82 shown in FIG. 2, the instruction prefetch circuit 80 has a more complicated configuration than the instruction prefetch circuit 11 as can be seen from the microcomputer 52 shown in FIG.
Since it is not necessary to provide the selectors 60 and 61 and the specific instruction code memory 62 shown in FIG. 1, the size and cost can be reduced as a whole.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, as shown in FIG. 1, the instruction code from the data bus 16 is output to the instruction decoder 13 via the instruction prefetch circuits 11 and 80, and the instruction code from the data bus 16 is Although the selector 12 is provided so as to be able to select whether to directly output to the prefetch circuits 11 and 80, a configuration may be adopted in which only one of them is performed. For example, when the instruction code from the data bus 16 is always output to the instruction decoder 13 via the instruction prefetch circuit 11, the microcomputer 52 shown in FIG.
And the output from the instruction prefetch circuit 11 is directly input to the instruction decoder 13. When always outputting the instruction code from the data bus 16 directly to the instruction decoder 13, the microcomputer 52 shown in FIG. 1 removes the selectors 12 and 61 and the instruction prefetch circuit 11 and outputs the instruction code from the data bus 16. The instruction code is directly output to the instruction decoder 13.

Similarly, in the case of the microcomputer 82 shown in FIG. 2, the selector 12 is removed and the instruction code or data bus 16 from the instruction prefetch circuit 80 is removed.
May be input to the instruction decoder 13.

Further, in the above-described embodiment, the process of replacing the instruction code with the specific instruction code is performed for all the bits of the instruction code, but the process for replacing one or more bits constituting a part of the instruction code is performed. Only the specific instruction code may be replaced. Further, the bits constituting the instruction code are divided into a plurality of groups, and for each group, based on a jamming request signal corresponding to each group,
Replacement with a specific instruction code may be performed.

Further, in the above-described embodiment, the case where the communication cables 30, 31, 32 and 33 are individually provided has been exemplified. However, all or some of them may be combined into one communication cable.

[0077]

As described above, according to the program development support system of the present invention, the first instruction code used for confirming the operation of the control program to be confirmed is stored in the programmed arithmetic processing unit. It can be executed at the timing. Further, according to the programmed arithmetic processing device of the present invention, the first instruction code can be supplied to the execution circuit in a short time in response to the execution instruction signal input from the outside,
The first instruction code can be executed at a desired timing. Further, according to the program development support device of the present invention, it is possible to execute the first instruction code in the program-based arithmetic processing device instead of outputting the first instruction code to the program-based arithmetic processing device. Since the execution instruction signal for instructing is output, the time from the detection of an address match by the address match detection circuit to the execution of the first instruction code by the programmable arithmetic processing device can be shortened. Can execute the first instruction code at a desired timing. Furthermore, according to the program development support system, the program-based arithmetic processing device, and the program-development support device of the present invention, the first instruction code can be executed at a desired timing by the program-based arithmetic processing device. Can stop the operation of the programmed arithmetic processing device at a desired timing, and can accurately grasp the operation of the control program to be checked.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a microcomputer and a program development support device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a microcomputer and a program development support device according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of an instruction prefetch circuit shown in FIG. 2;

FIG. 4 is a configuration diagram of a conventional microcomputer and a program development support device.

[Explanation of symbols]

10 ROM, 11, 80 instruction prefetch circuit, 1
2, 60, 61 ... selector, 13 ... instruction decoder, 14
... Logic operation circuit, 15 ... Program counter, 21 ... Jamming address memory, 22 ... Address coincidence detection circuit, 25 ... Memory, 26 ... Monitor, 27 ... Input unit, 5
1,81 ... Program development support system, 52,82 ...
Microcomputer, 54: program development support device, 62: specific instruction code memory, 70: control circuit, 8
5 _{1 to} 85 ₄ ... prefetch register, 86 ... control circuit, 87 ... specific instruction code setting circuit

Claims (20)

[Claims] 1. A program development support system used to develop a control program for controlling a programmable arithmetic processing device by connecting the programmable arithmetic processing device and a program development support device via a communication cable, The program development support device includes a first control program storage circuit that stores a control program to be checked for operation in a development stage, and an address of the control program that is being executed by the programmable arithmetic processing device. To determine whether the program-type arithmetic processing unit executes the first instruction code used for confirming the operation of the control program when it is determined that the addresses match with each other. Address match for outputting an instruction signal to the programmed arithmetic processing unit via a second communication line An output circuit, and reads a second instruction code of the control program from the first control program storage circuit based on an address of the control program being executed by the programmed arithmetic processing unit, and reads a first communication line. And a control circuit for outputting to the programmed arithmetic processing device through the control unit. The programmed arithmetic processing device includes: a signal transmission line for transmitting an instruction code; and When the execution instruction signal input via the second communication line indicates that the first instruction code is to be executed, the first instruction code is selected and the first instruction code is executed. When not instructing to select the second instruction code of the control program input through the first communication line transmitting the signal transmission line when the instruction is not given. Program development comprising: a circuit; an execution circuit that executes a process corresponding to the selected instruction code; and a second control program storage circuit that stores the developed control program after the control program is developed. Support system. 2. The program-type arithmetic processing device according to claim 1, wherein the signal transmission line, the selection circuit, the execution circuit, and the second
2. The program development support system according to claim 1, wherein said control program storage circuit is incorporated in an integrated circuit. 3. The program development support system according to claim 1, wherein said program type arithmetic processing unit further comprises an instruction code storage circuit for storing said first instruction code. 4. The first communication line for transmitting the signal transmission line in response to the execution instruction signal when each of the selection circuits of the programmable arithmetic processing device is developing the control program. And a first selection circuit and a second selection circuit for selecting one of the first instruction code and a second instruction code input via the CPU, and the programmed arithmetic processing device. A fetch circuit that stores the instruction code selected by the first selection circuit and outputs the stored instruction code; an instruction code selected by the second selection circuit; and an instruction code output from the fetch circuit. 2. The program development support system according to claim 1, further comprising: a third selection circuit that selects one of the instruction codes and outputs the selected instruction code to the execution circuit. 5. The program-type arithmetic processing device according to claim 1, wherein the selection circuit includes: a register for storing the second instruction code input from the signal transmission line; and a storage content of the register in response to the execution instruction signal. 2. The program development support system according to claim 1, further comprising an instruction code setting circuit for replacing the instruction code with the first instruction code. 6. The program-based arithmetic processing device, wherein the selection circuit reads a plurality of registers for storing the second instruction code input from the signal transmission line, and reads stored contents of the plurality of registers in a writing order. The instruction code setting circuit replaces the storage content of at least one of the plurality of registers with the first instruction code according to the execution instruction signal. 6. The program development support system according to 5. 7. An execution circuit of the programmed arithmetic processing device, comprising: a decode circuit that decodes the selected instruction code to generate a control signal; and a logical operation circuit that operates based on the control signal. Item 2. The program development support system according to Item 1. 8. The program development support system according to claim 7, wherein said first instruction code is an instruction code for instructing to suspend the operation of said logical operation circuit. 9. The program-based arithmetic processing device, wherein the signal transmission line transmits an instruction code of a control program read from the second control program storage circuit after the control program has been developed; 2. The control circuit according to claim 1, wherein the selection circuit of the arithmetic processing unit always selects an instruction code of the control program read from the second control program storage circuit transmitting the signal transmission line after the control program is developed.
The program development support system described in 1. 10. A program-based arithmetic processing unit for performing processing based on a control program, comprising: a signal transmission line for transmitting an instruction code; and an execution instruction signal input from outside during the development of the control program. While instructing to execute a first instruction code used for confirming the operation of the control program, selecting the first instruction code and instructing to execute the first instruction code A selection circuit for selecting a second instruction code of a control program, which is an operation confirmation target input from the outside transmitting the signal transmission line when the signal transmission line is not being transmitted, and a process corresponding to the selected instruction code. A program-type program having an execution circuit to execute, and a control program storage circuit that stores the developed control program after the control program has been developed. Arithmetic processing unit. 11. The programmed arithmetic processing device according to claim 10, further comprising an external terminal for inputting said execution instruction signal, separately from an external terminal for inputting said second instruction code. 12. The programmed arithmetic processing device according to claim 10, further comprising an instruction code storage circuit for storing said first instruction code. 13. The control circuit according to claim 1, wherein said selecting circuit is adapted to, in a stage where said control program is being developed, respond to said execution instruction signal by receiving a second external signal transmitted through said signal transmission line.
And a first selection circuit and a second selection circuit for selecting one of the first instruction code and the first instruction code, and stores the instruction code selected by the first selection circuit. A fetch circuit to be output after the execution, an instruction code selected by the second selection circuit, and an instruction code output from the fetch circuit are selected, and the selected instruction code is executed. 11. The programmed arithmetic processing device according to claim 10, further comprising a third selection circuit for outputting to the circuit. 14. The selection circuit, wherein the register for storing the second instruction code input from the signal transmission line, and replacing the storage content of the register with the first instruction code in response to the execution instruction signal 11. The programmed arithmetic processing device according to claim 10, further comprising an instruction code setting circuit. 15. The semiconductor device further comprising: a plurality of registers for storing the second instruction code input from the signal transmission line; and a control circuit for controlling storage contents of the plurality of registers to be read out in a writing order. 15. The programmed operation processing device according to claim 14, wherein the instruction code setting circuit replaces a storage content of at least one of the plurality of registers with the first instruction code in response to the execution instruction signal. 16. The program according to claim 10, wherein said execution circuit includes: a decoding circuit that decodes said selected instruction code to generate a control signal; and a logical operation circuit that operates based on said control signal. Expression arithmetic processing unit. 17. The programmed arithmetic processing device according to claim 16, wherein said first instruction code is an instruction code for instructing to suspend the operation of said logical operation circuit. 18. The programmed arithmetic processing device according to claim 10, wherein said signal transmission line, said selection circuit, said execution circuit and said control program storage circuit are incorporated in an integrated circuit. 19. A program development support device used to check the operation of a control program executed by a program-type arithmetic processing device, comprising: a control program storage circuit for storing a control program to be checked for operation in a development stage; It is determined whether or not the address of the control program being executed by the programmed arithmetic processing device matches a predetermined address, and when it is determined that the address matches, it is used to confirm the operation of the control program. An address match detection circuit that outputs to the programmed arithmetic processing device an execution instruction signal for instructing the programmed arithmetic processing device to execute the first instruction code, which is executed by the programmed arithmetic processing device The control program is stored in the control program storage circuit based on the address of the control program. Aid device and a control circuit for reading the second instruction code of the ram and outputs to the programmable processor. 20. The program development support device according to claim 19, further comprising an external terminal for outputting the execution instruction signal, in addition to an external terminal for outputting an instruction code read from the control program storage circuit.