ITVA20050007A1 - Circuito di distribuzione di un segnale di prova applicato su un pad di un dispositivo elettronico - Google Patents

Circuito di distribuzione di un segnale di prova applicato su un pad di un dispositivo elettronico

Info

Publication number
ITVA20050007A1
ITVA20050007A1 IT000007A ITVA20050007A ITVA20050007A1 IT VA20050007 A1 ITVA20050007 A1 IT VA20050007A1 IT 000007 A IT000007 A IT 000007A IT VA20050007 A ITVA20050007 A IT VA20050007A IT VA20050007 A1 ITVA20050007 A1 IT VA20050007A1
Authority
IT
Italy
Prior art keywords
pad
electronic device
test signal
signal applied
distribution circuit
Prior art date
Application number
IT000007A
Other languages
English (en)
Inventor
Gatto Nicola Del
Antonio Geraci
Nicola Rosito
Marco Sforzin
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000007A priority Critical patent/ITVA20050007A1/it
Priority to US11/349,596 priority patent/US7750656B2/en
Publication of ITVA20050007A1 publication Critical patent/ITVA20050007A1/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31723—Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT000007A 2005-02-08 2005-02-08 Circuito di distribuzione di un segnale di prova applicato su un pad di un dispositivo elettronico ITVA20050007A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT000007A ITVA20050007A1 (it) 2005-02-08 2005-02-08 Circuito di distribuzione di un segnale di prova applicato su un pad di un dispositivo elettronico
US11/349,596 US7750656B2 (en) 2005-02-08 2006-02-08 Circuit for distributing a test signal applied to a pad of an electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000007A ITVA20050007A1 (it) 2005-02-08 2005-02-08 Circuito di distribuzione di un segnale di prova applicato su un pad di un dispositivo elettronico

Publications (1)

Publication Number Publication Date
ITVA20050007A1 true ITVA20050007A1 (it) 2006-08-09

Family

ID=36933170

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000007A ITVA20050007A1 (it) 2005-02-08 2005-02-08 Circuito di distribuzione di un segnale di prova applicato su un pad di un dispositivo elettronico

Country Status (2)

Country Link
US (1) US7750656B2 (it)
IT (1) ITVA20050007A1 (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9500700B1 (en) * 2013-11-15 2016-11-22 Xilinx, Inc. Circuits for and methods of testing the operation of an input/output port

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6170475A (ja) * 1984-09-14 1986-04-11 Hitachi Ltd 集積回路用入出力共用回路
US4827437A (en) * 1986-09-22 1989-05-02 Vhl Associates, Inc. Auto calibration circuit for VLSI tester
US5311122A (en) * 1991-12-02 1994-05-10 Motorola, Inc. RF test equipment and wire bond interface circuit
KR950001293B1 (ko) * 1992-04-22 1995-02-15 삼성전자주식회사 반도체 메모리칩의 병렬테스트 회로
US5656949A (en) * 1995-12-29 1997-08-12 Cypress Semiconductor Corp. Architecture for FPGAs
US5796266A (en) * 1996-03-18 1998-08-18 Micron Technology, Inc. Circuit and a method for configuring pad connections in an integrated device
US6363505B1 (en) * 1997-11-14 2002-03-26 Altera Corporation Programmable control circuit for grounding unused outputs
JP4201878B2 (ja) * 1998-05-07 2008-12-24 株式会社ルネサステクノロジ 半導体装置及び試験ボード
US6728915B2 (en) * 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
JP2001267511A (ja) * 2000-03-22 2001-09-28 Mitsubishi Electric Corp 半導体集積回路
JP2002303653A (ja) * 2001-01-30 2002-10-18 Hitachi Ltd 半導体集積回路装置
US6433628B1 (en) * 2001-05-17 2002-08-13 Agere Systems Guardian Corp. Wafer testable integrated circuit
JP3798713B2 (ja) * 2002-03-11 2006-07-19 株式会社東芝 半導体集積回路装置及びそのテスト方法
US6825683B1 (en) * 2002-04-18 2004-11-30 Cypress Semiconductor Corporation System and method for testing multiple integrated circuits that are in the same package
JP3898609B2 (ja) * 2002-09-17 2007-03-28 株式会社東芝 半導体集積回路
KR20040101660A (ko) * 2003-05-26 2004-12-03 삼성전자주식회사 테스트용 신호 패스를 가지는 출력 버퍼 회로 및 이에대한 테스트 방법
US6847203B1 (en) * 2003-07-02 2005-01-25 International Business Machines Corporation Applying parametric test patterns for high pin count ASICs on low pin count testers
JP2005072375A (ja) * 2003-08-26 2005-03-17 Renesas Technology Corp 半導体集積回路
JP4610919B2 (ja) * 2004-03-29 2011-01-12 ルネサスエレクトロニクス株式会社 半導体集積回路装置

Also Published As

Publication number Publication date
US7750656B2 (en) 2010-07-06
US20060195735A1 (en) 2006-08-31

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