ITTO20010818A0 - Circuito per elevare a potenza. - Google Patents

Circuito per elevare a potenza.

Info

Publication number
ITTO20010818A0
ITTO20010818A0 IT2001TO000818A ITTO20010818A ITTO20010818A0 IT TO20010818 A0 ITTO20010818 A0 IT TO20010818A0 IT 2001TO000818 A IT2001TO000818 A IT 2001TO000818A IT TO20010818 A ITTO20010818 A IT TO20010818A IT TO20010818 A0 ITTO20010818 A0 IT TO20010818A0
Authority
IT
Italy
Prior art keywords
raise
circuit
power
Prior art date
Application number
IT2001TO000818A
Other languages
English (en)
Inventor
Donato Ettorre
Alfredo Ruscitto
Bruno Melis
Original Assignee
Telecom Italia Lab Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecom Italia Lab Spa filed Critical Telecom Italia Lab Spa
Priority to IT2001TO000818A priority Critical patent/ITTO20010818A1/it
Publication of ITTO20010818A0 publication Critical patent/ITTO20010818A0/it
Priority to JP2003521929A priority patent/JP2005500614A/ja
Priority to CA002457201A priority patent/CA2457201A1/en
Priority to PCT/IT2002/000539 priority patent/WO2003017085A2/en
Priority to EP02775203A priority patent/EP1423785A2/en
Priority to KR10-2004-7002286A priority patent/KR20040036911A/ko
Priority to CNA028161173A priority patent/CN1543600A/zh
Priority to US10/487,106 priority patent/US20040181566A1/en
Publication of ITTO20010818A1 publication Critical patent/ITTO20010818A1/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/552—Powers or roots, e.g. Pythagorean sums
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3852—Calculation with most significant digit first
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/552—Indexing scheme relating to groups G06F7/552 - G06F7/5525
    • G06F2207/5523—Calculates a power, e.g. the square, of a number or a function, e.g. polynomials

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
  • Transmitters (AREA)
  • Power Sources (AREA)
  • Rear-View Mirror Devices That Are Mounted On The Exterior Of The Vehicle (AREA)
  • Illuminated Signs And Luminous Advertising (AREA)
  • Fluid-Pressure Circuits (AREA)
IT2001TO000818A 2001-08-17 2001-08-17 Circuito per elevare a potenza. ITTO20010818A1 (it)

Priority Applications (8)

Application Number Priority Date Filing Date Title
IT2001TO000818A ITTO20010818A1 (it) 2001-08-17 2001-08-17 Circuito per elevare a potenza.
JP2003521929A JP2005500614A (ja) 2001-08-17 2002-08-14 累乗回路
CA002457201A CA2457201A1 (en) 2001-08-17 2002-08-14 Power raising circuit
PCT/IT2002/000539 WO2003017085A2 (en) 2001-08-17 2002-08-14 Power raising circuit
EP02775203A EP1423785A2 (en) 2001-08-17 2002-08-14 Power raising circuit
KR10-2004-7002286A KR20040036911A (ko) 2001-08-17 2002-08-14 거듭제곱 올림회로
CNA028161173A CN1543600A (zh) 2001-08-17 2002-08-14 幂乘电路
US10/487,106 US20040181566A1 (en) 2001-08-17 2002-08-14 Power raising circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2001TO000818A ITTO20010818A1 (it) 2001-08-17 2001-08-17 Circuito per elevare a potenza.

Publications (2)

Publication Number Publication Date
ITTO20010818A0 true ITTO20010818A0 (it) 2001-08-17
ITTO20010818A1 ITTO20010818A1 (it) 2003-02-17

Family

ID=11459154

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2001TO000818A ITTO20010818A1 (it) 2001-08-17 2001-08-17 Circuito per elevare a potenza.

Country Status (8)

Country Link
US (1) US20040181566A1 (it)
EP (1) EP1423785A2 (it)
JP (1) JP2005500614A (it)
KR (1) KR20040036911A (it)
CN (1) CN1543600A (it)
CA (1) CA2457201A1 (it)
IT (1) ITTO20010818A1 (it)
WO (1) WO2003017085A2 (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11144316B1 (en) 2018-04-17 2021-10-12 Ali Tasdighi Far Current-mode mixed-signal SRAM based compute-in-memory for low power machine learning
US11016732B1 (en) 2018-04-17 2021-05-25 Ali Tasdighi Far Approximate nonlinear digital data conversion for small size multiply-accumulate in artificial intelligence
US10884705B1 (en) 2018-04-17 2021-01-05 Ali Tasdighi Far Approximate mixed-mode square-accumulate for small area machine learning
US11610104B1 (en) 2019-12-30 2023-03-21 Ali Tasdighi Far Asynchronous analog accelerator for fully connected artificial neural networks
US11615256B1 (en) 2019-12-30 2023-03-28 Ali Tasdighi Far Hybrid accumulation method in multiply-accumulate for machine learning

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3780278A (en) * 1971-03-10 1973-12-18 Du Pont Binary squaring circuit
JPS60175142A (ja) * 1984-02-20 1985-09-09 Fujitsu Ltd デイジタル演算回路
FR2712410B1 (fr) * 1993-11-08 1996-02-09 Sgs Thomson Microelectronics Circuit élévateur au carré de nombres binaires.
US6223198B1 (en) * 1998-08-14 2001-04-24 Advanced Micro Devices, Inc. Method and apparatus for multi-function arithmetic
US6301598B1 (en) * 1998-12-09 2001-10-09 Lsi Logic Corporation Method and apparatus for estimating a square of a number

Also Published As

Publication number Publication date
WO2003017085A2 (en) 2003-02-27
JP2005500614A (ja) 2005-01-06
CN1543600A (zh) 2004-11-03
WO2003017085A3 (en) 2004-04-08
EP1423785A2 (en) 2004-06-02
ITTO20010818A1 (it) 2003-02-17
KR20040036911A (ko) 2004-05-03
CA2457201A1 (en) 2003-02-27
US20040181566A1 (en) 2004-09-16

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