ITTO20010817A0 - Circuito moltiplicatore. - Google Patents

Circuito moltiplicatore.

Info

Publication number
ITTO20010817A0
ITTO20010817A0 IT2001TO000817A ITTO20010817A ITTO20010817A0 IT TO20010817 A0 ITTO20010817 A0 IT TO20010817A0 IT 2001TO000817 A IT2001TO000817 A IT 2001TO000817A IT TO20010817 A ITTO20010817 A IT TO20010817A IT TO20010817 A0 ITTO20010817 A0 IT TO20010817A0
Authority
IT
Italy
Prior art keywords
multiplier circuit
multiplier
circuit
Prior art date
Application number
IT2001TO000817A
Other languages
English (en)
Inventor
Donato Ettorre
Alfredo Ruscitto
Bruno Melis
Original Assignee
Telecom Italia Lab Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecom Italia Lab Spa filed Critical Telecom Italia Lab Spa
Priority to IT2001TO000817A priority Critical patent/ITTO20010817A1/it
Publication of ITTO20010817A0 publication Critical patent/ITTO20010817A0/it
Priority to CA002457199A priority patent/CA2457199A1/en
Priority to CNA028161181A priority patent/CN1545652A/zh
Priority to US10/487,109 priority patent/US20040186871A1/en
Priority to EP02775204A priority patent/EP1417564A2/en
Priority to JP2003521928A priority patent/JP2005500613A/ja
Priority to PCT/IT2002/000540 priority patent/WO2003017084A2/en
Priority to KR10-2004-7002285A priority patent/KR20040036910A/ko
Publication of ITTO20010817A1 publication Critical patent/ITTO20010817A1/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3852—Calculation with most significant digit first

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Processing Of Color Television Signals (AREA)
  • Amplifiers (AREA)
  • Stereo-Broadcasting Methods (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Logic Circuits (AREA)
IT2001TO000817A 2001-08-17 2001-08-17 Circuito moltiplicatore. ITTO20010817A1 (it)

Priority Applications (8)

Application Number Priority Date Filing Date Title
IT2001TO000817A ITTO20010817A1 (it) 2001-08-17 2001-08-17 Circuito moltiplicatore.
CA002457199A CA2457199A1 (en) 2001-08-17 2002-08-14 Multiplier circuit
CNA028161181A CN1545652A (zh) 2001-08-17 2002-08-14 乘法器电路
US10/487,109 US20040186871A1 (en) 2001-08-17 2002-08-14 Multiplier circuit
EP02775204A EP1417564A2 (en) 2001-08-17 2002-08-14 Multiplier circuit
JP2003521928A JP2005500613A (ja) 2001-08-17 2002-08-14 乗算器回路
PCT/IT2002/000540 WO2003017084A2 (en) 2001-08-17 2002-08-14 Multiplier circuit
KR10-2004-7002285A KR20040036910A (ko) 2001-08-17 2002-08-14 곱셈기 회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2001TO000817A ITTO20010817A1 (it) 2001-08-17 2001-08-17 Circuito moltiplicatore.

Publications (2)

Publication Number Publication Date
ITTO20010817A0 true ITTO20010817A0 (it) 2001-08-17
ITTO20010817A1 ITTO20010817A1 (it) 2003-02-17

Family

ID=11459153

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2001TO000817A ITTO20010817A1 (it) 2001-08-17 2001-08-17 Circuito moltiplicatore.

Country Status (8)

Country Link
US (1) US20040186871A1 (it)
EP (1) EP1417564A2 (it)
JP (1) JP2005500613A (it)
KR (1) KR20040036910A (it)
CN (1) CN1545652A (it)
CA (1) CA2457199A1 (it)
IT (1) ITTO20010817A1 (it)
WO (1) WO2003017084A2 (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100823252B1 (ko) * 2002-11-07 2008-04-21 삼성전자주식회사 Ｏｆｄｍ 기반 동기 검출 장치 및 방법
DE102004060185B3 (de) * 2004-12-14 2006-05-18 Infineon Technologies Ag Verfahren und Vorrichtung zur Durchführung einer Multiplikations- oder Divisionsoperation in einer elektronischen Schaltung
US8320235B2 (en) * 2006-02-17 2012-11-27 Advantest (Singapore) Pte Ltd Self-repair system and method for providing resource failure tolerance
CN101866278B (zh) * 2010-06-18 2013-05-15 广东工业大学 一种异步迭代的64位整型乘法器及其计算方法
CN105867876A (zh) * 2016-03-28 2016-08-17 武汉芯泰科技有限公司 一种乘加器、乘加器阵列、数字滤波器及乘加计算方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175142A (ja) * 1984-02-20 1985-09-09 Fujitsu Ltd デイジタル演算回路
US5008850A (en) * 1990-05-25 1991-04-16 Sun Microsystems, Inc. Circuitry for multiplying binary numbers
US5220525A (en) * 1991-11-04 1993-06-15 Motorola, Inc. Recoded iterative multiplier
US5402369A (en) * 1993-07-06 1995-03-28 The 3Do Company Method and apparatus for digital multiplication based on sums and differences of finite sets of powers of two
US5436860A (en) * 1994-05-26 1995-07-25 Motorola, Inc. Combined multiplier/shifter and method therefor
US5844827A (en) * 1996-10-17 1998-12-01 Samsung Electronics Co., Ltd. Arithmetic shifter that performs multiply/divide by two to the nth power for positive and negative N

Also Published As

Publication number Publication date
CA2457199A1 (en) 2003-02-27
EP1417564A2 (en) 2004-05-12
WO2003017084A3 (en) 2003-12-31
WO2003017084A2 (en) 2003-02-27
KR20040036910A (ko) 2004-05-03
US20040186871A1 (en) 2004-09-23
ITTO20010817A1 (it) 2003-02-17
JP2005500613A (ja) 2005-01-06
CN1545652A (zh) 2004-11-10

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