ITTO20000633A0 - Metodo di allineamento di fase di flussi di dati appartenenti a tramea divisione di tempo relativo circuito. - Google Patents

Metodo di allineamento di fase di flussi di dati appartenenti a tramea divisione di tempo relativo circuito.

Info

Publication number
ITTO20000633A0
ITTO20000633A0 IT2000TO000633A ITTO20000633A ITTO20000633A0 IT TO20000633 A0 ITTO20000633 A0 IT TO20000633A0 IT 2000TO000633 A IT2000TO000633 A IT 2000TO000633A IT TO20000633 A ITTO20000633 A IT TO20000633A IT TO20000633 A0 ITTO20000633 A0 IT TO20000633A0
Authority
IT
Italy
Prior art keywords
time division
data streams
relative time
division circuit
phase alignment
Prior art date
Application number
IT2000TO000633A
Other languages
English (en)
Inventor
Luca Razzetti
Giovanni Traverso
Marco Novati
Original Assignee
Cit Alcatel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cit Alcatel filed Critical Cit Alcatel
Priority to IT2000TO000633A priority Critical patent/IT1320459B1/it
Publication of ITTO20000633A0 publication Critical patent/ITTO20000633A0/it
Priority to EP01401565A priority patent/EP1168706B1/en
Priority to DE60138339T priority patent/DE60138339D1/de
Priority to AT01401565T priority patent/ATE429097T1/de
Priority to US09/884,226 priority patent/US20020064175A1/en
Priority to CA002351778A priority patent/CA2351778A1/en
Publication of ITTO20000633A1 publication Critical patent/ITTO20000633A1/it
Application granted granted Critical
Publication of IT1320459B1 publication Critical patent/IT1320459B1/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
IT2000TO000633A 2000-06-27 2000-06-27 Metodo di allineamento di fase di flussi di dati appartenenti a tramea divisione di tempo relativo circuito. IT1320459B1 (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT2000TO000633A IT1320459B1 (it) 2000-06-27 2000-06-27 Metodo di allineamento di fase di flussi di dati appartenenti a tramea divisione di tempo relativo circuito.
EP01401565A EP1168706B1 (en) 2000-06-27 2001-06-15 Method and circuit for aligning data flows in time division frames
DE60138339T DE60138339D1 (de) 2000-06-27 2001-06-15 Verfahren und Schaltung zur Einphasung von Datenströmen in Zeitmultiplex-Rahmen
AT01401565T ATE429097T1 (de) 2000-06-27 2001-06-15 Verfahren und schaltung zur einphasung von datenströmen in zeitmultiplex-rahmen
US09/884,226 US20020064175A1 (en) 2000-06-27 2001-06-20 Method and circuit for aligning data flows in time division frames
CA002351778A CA2351778A1 (en) 2000-06-27 2001-06-26 Method and circuit for aligning data flows in time division frames

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2000TO000633A IT1320459B1 (it) 2000-06-27 2000-06-27 Metodo di allineamento di fase di flussi di dati appartenenti a tramea divisione di tempo relativo circuito.

Publications (3)

Publication Number Publication Date
ITTO20000633A0 true ITTO20000633A0 (it) 2000-06-27
ITTO20000633A1 ITTO20000633A1 (it) 2001-12-27
IT1320459B1 IT1320459B1 (it) 2003-11-26

Family

ID=11457861

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2000TO000633A IT1320459B1 (it) 2000-06-27 2000-06-27 Metodo di allineamento di fase di flussi di dati appartenenti a tramea divisione di tempo relativo circuito.

Country Status (6)

Country Link
US (1) US20020064175A1 (it)
EP (1) EP1168706B1 (it)
AT (1) ATE429097T1 (it)
CA (1) CA2351778A1 (it)
DE (1) DE60138339D1 (it)
IT (1) IT1320459B1 (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7342521B1 (en) * 2006-06-28 2008-03-11 Chrontel, Inc. System and method for multi-channel delay cell based clock and data recovery
US9069042B2 (en) * 2013-11-05 2015-06-30 Freescale Semiconductor, Inc. Efficient apparatus and method for testing digital shadow logic around non-logic design structures
WO2017189796A1 (en) * 2016-04-29 2017-11-02 Megachips Technology America Corporation Data transmission method and data transmission system

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3908084A (en) * 1974-10-07 1975-09-23 Bell Telephone Labor Inc High frequency character receiver
US6570944B2 (en) * 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
FR2479620B1 (fr) * 1980-03-28 1988-01-08 Thomson Csf Dispositif de synchronisation d'informations numeriques transmises par paquets et recepteur comportant un tel dispositif
IT1128766B (it) * 1980-04-04 1986-06-04 Cselt Centro Studi Lab Telecom Procedimento e dispositivo per la sincronizzazione di trama di un segnale di informazione supplementare trasmesso a divisione di livello
GB8609499D0 (en) * 1986-04-18 1986-05-21 Gen Electric Co Plc Digital transmission system
JP2531272B2 (ja) * 1988-08-11 1996-09-04 日本電気株式会社 フレ―ム同期制御方式
US5034967A (en) * 1988-11-14 1991-07-23 Datapoint Corporation Metastable-free digital synchronizer with low phase error
US4980585A (en) * 1989-12-01 1990-12-25 Intel Corporation Method and apparatus for synthesizing digital waveforms
US5544203A (en) * 1993-02-17 1996-08-06 Texas Instruments Incorporated Fine resolution digital delay line with coarse and fine adjustment stages
FR2704376B1 (fr) * 1993-04-22 1995-06-30 Rainard Jean Luc Procédé de récupération d'horloge et de synchronisation pour la réception d'informations transmises par un réseau ATM et dispositif de mise en Óoeuvre du procédé.
US5533072A (en) * 1993-11-12 1996-07-02 International Business Machines Corporation Digital phase alignment and integrated multichannel transceiver employing same
TW250607B (en) * 1994-03-17 1995-07-01 Advanced Micro Devices Inc Precoded waveshaping transmitter for twisted pair which eliminates the need for a filter
IT1273098B (it) * 1994-03-31 1997-07-04 Cselt Centro Studi Lab Telecom Dispositivo per il riallineamento di fase di celle atm in nodi atm ottici
JPH0818414A (ja) * 1994-04-26 1996-01-19 Hitachi Ltd 信号処理用遅延回路
US5822386A (en) * 1995-11-29 1998-10-13 Lucent Technologies Inc. Phase recovery circuit for high speed and high density applications
US5870445A (en) * 1995-12-27 1999-02-09 Raytheon Company Frequency independent clock synchronizer
GB2313001B (en) * 1996-05-07 2000-11-01 Nokia Mobile Phones Ltd Frequency modulation using a phase-locked loop
US5920897A (en) * 1996-08-07 1999-07-06 Seeq Technology, Incorporated Apparatus and method for providing multiple channel clock-data alignment
EP0863640A3 (en) * 1997-03-04 2005-09-21 Texas Instruments Incorporated Improved physical layer interface device
GB2326308B (en) * 1997-06-06 2002-06-26 Nokia Mobile Phones Ltd Method and apparatus for controlling time diversity in telephony
US6289068B1 (en) * 1998-06-22 2001-09-11 Xilinx, Inc. Delay lock loop with clock phase shifter
FR2782430B1 (fr) * 1998-08-13 2004-05-28 Bull Sa Procede et interface d'interconnection mettant en oeuvre des liaisons serie haut-debit
US6711227B1 (en) * 1999-02-05 2004-03-23 Broadcom Corporation Synchronizing method and apparatus
JP2000269423A (ja) * 1999-03-16 2000-09-29 Toshiba Microelectronics Corp 半導体集積回路
US6122335A (en) * 1999-10-01 2000-09-19 Quantum Bridge Communications, Inc. Method and apparatus for fast burst mode data recovery

Also Published As

Publication number Publication date
US20020064175A1 (en) 2002-05-30
ATE429097T1 (de) 2009-05-15
DE60138339D1 (de) 2009-05-28
CA2351778A1 (en) 2001-12-27
ITTO20000633A1 (it) 2001-12-27
EP1168706A2 (en) 2002-01-02
EP1168706B1 (en) 2009-04-15
EP1168706A3 (en) 2005-08-17
IT1320459B1 (it) 2003-11-26

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