DE1139242T1 - Nichtsynchronisierter Multiplexdatentransport über Synchronsysteme - Google Patents

Nichtsynchronisierter Multiplexdatentransport über Synchronsysteme

Info

Publication number
DE1139242T1
DE1139242T1 DE1139242T DE01302952T DE1139242T1 DE 1139242 T1 DE1139242 T1 DE 1139242T1 DE 1139242 T DE1139242 T DE 1139242T DE 01302952 T DE01302952 T DE 01302952T DE 1139242 T1 DE1139242 T1 DE 1139242T1
Authority
DE
Germany
Prior art keywords
unsynchronized
data transport
multiplex data
transport via
via synchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE1139242T
Other languages
English (en)
Inventor
Charles W Selvidge
Kenneth W Crouch
Muralidhar R Kudlugh
Soha M N Hassoun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ikos Systems Inc
Original Assignee
Ikos Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ikos Systems Inc filed Critical Ikos Systems Inc
Publication of DE1139242T1 publication Critical patent/DE1139242T1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Hardware Redundancy (AREA)
  • Information Transfer Systems (AREA)
DE1139242T 2000-03-30 2001-03-29 Nichtsynchronisierter Multiplexdatentransport über Synchronsysteme Pending DE1139242T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/539,463 US6961691B1 (en) 2000-03-30 2000-03-30 Non-synchronized multiplex data transport across synchronous systems

Publications (1)

Publication Number Publication Date
DE1139242T1 true DE1139242T1 (de) 2002-07-04

Family

ID=24151318

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1139242T Pending DE1139242T1 (de) 2000-03-30 2001-03-29 Nichtsynchronisierter Multiplexdatentransport über Synchronsysteme

Country Status (3)

Country Link
US (1) US6961691B1 (de)
EP (1) EP1139242A3 (de)
DE (1) DE1139242T1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7305633B2 (en) * 2001-10-30 2007-12-04 Mentor Graphics Corporation Distributed configuration of integrated circuits in an emulation system
US20040114636A1 (en) * 2002-12-13 2004-06-17 General Instrument Corporation Asynchronous data multiplexer
US7085706B1 (en) * 2003-01-14 2006-08-01 Xilinx, Inc. Systems and methods of utilizing virtual input and output modules in a programmable logic device
FR2854703B1 (fr) * 2003-05-07 2005-06-24 Arteris Dispositif d'emulation d'une ou plusieurs puces de circuits integres
US7363600B1 (en) 2003-10-21 2008-04-22 Xilinx, Inc. Method of simulating bidirectional signals in a modeling system
US8359186B2 (en) * 2006-01-26 2013-01-22 Subbu Ganesan Method for delay immune and accelerated evaluation of digital circuits by compiling asynchronous completion handshaking means
WO2007096376A1 (en) * 2006-02-21 2007-08-30 Mentor Graphics Corporation Communication scheme between programmable sub-cores in an emulation environment
US7890684B2 (en) * 2006-08-31 2011-02-15 Standard Microsystems Corporation Two-cycle return path clocking
US8839179B2 (en) 2010-02-12 2014-09-16 Synopsys Taiwan Co., LTD. Prototype and emulation system for multiple custom prototype boards
US8843861B2 (en) 2012-02-16 2014-09-23 Mentor Graphics Corporation Third party component debugging for integrated circuit design
US9703579B2 (en) 2012-04-27 2017-07-11 Mentor Graphics Corporation Debug environment for a multi user hardware assisted verification system
US8949752B2 (en) * 2012-12-01 2015-02-03 Synopsys, Inc. System and method of emulating multiple custom prototype boards
WO2016049336A1 (en) * 2014-09-26 2016-03-31 Moog Inc. Data visualization and logging system

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3873920A (en) 1973-12-12 1975-03-25 Bell Telephone Labor Inc Variable block length synchronization system
SE457308B (sv) 1987-04-07 1988-12-12 Ericsson Telefon Ab L M Kodningsfoerfarande vid oeverfoering av ett antal oeversamplade datakanaler jaemte anordning foer utfoerande av foerfarandet
US5297181A (en) * 1992-01-17 1994-03-22 Alesis Method and apparatus for providing a digital audio interface protocol
AU2561192A (en) 1992-08-28 1994-03-29 Prabhakar Goel Multichip ic design using tdm
US5596742A (en) * 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5761484A (en) * 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
WO1996013902A1 (en) 1994-11-01 1996-05-09 Virtual Machine Works, Inc. Programmable multiplexing input/output port
US5659716A (en) * 1994-11-23 1997-08-19 Virtual Machine Works, Inc. Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation
US5649176A (en) 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5802348A (en) 1995-12-18 1998-09-01 Virtual Machine Works, Inc. Logic analysis system for logic emulation systems
US5854752A (en) 1996-01-19 1998-12-29 Ikos Systems, Inc. Circuit partitioning technique for use with multiplexed inter-connections
US5943490A (en) * 1997-05-30 1999-08-24 Quickturn Design Systems, Inc. Distributed logic analyzer for use in a hardware logic emulation system
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US6061511A (en) * 1998-06-12 2000-05-09 Ikos Systems, Inc. Reconstruction engine for a hardware circuit emulator
US6836757B1 (en) * 1999-02-19 2004-12-28 Texas Instruments Incorporated Emulation system employing serial test port and alternative data transfer protocol
EP1077562A1 (de) * 1999-08-17 2001-02-21 Siemens Aktiengesellschaft Verfahren zur Synchronisierung von Datenpaketen variabler Länge in einem bit-orientierten Kanal
EP1077532A1 (de) 1999-08-17 2001-02-21 BRITISH TELECOMMUNICATIONS public limited company Spreizspektrum Signalgenerator- und Dekodierer für Einzeitenbandübertragung

Also Published As

Publication number Publication date
US6961691B1 (en) 2005-11-01
EP1139242A3 (de) 2002-07-03
EP1139242A2 (de) 2001-10-04

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