ITRM970430A0 - - Google Patents

Info

Publication number
ITRM970430A0
ITRM970430A0 ITRM970430A ITRM970430A ITRM970430A0 IT RM970430 A0 ITRM970430 A0 IT RM970430A0 IT RM970430 A ITRM970430 A IT RM970430A IT RM970430 A ITRM970430 A IT RM970430A IT RM970430 A0 ITRM970430 A0 IT RM970430A0
Authority
IT
Italy
Application number
ITRM970430A
Other languages
Italian (it)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to IT97RM000430A priority Critical patent/IT1293535B1/it
Publication of ITRM970430A0 publication Critical patent/ITRM970430A0/it
Priority to SG1998001761A priority patent/SG71131A1/en
Priority to US09/115,305 priority patent/US6110781A/en
Priority to EP98305602A priority patent/EP0893820A3/en
Priority to KR1019980028387A priority patent/KR19990013849A/ko
Priority to TW087113375A priority patent/TW480620B/zh
Publication of ITRM970430A1 publication Critical patent/ITRM970430A1/it
Application granted granted Critical
Publication of IT1293535B1 publication Critical patent/IT1293535B1/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Silicon Compounds (AREA)
  • Semiconductor Memories (AREA)
IT97RM000430A 1997-07-14 1997-07-14 Perfezionamento nel procedimento di attacco chimico anisotropo dell'ossido di silicio, in particolare nella fabbricazione di IT1293535B1 (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT97RM000430A IT1293535B1 (it) 1997-07-14 1997-07-14 Perfezionamento nel procedimento di attacco chimico anisotropo dell'ossido di silicio, in particolare nella fabbricazione di
SG1998001761A SG71131A1 (en) 1997-07-14 1998-07-13 Improvement to the anisotropic chemical etching process of silicon oxide in the manufacture of mos transistor flash eprom devices
US09/115,305 US6110781A (en) 1997-07-14 1998-07-14 Anisotropic chemical etching process of silicon oxide in the manufacture of MOS transistor flash EPROM devices
EP98305602A EP0893820A3 (en) 1997-07-14 1998-07-14 Anisotropic chemical etching process of silicon oxide in the manufacture of MOS transistor flash EPROM devices
KR1019980028387A KR19990013849A (ko) 1997-07-14 1998-07-14 Mos 트랜지스터 플래쉬 eprom 디바이스의 제조에서 실리콘 산화물의 이방성 화학 에칭 공정의 개선
TW087113375A TW480620B (en) 1997-07-14 1998-08-14 Improvement to the anisotropic chemical etching process of silicon oxide in the manufacture of MOS transistor flash EPROM devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT97RM000430A IT1293535B1 (it) 1997-07-14 1997-07-14 Perfezionamento nel procedimento di attacco chimico anisotropo dell'ossido di silicio, in particolare nella fabbricazione di

Publications (3)

Publication Number Publication Date
ITRM970430A0 true ITRM970430A0 (en, 2012) 1997-07-14
ITRM970430A1 ITRM970430A1 (it) 1999-01-14
IT1293535B1 IT1293535B1 (it) 1999-03-01

Family

ID=11405175

Family Applications (1)

Application Number Title Priority Date Filing Date
IT97RM000430A IT1293535B1 (it) 1997-07-14 1997-07-14 Perfezionamento nel procedimento di attacco chimico anisotropo dell'ossido di silicio, in particolare nella fabbricazione di

Country Status (6)

Country Link
US (1) US6110781A (en, 2012)
EP (1) EP0893820A3 (en, 2012)
KR (1) KR19990013849A (en, 2012)
IT (1) IT1293535B1 (en, 2012)
SG (1) SG71131A1 (en, 2012)
TW (1) TW480620B (en, 2012)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100607322B1 (ko) * 1999-06-30 2006-07-28 주식회사 하이닉스반도체 플래쉬 이이피롬 셀의 제조 방법
JP4149644B2 (ja) * 2000-08-11 2008-09-10 株式会社東芝 不揮発性半導体記憶装置
KR101024252B1 (ko) * 2003-10-30 2011-03-29 주식회사 하이닉스반도체 반도체소자 제조 방법
US7276755B2 (en) * 2005-05-02 2007-10-02 Advanced Micro Devices, Inc. Integrated circuit and method of manufacture
CN105070718B (zh) * 2015-08-18 2019-01-04 上海华虹宏力半导体制造有限公司 一种降低sonos存储器串联电阻的方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5275972A (en) * 1990-02-19 1994-01-04 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window
US5019879A (en) * 1990-03-15 1991-05-28 Chiu Te Long Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area
TW203148B (en, 2012) * 1991-03-27 1993-04-01 American Telephone & Telegraph
JP3259349B2 (ja) * 1992-06-09 2002-02-25 ソニー株式会社 不揮発性半導体装置及びその製造方法
US5270234A (en) * 1992-10-30 1993-12-14 International Business Machines Corporation Deep submicron transistor fabrication method
JP2982580B2 (ja) * 1993-10-07 1999-11-22 日本電気株式会社 不揮発性半導体装置の製造方法
US5467308A (en) * 1994-04-05 1995-11-14 Motorola Inc. Cross-point eeprom memory array
JP2891205B2 (ja) * 1996-10-21 1999-05-17 日本電気株式会社 半導体集積回路の製造方法
US5766992A (en) * 1997-04-11 1998-06-16 Taiwan Semiconductor Manufacturing Company Ltd. Process for integrating a MOSFET device, using silicon nitride spacers and a self-aligned contact structure, with a capacitor structure

Also Published As

Publication number Publication date
IT1293535B1 (it) 1999-03-01
EP0893820A2 (en) 1999-01-27
TW480620B (en) 2002-03-21
US6110781A (en) 2000-08-29
ITRM970430A1 (it) 1999-01-14
KR19990013849A (ko) 1999-02-25
EP0893820A3 (en) 2003-10-29
SG71131A1 (en) 2000-03-21

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Legal Events

Date Code Title Description
0001 Granted