ITRM20010541A1 - Metodo ed apparecchio per amministrare le proprieta' di inversione inun dispositivo di collaudo di memoria. - Google Patents

Metodo ed apparecchio per amministrare le proprieta' di inversione inun dispositivo di collaudo di memoria.

Info

Publication number
ITRM20010541A1
ITRM20010541A1 IT2001RM000541A ITRM20010541A ITRM20010541A1 IT RM20010541 A1 ITRM20010541 A1 IT RM20010541A1 IT 2001RM000541 A IT2001RM000541 A IT 2001RM000541A IT RM20010541 A ITRM20010541 A IT RM20010541A IT RM20010541 A1 ITRM20010541 A1 IT RM20010541A1
Authority
IT
Italy
Prior art keywords
administer
testing device
memory testing
inversion properties
inversion
Prior art date
Application number
IT2001RM000541A
Other languages
English (en)
Inventor
Alan S Krech Jr
John M Freeseman
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of ITRM20010541A0 publication Critical patent/ITRM20010541A0/it
Publication of ITRM20010541A1 publication Critical patent/ITRM20010541A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
IT2001RM000541A 2000-09-11 2001-09-07 Metodo ed apparecchio per amministrare le proprieta' di inversione inun dispositivo di collaudo di memoria. ITRM20010541A1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/659,198 US6973404B1 (en) 2000-09-11 2000-09-11 Method and apparatus for administering inversion property in a memory tester

Publications (2)

Publication Number Publication Date
ITRM20010541A0 ITRM20010541A0 (it) 2001-09-07
ITRM20010541A1 true ITRM20010541A1 (it) 2003-03-07

Family

ID=24644458

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2001RM000541A ITRM20010541A1 (it) 2000-09-11 2001-09-07 Metodo ed apparecchio per amministrare le proprieta' di inversione inun dispositivo di collaudo di memoria.

Country Status (5)

Country Link
US (1) US6973404B1 (it)
JP (1) JP2002148314A (it)
KR (1) KR100786414B1 (it)
DE (1) DE10144660A1 (it)
IT (1) ITRM20010541A1 (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007058450A (ja) * 2005-08-23 2007-03-08 Freescale Semiconductor Inc 半導体集積回路
JP2009187615A (ja) * 2008-02-05 2009-08-20 Elpida Memory Inc 半導体記憶装置
US8868975B2 (en) * 2011-07-26 2014-10-21 International Business Machines Corporation Testing and operating a multiprocessor chip with processor redundancy
US11733290B2 (en) * 2020-03-31 2023-08-22 Advantest Corporation Flexible sideband support systems and methods

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0724013B2 (ja) * 1986-09-10 1995-03-15 株式会社日立製作所 ベクトルプロセツサ
JP2717712B2 (ja) * 1989-08-18 1998-02-25 三菱電機株式会社 半導体記憶装置
JPH04141900A (ja) * 1990-10-01 1992-05-15 Nec Ic Microcomput Syst Ltd 半導体集積回路
JPH0756892A (ja) * 1993-08-10 1995-03-03 Fujitsu Ltd マスク付きベクトル演算器を持つ計算機
JP3237473B2 (ja) * 1995-06-29 2001-12-10 安藤電気株式会社 マスク制御装置
US5666368A (en) * 1996-01-30 1997-09-09 Sun Microsystems, Inc. System and method for testing the operation of registers in digital electronic systems
US5717701A (en) * 1996-08-13 1998-02-10 International Business Machines Corporation Apparatus and method for testing interconnections between semiconductor devices
KR20000065188A (ko) * 1997-03-04 2000-11-06 요트.게.아. 롤페즈 판독/기록 메모리 및 이를 테스트하는 테스트 회로를 구비하는집적 회로, 및 판독/기록 메모리 테스트 방법
JPH11306798A (ja) * 1998-04-22 1999-11-05 Oki Electric Ind Co Ltd メモリ装置のテスト容易化回路
KR20000046815A (ko) * 1998-12-31 2000-07-25 구자홍 메모리용 테스트 로직회로
US6246971B1 (en) * 1999-01-05 2001-06-12 Lucent Technologies Inc. Testing asynchronous circuits
KR20010084440A (ko) * 2000-02-25 2001-09-06 윤종용 향상된 써큘러 빌트-인 셀프 테스트 회로

Also Published As

Publication number Publication date
ITRM20010541A0 (it) 2001-09-07
US6973404B1 (en) 2005-12-06
JP2002148314A (ja) 2002-05-22
KR100786414B1 (ko) 2007-12-17
DE10144660A1 (de) 2002-06-13
KR20020020860A (ko) 2002-03-16

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