ITMI913303A1 - METODO E SISTEMA PER LA RIDUZIONE DEL JITTER DI UNA STRUTTURA A PLL (PHASE LOKED LOOP) CARATTERIZZATO DA UN RAPPORTO RAZIONALE TRA LE LE FREQUENZE DyINGRESSO E DI USCITA. - Google Patents

METODO E SISTEMA PER LA RIDUZIONE DEL JITTER DI UNA STRUTTURA A PLL (PHASE LOKED LOOP) CARATTERIZZATO DA UN RAPPORTO RAZIONALE TRA LE LE FREQUENZE DyINGRESSO E DI USCITA.

Info

Publication number
ITMI913303A1
ITMI913303A1 IT003303A ITMI913303A ITMI913303A1 IT MI913303 A1 ITMI913303 A1 IT MI913303A1 IT 003303 A IT003303 A IT 003303A IT MI913303 A ITMI913303 A IT MI913303A IT MI913303 A1 ITMI913303 A1 IT MI913303A1
Authority
IT
Italy
Prior art keywords
loked
jitter
loop
reduction
phase
Prior art date
Application number
IT003303A
Other languages
English (en)
Inventor
Claudio Colombo
Luca Ponte
Original Assignee
Alcatel Italia
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Italia filed Critical Alcatel Italia
Priority to ITMI913303A priority Critical patent/IT1252241B/it
Publication of ITMI913303A0 publication Critical patent/ITMI913303A0/it
Priority to AU29811/92A priority patent/AU657820B2/en
Priority to ES92120705T priority patent/ES2112292T3/es
Priority to DE69223220T priority patent/DE69223220T2/de
Priority to EP92120705A priority patent/EP0546466B1/en
Publication of ITMI913303A1 publication Critical patent/ITMI913303A1/it
Application granted granted Critical
Publication of IT1252241B publication Critical patent/IT1252241B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
ITMI913303A 1991-12-10 1991-12-10 Metodo e sistema per la riduzione del jitter di una struttura a pll (phase loked loop) caratterizzato da un rapporto razionale tra le le frequenze d`ingresso e di uscita. IT1252241B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
ITMI913303A IT1252241B (it) 1991-12-10 1991-12-10 Metodo e sistema per la riduzione del jitter di una struttura a pll (phase loked loop) caratterizzato da un rapporto razionale tra le le frequenze d`ingresso e di uscita.
AU29811/92A AU657820B2 (en) 1991-12-10 1992-12-01 Method of reducing jitter in phase-locked loop
ES92120705T ES2112292T3 (es) 1991-12-10 1992-12-04 Metodo y sistema para reducir la fluctuacion de una estructura pll (bucle de enganche de fase) caracterizada por una relacion racional entre frecuencias de entrada y de salida.
DE69223220T DE69223220T2 (de) 1991-12-10 1992-12-04 Verfahren und System zur Phasenjitterreduzierung in einem Phasenregelkreis mit gebrochenem N-Teilerverhältnis
EP92120705A EP0546466B1 (en) 1991-12-10 1992-12-04 Method and system for reducing the jitter of a PLL (Phase Locked Loop) structure characterized by a rational ratio between input and output frequencies

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI913303A IT1252241B (it) 1991-12-10 1991-12-10 Metodo e sistema per la riduzione del jitter di una struttura a pll (phase loked loop) caratterizzato da un rapporto razionale tra le le frequenze d`ingresso e di uscita.

Publications (3)

Publication Number Publication Date
ITMI913303A0 ITMI913303A0 (it) 1991-12-10
ITMI913303A1 true ITMI913303A1 (it) 1993-06-10
IT1252241B IT1252241B (it) 1995-06-05

Family

ID=11361295

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI913303A IT1252241B (it) 1991-12-10 1991-12-10 Metodo e sistema per la riduzione del jitter di una struttura a pll (phase loked loop) caratterizzato da un rapporto razionale tra le le frequenze d`ingresso e di uscita.

Country Status (5)

Country Link
EP (1) EP0546466B1 (it)
AU (1) AU657820B2 (it)
DE (1) DE69223220T2 (it)
ES (1) ES2112292T3 (it)
IT (1) IT1252241B (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011815A (en) * 1997-09-16 2000-01-04 Telefonaktiebolaget Lm Ericsson Compensated ΔΣ controlled phase locked loop modulator
US6047029A (en) * 1997-09-16 2000-04-04 Telefonaktiebolaget Lm Ericsson Post-filtered delta sigma for controlling a phase locked loop modulator
US7282967B2 (en) 2003-10-30 2007-10-16 Avago Technologies General Ip ( Singapore) Pte. Ltd. Fixed frequency clock output having a variable high frequency input clock and an unrelated fixed frequency reference signal

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8907316D0 (en) * 1989-03-31 1989-09-13 Plessey Co Plc Fractional'n'synthesisers
CA2003428C (en) * 1989-11-21 1999-12-14 Thomas Atkin Denning Riley Frequency synthesizer
GB2238434B (en) * 1989-11-22 1994-03-16 Stc Plc Frequency synthesiser
US5055802A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Multiaccumulator sigma-delta fractional-n synthesis

Also Published As

Publication number Publication date
AU2981192A (en) 1993-06-17
AU657820B2 (en) 1995-03-23
ES2112292T3 (es) 1998-04-01
EP0546466A1 (en) 1993-06-16
ITMI913303A0 (it) 1991-12-10
EP0546466B1 (en) 1997-11-19
IT1252241B (it) 1995-06-05
DE69223220T2 (de) 1998-07-09
DE69223220D1 (de) 1998-01-02

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971128