DE69223220T2 - Verfahren und System zur Phasenjitterreduzierung in einem Phasenregelkreis mit gebrochenem N-Teilerverhältnis - Google Patents

Verfahren und System zur Phasenjitterreduzierung in einem Phasenregelkreis mit gebrochenem N-Teilerverhältnis

Info

Publication number
DE69223220T2
DE69223220T2 DE69223220T DE69223220T DE69223220T2 DE 69223220 T2 DE69223220 T2 DE 69223220T2 DE 69223220 T DE69223220 T DE 69223220T DE 69223220 T DE69223220 T DE 69223220T DE 69223220 T2 DE69223220 T2 DE 69223220T2
Authority
DE
Germany
Prior art keywords
phase
broken
locked loop
divider ratio
jitter reduction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69223220T
Other languages
English (en)
Other versions
DE69223220D1 (de
Inventor
Silvio Cucchi
Luca Ponte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent Italia SpA
Original Assignee
Alcatel Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Italia SpA filed Critical Alcatel Italia SpA
Application granted granted Critical
Publication of DE69223220D1 publication Critical patent/DE69223220D1/de
Publication of DE69223220T2 publication Critical patent/DE69223220T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
DE69223220T 1991-12-10 1992-12-04 Verfahren und System zur Phasenjitterreduzierung in einem Phasenregelkreis mit gebrochenem N-Teilerverhältnis Expired - Fee Related DE69223220T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI913303A IT1252241B (it) 1991-12-10 1991-12-10 Metodo e sistema per la riduzione del jitter di una struttura a pll (phase loked loop) caratterizzato da un rapporto razionale tra le le frequenze d`ingresso e di uscita.

Publications (2)

Publication Number Publication Date
DE69223220D1 DE69223220D1 (de) 1998-01-02
DE69223220T2 true DE69223220T2 (de) 1998-07-09

Family

ID=11361295

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69223220T Expired - Fee Related DE69223220T2 (de) 1991-12-10 1992-12-04 Verfahren und System zur Phasenjitterreduzierung in einem Phasenregelkreis mit gebrochenem N-Teilerverhältnis

Country Status (5)

Country Link
EP (1) EP0546466B1 (de)
AU (1) AU657820B2 (de)
DE (1) DE69223220T2 (de)
ES (1) ES2112292T3 (de)
IT (1) IT1252241B (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011815A (en) * 1997-09-16 2000-01-04 Telefonaktiebolaget Lm Ericsson Compensated ΔΣ controlled phase locked loop modulator
US6047029A (en) * 1997-09-16 2000-04-04 Telefonaktiebolaget Lm Ericsson Post-filtered delta sigma for controlling a phase locked loop modulator
US7282967B2 (en) * 2003-10-30 2007-10-16 Avago Technologies General Ip ( Singapore) Pte. Ltd. Fixed frequency clock output having a variable high frequency input clock and an unrelated fixed frequency reference signal

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8907316D0 (en) * 1989-03-31 1989-09-13 Plessey Co Plc Fractional'n'synthesisers
CA2003428C (en) * 1989-11-21 1999-12-14 Thomas Atkin Denning Riley Frequency synthesizer
GB2238434B (en) * 1989-11-22 1994-03-16 Stc Plc Frequency synthesiser
US5055802A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Multiaccumulator sigma-delta fractional-n synthesis

Also Published As

Publication number Publication date
EP0546466A1 (de) 1993-06-16
AU657820B2 (en) 1995-03-23
IT1252241B (it) 1995-06-05
ITMI913303A0 (it) 1991-12-10
ITMI913303A1 (it) 1993-06-10
ES2112292T3 (es) 1998-04-01
DE69223220D1 (de) 1998-01-02
EP0546466B1 (de) 1997-11-19
AU2981192A (en) 1993-06-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee