ITMI20042213A1 - Architettura di bus dati per memoria a semiconduttore - Google Patents

Architettura di bus dati per memoria a semiconduttore

Info

Publication number
ITMI20042213A1
ITMI20042213A1 IT002213A ITMI20042213A ITMI20042213A1 IT MI20042213 A1 ITMI20042213 A1 IT MI20042213A1 IT 002213 A IT002213 A IT 002213A IT MI20042213 A ITMI20042213 A IT MI20042213A IT MI20042213 A1 ITMI20042213 A1 IT MI20042213A1
Authority
IT
Italy
Prior art keywords
semiconductor memory
data bus
bus architecture
architecture
semiconductor
Prior art date
Application number
IT002213A
Other languages
English (en)
Inventor
Luca Crippa
Rino Micheloni
Miriam Sangalli
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT002213A priority Critical patent/ITMI20042213A1/it
Publication of ITMI20042213A1 publication Critical patent/ITMI20042213A1/it
Priority to US11/281,932 priority patent/US7260005B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
IT002213A 2004-11-18 2004-11-18 Architettura di bus dati per memoria a semiconduttore ITMI20042213A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT002213A ITMI20042213A1 (it) 2004-11-18 2004-11-18 Architettura di bus dati per memoria a semiconduttore
US11/281,932 US7260005B2 (en) 2004-11-18 2005-11-17 Data bus architecture for a semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT002213A ITMI20042213A1 (it) 2004-11-18 2004-11-18 Architettura di bus dati per memoria a semiconduttore

Publications (1)

Publication Number Publication Date
ITMI20042213A1 true ITMI20042213A1 (it) 2005-02-18

Family

ID=36611325

Family Applications (1)

Application Number Title Priority Date Filing Date
IT002213A ITMI20042213A1 (it) 2004-11-18 2004-11-18 Architettura di bus dati per memoria a semiconduttore

Country Status (2)

Country Link
US (1) US7260005B2 (it)
IT (1) ITMI20042213A1 (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10984854B1 (en) * 2019-10-01 2021-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device with signal edge sharpener circuitry

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6442089B1 (en) * 1999-12-22 2002-08-27 Intel Corporation Multi-level, low voltage swing sensing scheme for high speed memory design
US6351150B1 (en) * 2000-09-11 2002-02-26 Intel Corporation Low switching activity dynamic driver for high performance interconnects
US6442069B1 (en) * 2000-12-29 2002-08-27 Intel Corporation Differential signal path for high speed data transmission in flash memory
KR100402245B1 (ko) * 2001-09-18 2003-10-17 주식회사 하이닉스반도체 메모리 장치

Also Published As

Publication number Publication date
US7260005B2 (en) 2007-08-21
US20060140033A1 (en) 2006-06-29

Similar Documents

Publication Publication Date Title
GB0714910D0 (en) Memory buffers for merging local data from memory modules
DE602005001354D1 (de) Datenaufzeichnungssystem
EP1748488A4 (en) SEMICONDUCTOR MEMORY
EP1725932A4 (en) DATA ACCESS ARCHITECTURE
DE502005004657D1 (de) Redundantes datenbussystem
DE602005009411D1 (de) Halbleiterspeichervorrichtung
GB2446997B (en) Memory access request arbitration
DE602005006197D1 (de) Halbleiterspeicherbaustein
DE602005017526D1 (de) Speichersteuersystem
DE602005013212D1 (de) Halbleiter-speicherkarte
EP1896951A4 (en) MEMORY PAGES MANAGEMENT
ITMI20070292A1 (it) Utensile rotante con supporto elettronico di dati
GB2433333B (en) Distributed direct memory access provision within a data processing system
DE602005015925D1 (de) Speicherkarte
DE602005008550D1 (de) Halbleiterspeicher
HK1094050A1 (en) Semiconductor device having flash memory
GB0714439D0 (en) A single chip having a magnetoresistive memory
EP1793331A4 (en) MEMORY CARD WITH SEMICONDUCTOR
ITMI20041957A1 (it) Dispositivo di memoria
ITMI20042462A1 (it) Memoria ausiliare
DE602004012987D1 (de) Datenspeichersystem
DE602005007878D1 (de) Halbleiterspeicher
DE602006003509D1 (de) Halbleiterspeicheranordnung
EP1821214A4 (en) NON-VOLATILE STORAGE SYSTEM
DE602004009078D1 (de) Speicherordnung