ITMI20030276A1 - Architettura ottimizzata per un blocco di connessione in gate - Google Patents

Architettura ottimizzata per un blocco di connessione in gate

Info

Publication number
ITMI20030276A1
ITMI20030276A1 IT000276A ITMI20030276A ITMI20030276A1 IT MI20030276 A1 ITMI20030276 A1 IT MI20030276A1 IT 000276 A IT000276 A IT 000276A IT MI20030276 A ITMI20030276 A IT MI20030276A IT MI20030276 A1 ITMI20030276 A1 IT MI20030276A1
Authority
IT
Italy
Prior art keywords
connection block
gate connection
optimized architecture
architecture
optimized
Prior art date
Application number
IT000276A
Other languages
English (en)
Inventor
Fabio Campi
Andrea Cappelli
Luca Ciccarelli
Andrea Lodi
Mario Toma
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000276A priority Critical patent/ITMI20030276A1/it
Priority to US10/778,913 priority patent/US7193437B2/en
Publication of ITMI20030276A1 publication Critical patent/ITMI20030276A1/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
IT000276A 2003-02-14 2003-02-14 Architettura ottimizzata per un blocco di connessione in gate ITMI20030276A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT000276A ITMI20030276A1 (it) 2003-02-14 2003-02-14 Architettura ottimizzata per un blocco di connessione in gate
US10/778,913 US7193437B2 (en) 2003-02-14 2004-02-13 Architecture for a connection block in reconfigurable gate arrays

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000276A ITMI20030276A1 (it) 2003-02-14 2003-02-14 Architettura ottimizzata per un blocco di connessione in gate

Publications (1)

Publication Number Publication Date
ITMI20030276A1 true ITMI20030276A1 (it) 2004-08-15

Family

ID=33398056

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000276A ITMI20030276A1 (it) 2003-02-14 2003-02-14 Architettura ottimizzata per un blocco di connessione in gate

Country Status (2)

Country Link
US (1) US7193437B2 (it)
IT (1) ITMI20030276A1 (it)

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US7146441B1 (en) * 1998-03-16 2006-12-05 Actel Corporation SRAM bus architecture and interconnect to an FPGA
US7129744B2 (en) * 2003-10-23 2006-10-31 Viciciv Technology Programmable interconnect structures
US7167025B1 (en) * 2004-02-14 2007-01-23 Herman Schmit Non-sequentially configurable IC
US7425841B2 (en) * 2004-02-14 2008-09-16 Tabula Inc. Configurable circuits, IC's, and systems
US7330050B2 (en) 2004-11-08 2008-02-12 Tabula, Inc. Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements
US7735035B1 (en) * 2005-06-01 2010-06-08 Cadence Design Systems, Inc. Method and system for creating a boolean model of multi-path and multi-strength signals for verification
US7679401B1 (en) 2005-12-01 2010-03-16 Tabula, Inc. User registers implemented with routing circuits in a configurable IC
CN100346335C (zh) * 2005-12-02 2007-10-31 浙江大学 一种采用异步通信机制的可重构计算单元
EP2597777A3 (en) 2007-03-20 2014-08-20 Tabula, Inc. Configurable IC having a routing fabric with storage elements
WO2009035586A1 (en) 2007-09-06 2009-03-19 Tabula, Inc. Configuration context switcher
US7970979B1 (en) * 2007-09-19 2011-06-28 Agate Logic, Inc. System and method of configurable bus-based dedicated connection circuits
US8131909B1 (en) 2007-09-19 2012-03-06 Agate Logic, Inc. System and method of signal processing engines with programmable logic fabric
WO2010033263A1 (en) 2008-09-17 2010-03-25 Tabula, Inc. Controllable storage elements for an ic
WO2011123151A1 (en) 2010-04-02 2011-10-06 Tabula Inc. System and method for reducing reconfiguration power usage
US8788987B2 (en) 2010-06-23 2014-07-22 Tabula, Inc. Rescaling
US8650514B2 (en) 2010-06-23 2014-02-11 Tabula, Inc. Rescaling
US8760193B2 (en) 2011-07-01 2014-06-24 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
KR20130066267A (ko) * 2011-12-12 2013-06-20 한국전자통신연구원 필드 프로그래머블 게이트 어레이의 스위치 블록 회로
US9203397B1 (en) 2011-12-16 2015-12-01 Altera Corporation Delaying start of user design execution
JP5677339B2 (ja) * 2012-02-17 2015-02-25 株式会社東芝 メモリ回路
JP5665789B2 (ja) 2012-03-28 2015-02-04 株式会社東芝 コンフィギュレーションメモリ
US9490811B2 (en) * 2012-10-04 2016-11-08 Efinix, Inc. Fine grain programmable gate architecture with hybrid logic/routing element and direct-drive routing
US9000801B1 (en) 2013-02-27 2015-04-07 Tabula, Inc. Implementation of related clocks
JP2015026901A (ja) 2013-07-24 2015-02-05 株式会社東芝 リコンフィギュラブル論理回路
JP2015026998A (ja) 2013-07-26 2015-02-05 株式会社東芝 マルチコンテキストコンフィグレーションメモリ
JP2015061238A (ja) 2013-09-19 2015-03-30 株式会社東芝 再構成可能な半導体集積回路および電子機器
JP2015185180A (ja) 2014-03-20 2015-10-22 株式会社東芝 コンフィギュレーションメモリ
JP2016063490A (ja) 2014-09-19 2016-04-25 株式会社東芝 再構成可能な半導体集積回路および電子機器
US9954531B2 (en) * 2015-03-03 2018-04-24 Semiconductor Energy Laboratory Co., Ltd. Electronic device
KR20160108052A (ko) * 2015-03-06 2016-09-19 에스케이하이닉스 주식회사 반도체 소자
US9774317B1 (en) 2016-08-29 2017-09-26 Amazon Technologies, Inc. Bistable-element for random number generation
US11790243B1 (en) * 2022-06-30 2023-10-17 International Business Machines Corporation Ferroelectric field effect transistor for implementation of decision tree

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Publication number Priority date Publication date Assignee Title
JPH01116690A (ja) * 1987-10-30 1989-05-09 Fujitsu Ltd 論理演算回路
US5801551A (en) * 1996-08-01 1998-09-01 Advanced Micro Devices, Inc. Depletion mode pass gates with controlling decoder and negative power supply for a programmable logic device
US5808933A (en) * 1997-03-28 1998-09-15 International Business Machines Corporation Zero-write-cycle memory cell apparatus
US6265895B1 (en) * 1998-01-30 2001-07-24 Altera Corporation Programmable logic device incorporating a memory efficient interconnection device
US6430083B1 (en) * 2000-06-28 2002-08-06 Intel Corporation Register file scheme
US6617912B1 (en) * 2002-06-13 2003-09-09 Xilinx, Inc. Pass gate multiplexer circuit with reduced susceptibility to single event upsets
US7112994B2 (en) * 2002-07-08 2006-09-26 Viciciv Technology Three dimensional integrated circuits
US6768335B1 (en) * 2003-01-30 2004-07-27 Xilinx, Inc. Integrated circuit multiplexer including transistors of more than one oxide thickness
US6804143B1 (en) * 2003-04-02 2004-10-12 Cogent Chipware Inc. Write-assisted SRAM bit cell
US7054217B2 (en) * 2003-09-12 2006-05-30 Sanyo Electric Co. Ltd. Semiconductor memory device

Also Published As

Publication number Publication date
US7193437B2 (en) 2007-03-20
US20040225980A1 (en) 2004-11-11

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