IT969982B - Sistema di indirizzamento perfe zionato per memorie di calcola tori numerici - Google Patents

Sistema di indirizzamento perfe zionato per memorie di calcola tori numerici

Info

Publication number
IT969982B
IT969982B IT31012/72A IT3101272A IT969982B IT 969982 B IT969982 B IT 969982B IT 31012/72 A IT31012/72 A IT 31012/72A IT 3101272 A IT3101272 A IT 3101272A IT 969982 B IT969982 B IT 969982B
Authority
IT
Italy
Prior art keywords
perfect
numerical calculation
addressing system
calculation memories
memories
Prior art date
Application number
IT31012/72A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT969982B publication Critical patent/IT969982B/it

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/415—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Static Random-Access Memory (AREA)
IT31012/72A 1971-12-30 1972-10-27 Sistema di indirizzamento perfe zionato per memorie di calcola tori numerici IT969982B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US21419971A 1971-12-30 1971-12-30

Publications (1)

Publication Number Publication Date
IT969982B true IT969982B (it) 1974-04-10

Family

ID=22798181

Family Applications (1)

Application Number Title Priority Date Filing Date
IT31012/72A IT969982B (it) 1971-12-30 1972-10-27 Sistema di indirizzamento perfe zionato per memorie di calcola tori numerici

Country Status (7)

Country Link
US (1) US3736574A (it)
JP (1) JPS5323982B2 (it)
CA (1) CA958486A (it)
DE (1) DE2256118C3 (it)
FR (1) FR2166226B1 (it)
GB (1) GB1347438A (it)
IT (1) IT969982B (it)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4060795A (en) * 1973-02-23 1977-11-29 Hitachi, Ltd. Scanning system
US3855577A (en) * 1973-06-11 1974-12-17 Texas Instruments Inc Power saving circuit for calculator system
JPS5516333B2 (it) * 1974-03-29 1980-05-01
US3872452A (en) * 1974-04-17 1975-03-18 Ibm Floating addressing system and method
US3922647A (en) * 1974-06-03 1975-11-25 Motorola Inc External exclusive OR type circuit for inverting cell MOS RAM
US3906464A (en) * 1974-06-03 1975-09-16 Motorola Inc External data control preset system for inverting cell random access memory
US3906463A (en) * 1974-06-03 1975-09-16 Motorola Inc MOS memory system
US4007451A (en) * 1975-05-30 1977-02-08 International Business Machines Corporation Method and circuit arrangement for operating a highly integrated monolithic information store
JPS5227229A (en) * 1975-08-25 1977-03-01 Fujitsu Ltd Semiconductor memory
DE2539617B1 (de) * 1975-09-05 1977-02-10 Siemens Ag Schaltungsanordnung aus integrierten digitalbausteinen zur speicherung von digitalen informationswerten
US4156926A (en) * 1976-06-01 1979-05-29 Texas Instruments Incorporated PROM circuit board programmer
US4099070A (en) * 1976-11-26 1978-07-04 Motorola, Inc. Sense-write circuit for random access memory
DE2738187C2 (de) * 1977-08-24 1979-02-15 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung für mehrere auf einem Bipolar-Baustein angeordnete Speicherzellen mit einer Regelschaltung zur Kennlinien-Anpassung der Speicherzellen
DE2739283A1 (de) * 1977-08-31 1979-03-15 Siemens Ag Integrierbare halbleiterspeicherzelle
US4164786A (en) * 1978-04-11 1979-08-14 The Bendix Corporation Apparatus for expanding memory size and direct memory addressing capabilities of digital computer means
US4296467A (en) * 1978-07-03 1981-10-20 Honeywell Information Systems Inc. Rotating chip selection technique and apparatus
FR2443118A1 (fr) * 1978-11-30 1980-06-27 Ibm France Dispositif pour l'alimentation des memoires monolithiques
DE2855866C3 (de) * 1978-12-22 1981-10-29 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren und Schaltungsanordnung zum Betreiben eines integrierten Halbleiterspeichers
JPS5833634B2 (ja) * 1979-02-28 1983-07-21 富士通株式会社 メモリセルアレイの駆動方式
DE2926050C2 (de) * 1979-06-28 1981-10-01 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren und Schaltungsanordnung zum Lesen Und/oder Schreiben eines integrierten Halbleiterspeichers mit Speicherzellen in MTL-Technik
JPS5831673B2 (ja) * 1979-08-22 1983-07-07 富士通株式会社 半導体記憶装置
DE3004565C2 (de) * 1980-02-07 1984-06-14 Siemens AG, 1000 Berlin und 8000 München Integrierte digitale Halbleiterschaltung
JPS56112122A (en) * 1980-02-08 1981-09-04 Fujitsu Ltd Decoder circuit
US4460984A (en) * 1981-12-30 1984-07-17 International Business Machines Corporation Memory array with switchable upper and lower word lines
DE3380678D1 (en) * 1983-05-25 1989-11-09 Ibm Deutschland Semiconductor memory
US4660178A (en) * 1983-09-21 1987-04-21 Inmos Corporation Multistage decoding
US4598390A (en) * 1984-06-25 1986-07-01 International Business Machines Corporation Random access memory RAM employing complementary transistor switch (CTS) memory cells
US4596002A (en) * 1984-06-25 1986-06-17 International Business Machines Corporation Random access memory RAM employing complementary transistor switch (CTS) memory cells
US4578779A (en) * 1984-06-25 1986-03-25 International Business Machines Corporation Voltage mode operation scheme for bipolar arrays
US4810962A (en) * 1987-10-23 1989-03-07 International Business Machines Corporation Voltage regulator capable of sinking current
US5335336A (en) * 1988-03-28 1994-08-02 Hitachi, Ltd. Memory device having refresh mode returning previous page address for resumed page mode
US5724540A (en) * 1988-03-28 1998-03-03 Hitachi, Ltd. Memory system having a column address counter and a page address counter
JPH02246099A (ja) * 1989-03-20 1990-10-01 Hitachi Ltd 大規模半導体集積回路装置とその欠陥救済法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3317902A (en) * 1964-04-06 1967-05-02 Ibm Address selection control apparatus
US3599182A (en) * 1969-01-15 1971-08-10 Ibm Means for reducing power consumption in a memory device

Also Published As

Publication number Publication date
JPS4878837A (it) 1973-10-23
CA958486A (en) 1974-11-26
DE2256118C3 (de) 1981-11-12
DE2256118A1 (de) 1973-07-12
US3736574A (en) 1973-05-29
JPS5323982B2 (it) 1978-07-18
DE2256118B2 (de) 1981-03-26
GB1347438A (en) 1974-02-27
FR2166226B1 (it) 1976-08-27
FR2166226A1 (it) 1973-08-10

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