IT964201B - Circuito integrabile allo stato solido atto a controllare ovvero a regolare la tensione di soglia effettiva di un transistore ad ef fetto di campo ad isolamento di porta - Google Patents

Circuito integrabile allo stato solido atto a controllare ovvero a regolare la tensione di soglia effettiva di un transistore ad ef fetto di campo ad isolamento di porta

Info

Publication number
IT964201B
IT964201B IT28438/72A IT2843872A IT964201B IT 964201 B IT964201 B IT 964201B IT 28438/72 A IT28438/72 A IT 28438/72A IT 2843872 A IT2843872 A IT 2843872A IT 964201 B IT964201 B IT 964201B
Authority
IT
Italy
Prior art keywords
field
regulate
threshold voltage
solid state
control
Prior art date
Application number
IT28438/72A
Other languages
English (en)
Italian (it)
Original Assignee
Itt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Itt filed Critical Itt
Application granted granted Critical
Publication of IT964201B publication Critical patent/IT964201B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/83135—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different gate conductor materials or different gate conductor implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT28438/72A 1971-09-04 1972-08-24 Circuito integrabile allo stato solido atto a controllare ovvero a regolare la tensione di soglia effettiva di un transistore ad ef fetto di campo ad isolamento di porta IT964201B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2144436A DE2144436C2 (de) 1971-09-04 1971-09-04 Integrierte Festkörperschaltung zum Einstellen der effektiven Schwellenspannung eines Isolierschicht-Feldeffekttransistors

Publications (1)

Publication Number Publication Date
IT964201B true IT964201B (it) 1974-01-21

Family

ID=5818710

Family Applications (1)

Application Number Title Priority Date Filing Date
IT28438/72A IT964201B (it) 1971-09-04 1972-08-24 Circuito integrabile allo stato solido atto a controllare ovvero a regolare la tensione di soglia effettiva di un transistore ad ef fetto di campo ad isolamento di porta

Country Status (5)

Country Link
JP (1) JPS4834677A (enExample)
AU (1) AU4603472A (enExample)
DE (1) DE2144436C2 (enExample)
FR (1) FR2152031A5 (enExample)
IT (1) IT964201B (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH614837B (fr) 1977-07-08 Ebauches Sa Dispositif pour regler, a une valeur determinee, la tension de seuil de transistors igfet d'un circuit integre par polarisation du substrat d'integration.
US4214962A (en) * 1978-07-21 1980-07-29 Pincon Andrew J Activated oxygen product and water treatment using same
DE2844878A1 (de) * 1978-10-14 1980-04-30 Itt Ind Gmbh Deutsche Integrierbarer isolierschicht-feldeffekttransistor
CH628462A5 (fr) * 1978-12-22 1982-02-26 Centre Electron Horloger Source de tension de reference.
JPS5714216A (en) * 1980-06-30 1982-01-25 Mitsubishi Electric Corp Input protecting circuit

Also Published As

Publication number Publication date
DE2144436C2 (de) 1983-01-20
FR2152031A5 (enExample) 1973-04-20
AU4603472A (en) 1974-03-07
JPS4834677A (enExample) 1973-05-21
DE2144436A1 (de) 1973-03-08

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