IT945520B - Disposizione logica di decodifi cazione di indirizzamento per una memoria a semiconduttore - Google Patents

Disposizione logica di decodifi cazione di indirizzamento per una memoria a semiconduttore

Info

Publication number
IT945520B
IT945520B IT54829/71A IT5482971A IT945520B IT 945520 B IT945520 B IT 945520B IT 54829/71 A IT54829/71 A IT 54829/71A IT 5482971 A IT5482971 A IT 5482971A IT 945520 B IT945520 B IT 945520B
Authority
IT
Italy
Prior art keywords
semiconductor memory
logical arrangement
addressing decoding
addressing
decoding
Prior art date
Application number
IT54829/71A
Other languages
English (en)
Original Assignee
North Amercian Rockwell Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by North Amercian Rockwell Corp filed Critical North Amercian Rockwell Corp
Application granted granted Critical
Publication of IT945520B publication Critical patent/IT945520B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
IT54829/71A 1970-12-18 1971-12-17 Disposizione logica di decodifi cazione di indirizzamento per una memoria a semiconduttore IT945520B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US9944070A 1970-12-18 1970-12-18

Publications (1)

Publication Number Publication Date
IT945520B true IT945520B (it) 1973-05-10

Family

ID=22275020

Family Applications (1)

Application Number Title Priority Date Filing Date
IT54829/71A IT945520B (it) 1970-12-18 1971-12-17 Disposizione logica di decodifi cazione di indirizzamento per una memoria a semiconduttore

Country Status (9)

Country Link
US (1) US3665473A (it)
JP (1) JPS5246463B1 (it)
BE (1) BE776888A (it)
CA (1) CA984968A (it)
DE (1) DE2162712A1 (it)
FR (1) FR2118181B1 (it)
GB (1) GB1340758A (it)
IT (1) IT945520B (it)
NL (1) NL7117402A (it)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728696A (en) * 1971-12-23 1973-04-17 North American Rockwell High density read-only memory
GB1375958A (en) * 1972-06-29 1974-12-04 Ibm Pulse circuit
US4045811A (en) * 1975-08-04 1977-08-30 Rca Corporation Semiconductor integrated circuit device including an array of insulated gate field effect transistors
US4001601A (en) * 1975-09-25 1977-01-04 International Business Machines Corporation Two bit partitioning circuit for a dynamic, programmed logic array
US4477739A (en) * 1975-12-29 1984-10-16 Mostek Corporation MOSFET Random access memory chip
US4044330A (en) * 1976-03-30 1977-08-23 Honeywell Information Systems, Inc. Power strobing to achieve a tri state
JPS5493335A (en) * 1977-12-30 1979-07-24 Fujitsu Ltd Decoder circuit
JPS5833633B2 (ja) * 1978-08-25 1983-07-21 シャープ株式会社 Ｍｏｓトランジスタ・デコ−ダ
US4292547A (en) * 1979-07-27 1981-09-29 Motorola, Inc. IGFET Decode circuit using series-coupled transistors
US4488266A (en) * 1982-09-29 1984-12-11 Rockwell International Corporation Low-power address decoder
DE3685654D1 (de) * 1986-08-22 1992-07-16 Ibm Dekodierverfahren und -schaltungsanordnung fuer einen redundanten cmos-halbleiterspeicher.
JP2679420B2 (ja) * 1991-02-01 1997-11-19 日本電気株式会社 半導体論理回路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3541543A (en) * 1966-07-25 1970-11-17 Texas Instruments Inc Binary decoder
US3539823A (en) * 1968-08-06 1970-11-10 Rca Corp Logic circuit
US3533089A (en) * 1969-05-16 1970-10-06 Shell Oil Co Single-rail mosfet memory with capacitive storage

Also Published As

Publication number Publication date
DE2162712A1 (de) 1972-07-13
FR2118181A1 (it) 1972-07-28
GB1340758A (en) 1974-01-30
NL7117402A (it) 1972-06-20
US3665473A (en) 1972-05-23
CA984968A (en) 1976-03-02
BE776888A (fr) 1972-04-17
JPS5246463B1 (it) 1977-11-25
FR2118181B1 (it) 1976-03-26

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