IT8722287A0 - Disposizione di controllo di trama per circuito di rifasatura di trama in multiplazione temporale in duplex. - Google Patents

Disposizione di controllo di trama per circuito di rifasatura di trama in multiplazione temporale in duplex.

Info

Publication number
IT8722287A0
IT8722287A0 IT8722287A IT2228787A IT8722287A0 IT 8722287 A0 IT8722287 A0 IT 8722287A0 IT 8722287 A IT8722287 A IT 8722287A IT 2228787 A IT2228787 A IT 2228787A IT 8722287 A0 IT8722287 A0 IT 8722287A0
Authority
IT
Italy
Prior art keywords
weft
multiplation
rephase
circuit
control arrangement
Prior art date
Application number
IT8722287A
Other languages
English (en)
Other versions
IT1222916B (it
Inventor
Robert E Renner
Original Assignee
Gte Communication Syst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gte Communication Syst filed Critical Gte Communication Syst
Publication of IT8722287A0 publication Critical patent/IT8722287A0/it
Application granted granted Critical
Publication of IT1222916B publication Critical patent/IT1222916B/it

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/06—Time-space-time switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
IT8722287A 1986-10-30 1987-10-15 Disposizione di controllo di trama per circuito di rifasatura di trama in multiplazione temporale in duplex IT1222916B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/925,044 US4740961A (en) 1986-10-30 1986-10-30 Frame checking arrangement for duplex time multiplexed reframing circuitry

Publications (2)

Publication Number Publication Date
IT8722287A0 true IT8722287A0 (it) 1987-10-15
IT1222916B IT1222916B (it) 1990-09-12

Family

ID=25451119

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8722287A IT1222916B (it) 1986-10-30 1987-10-15 Disposizione di controllo di trama per circuito di rifasatura di trama in multiplazione temporale in duplex

Country Status (4)

Country Link
US (1) US4740961A (it)
BE (1) BE1000171A6 (it)
CA (1) CA1282882C (it)
IT (1) IT1222916B (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0174596B1 (ko) * 1995-05-10 1999-04-01 김광호 교환시스템의 망동기제어를 위한 클럭수신회로
US5822328A (en) * 1996-05-15 1998-10-13 International Business Machines Corporation Frame synchronization mechanism for digital simultaneous voice/data modems
US6246736B1 (en) 1998-08-19 2001-06-12 Nortel Networks Limited Digital signal framing systems and methods
DE19961139B4 (de) * 1999-12-17 2004-09-30 Siemens Ag TSSI-Überwachungsvorrichtung sowie dazugehöriges Verfahren
US8415978B2 (en) * 2008-12-29 2013-04-09 Stmicroelectronics S.R.L. State machine for generating a pulse width modulation (PWM) waveform

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3452159A (en) * 1965-12-29 1969-06-24 Automatic Elect Lab Call-for-service circuits of communication switching marker
NL166591C (nl) * 1971-05-18 1981-08-17 Philips Nv Foutencorrigerend datatransmissiestelsel.
US4030069A (en) * 1975-01-30 1977-06-14 Trw Inc. Redundant message metering network
US4310901A (en) * 1979-06-11 1982-01-12 Electronic Memories & Magnetics Corporation Address mapping for memory
US4413335A (en) * 1981-11-27 1983-11-01 Gte Automatic Electric Labs Inc. Fault recovery apparatus for a PCM switching network
US4504947A (en) * 1983-06-22 1985-03-12 Gte Automatic Electric Incorporated PCM Supervision data reformatting circuit
US4516245A (en) * 1983-06-22 1985-05-07 Gte Automatic Electric Inc. Digital span transmission circuit
US4534027A (en) * 1983-06-22 1985-08-06 Gte Automatic Electric Incorporated Duplex digital span conversion circuit arrangement
US4598268A (en) * 1983-06-22 1986-07-01 Gte Automatic Electric Inc. Digital span conversion circuit
US4514844A (en) * 1983-06-22 1985-04-30 Gte Automatic Electric Inc. Duplex digital span transmission circuit arrangement
US4543651A (en) * 1983-09-12 1985-09-24 At&T Bell Laboratories Duplicated time division switching system
US4552997A (en) * 1983-12-28 1985-11-12 Gte Automatic Electric Incorporated Arrangement for loop analysis testing for a digital switching system
US4592044A (en) * 1984-05-22 1986-05-27 At&T Information Systems Inc. Apparatus and method for checking time slot integrity of a switching system

Also Published As

Publication number Publication date
BE1000171A6 (fr) 1988-07-05
CA1282882C (en) 1991-04-09
US4740961A (en) 1988-04-26
IT1222916B (it) 1990-09-12

Similar Documents

Publication Publication Date Title
DE3485166D1 (de) Speichersteuergeraet.
DE3787217D1 (de) Entscheidungszeitsteuerschaltung.
DE3486345D1 (de) Thermostatische Regelvorrichtungen.
IT1206470B (it) Circuito di correzione est-ovest.
IT8419655A0 (it) Circuito di controllo di interfono.
IT8026254A0 (it) Circuito di controllo d'orologio.
DE3675253D1 (de) Virtuelle bildspeicherschaltung fuer vielfache bildfenster.
DE3484427D1 (de) Steuergeraet.
IT1207039B (it) Dispositivo per inserzione di trama.
IT1228416B (it) Circuito di recupero di potenza.
DE3769921D1 (de) Regalbedienungsgeraet.
DE3485122D1 (de) Steuerschaltung.
IT8424010A0 (it) Circuito di regolazione di fase.
IT8722287A0 (it) Disposizione di controllo di trama per circuito di rifasatura di trama in multiplazione temporale in duplex.
MX155294A (es) Mejoras en circuito de recuperacion de dato numerico
IT8220135A0 (it) Circuito di controllo.
IT8323608A0 (it) Circuito di controllo di punti sensori.
IT8323709A0 (it) Circuito di controllo verificabile isolato otticamente.
DE3864639D1 (de) Regelschaltung fuer laseroszillator.
DE3776291D1 (de) Neigungssteuergeraet.
IT8419212A0 (it) Circuito di comando permicroeleboratore elettronico.
FI842698A (fi) Styrkrets.
IT1204395B (it) Circuito regolatore di fase,in particolare di fase orizzontale per visualizzatori di dati
IT8845726A0 (it) Dispositivo di controllo per friggitrice.
IT8722236A0 (it) Disposizione di sincronizzazione di trama per circuito duplex di rifasamento di trama in multiplazione temporale.