IT8521638A0 - Procedimento e dispositvo per la nastratura di telaietti adaduttori. - Google Patents

Procedimento e dispositvo per la nastratura di telaietti adaduttori.

Info

Publication number
IT8521638A0
IT8521638A0 IT8521638A IT2163885A IT8521638A0 IT 8521638 A0 IT8521638 A0 IT 8521638A0 IT 8521638 A IT8521638 A IT 8521638A IT 2163885 A IT2163885 A IT 2163885A IT 8521638 A0 IT8521638 A0 IT 8521638A0
Authority
IT
Italy
Prior art keywords
taping
procedure
adapter frames
adapter
frames
Prior art date
Application number
IT8521638A
Other languages
English (en)
Other versions
IT1185286B (it
Inventor
Brett Sharenow
Original Assignee
Rogers Corporations
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rogers Corporations filed Critical Rogers Corporations
Publication of IT8521638A0 publication Critical patent/IT8521638A0/it
Application granted granted Critical
Publication of IT1185286B publication Critical patent/IT1185286B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
IT21638/85A 1984-07-23 1985-07-19 Procedimento e dispositivo per la nastratura di telaietti ad aduttori IT1185286B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US63334484A 1984-07-23 1984-07-23

Publications (2)

Publication Number Publication Date
IT8521638A0 true IT8521638A0 (it) 1985-07-19
IT1185286B IT1185286B (it) 1987-11-04

Family

ID=24539266

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21638/85A IT1185286B (it) 1984-07-23 1985-07-19 Procedimento e dispositivo per la nastratura di telaietti ad aduttori

Country Status (5)

Country Link
JP (1) JPS6136960A (it)
FR (1) FR2568059A1 (it)
GB (1) GB8518468D0 (it)
IL (1) IL75877A0 (it)
IT (1) IT1185286B (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61296749A (ja) * 1985-06-25 1986-12-27 Toray Silicone Co Ltd 半導体装置用リードフレームの製造方法
DE3674292D1 (de) * 1985-07-23 1990-10-25 Fairchild Semiconductor Verpackungsanordnung fuer halbleiterchip und verfahren zum erleichtern deren pruefung und montage auf ein substrat.
US4796080A (en) * 1987-07-23 1989-01-03 Fairchild Camera And Instrument Corporation Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate
JPH0226479Y2 (it) * 1987-08-28 1990-07-18
JPH0341679Y2 (it) * 1988-12-01 1991-09-02
JPH02170457A (ja) * 1988-12-22 1990-07-02 Hitachi Cable Ltd 半導体装置用リードフレームとそれに使用される押えテープ
US5098863A (en) * 1990-11-29 1992-03-24 Intel Corporation Method of stabilizing lead dimensions on high pin count surface mount I.C. packages

Also Published As

Publication number Publication date
FR2568059A1 (fr) 1986-01-24
JPS6136960A (ja) 1986-02-21
IL75877A0 (en) 1985-11-29
GB8518468D0 (en) 1985-08-29
IT1185286B (it) 1987-11-04

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