IT8324347A0 - Circuito numerico ad aggancio di fase (pdll). - Google Patents

Circuito numerico ad aggancio di fase (pdll).

Info

Publication number
IT8324347A0
IT8324347A0 IT8324347A IT2434783A IT8324347A0 IT 8324347 A0 IT8324347 A0 IT 8324347A0 IT 8324347 A IT8324347 A IT 8324347A IT 2434783 A IT2434783 A IT 2434783A IT 8324347 A0 IT8324347 A0 IT 8324347A0
Authority
IT
Italy
Prior art keywords
pdll
phase locked
numerical circuit
numerical
circuit
Prior art date
Application number
IT8324347A
Other languages
English (en)
Other versions
IT1194538B (it
Inventor
Carlo Quaranta
Original Assignee
Italtel Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel Spa filed Critical Italtel Spa
Priority to IT24347/83A priority Critical patent/IT1194538B/it
Publication of IT8324347A0 publication Critical patent/IT8324347A0/it
Priority to EP84201795A priority patent/EP0148525B1/en
Priority to DE8484201795T priority patent/DE3482361D1/de
Priority to DE198484201795T priority patent/DE148525T1/de
Priority to US06/684,045 priority patent/US4596964A/en
Application granted granted Critical
Publication of IT1194538B publication Critical patent/IT1194538B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
IT24347/83A 1983-12-23 1983-12-23 Circuito numerico ad aggancio di fase (pdll) IT1194538B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT24347/83A IT1194538B (it) 1983-12-23 1983-12-23 Circuito numerico ad aggancio di fase (pdll)
EP84201795A EP0148525B1 (en) 1983-12-23 1984-12-04 Digital phase locked loop (dpll)
DE8484201795T DE3482361D1 (de) 1983-12-23 1984-12-04 Digitale phasenriegelschleife.
DE198484201795T DE148525T1 (de) 1983-12-23 1984-12-04 Digitale phasenriegelschleife.
US06/684,045 US4596964A (en) 1983-12-23 1984-12-20 Digital phase locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT24347/83A IT1194538B (it) 1983-12-23 1983-12-23 Circuito numerico ad aggancio di fase (pdll)

Publications (2)

Publication Number Publication Date
IT8324347A0 true IT8324347A0 (it) 1983-12-23
IT1194538B IT1194538B (it) 1988-09-22

Family

ID=11213199

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24347/83A IT1194538B (it) 1983-12-23 1983-12-23 Circuito numerico ad aggancio di fase (pdll)

Country Status (4)

Country Link
US (1) US4596964A (it)
EP (1) EP0148525B1 (it)
DE (2) DE148525T1 (it)
IT (1) IT1194538B (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4715000A (en) * 1985-08-06 1987-12-22 General Electric Company Digital phase-locked loop and frequency measuring device
US4787096A (en) * 1987-03-04 1988-11-22 National Semiconductor Corp. Second-order carrier/symbol sychronizer
EP0310088B1 (en) * 1987-10-01 1996-06-05 Sharp Kabushiki Kaisha Digital phase-locked loop system
DE4004195C2 (de) * 1990-02-12 1996-10-02 Broadcast Television Syst Schaltungsanordnung zur Erzeugung eines mit einem Referenzsignal verkoppelten Signals
US5442315A (en) * 1993-07-27 1995-08-15 International Business Machines Corporation Bit stream rate asynchronous digital phase-locked loop
DE19653129C2 (de) * 1996-12-19 1999-01-28 Siemens Ag Verfahren zum Erzeugen eines Ansteuersignals für einen spannungsgesteuerten Oszillator in einem Phasenregelkreis
US6249159B1 (en) 1999-12-30 2001-06-19 Intel Corporation Frequency control circuit having increased control bandwidth at lower device operating speed
FR2854751B1 (fr) * 2003-05-07 2005-07-22 St Microelectronics Sa Circuit de recuperation d'horloge
US11595048B1 (en) * 2022-03-25 2023-02-28 Cypress Semiconductor Corporation Faster phase-locked loop locking using successive approximation toward a target frequency

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3562661A (en) * 1969-01-15 1971-02-09 Ibm Digital automatic phase and frequency control system
US3715751A (en) * 1970-09-30 1973-02-06 Raytheon Co Digital speed gate for doppler radar
US3883817A (en) * 1973-08-20 1975-05-13 Nasa Digital phase-locked loop
US4019153A (en) * 1974-10-07 1977-04-19 The Charles Stark Draper Laboratory, Inc. Digital phase-locked loop filter
JPS5755628A (en) * 1980-09-22 1982-04-02 Hitachi Ltd Phase comparing circuit and frequency synthesizer using it
US4531102A (en) * 1983-02-28 1985-07-23 Gk Technologies, Incorporated Digital phase lock loop system

Also Published As

Publication number Publication date
DE148525T1 (de) 1985-09-26
IT1194538B (it) 1988-09-22
US4596964A (en) 1986-06-24
EP0148525B1 (en) 1990-05-23
DE3482361D1 (de) 1990-06-28
EP0148525A3 (en) 1987-08-19
EP0148525A2 (en) 1985-07-17

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