IT8224060A0 - Procedimento di mappatura della memoria in sistema di elaborazione dati. - Google Patents

Procedimento di mappatura della memoria in sistema di elaborazione dati.

Info

Publication number
IT8224060A0
IT8224060A0 IT8224060A IT2406082A IT8224060A0 IT 8224060 A0 IT8224060 A0 IT 8224060A0 IT 8224060 A IT8224060 A IT 8224060A IT 2406082 A IT2406082 A IT 2406082A IT 8224060 A0 IT8224060 A0 IT 8224060A0
Authority
IT
Italy
Prior art keywords
data processing
processing system
memory mapping
mapping procedure
procedure
Prior art date
Application number
IT8224060A
Other languages
English (en)
Other versions
IT8224060A1 (it
IT1153611B (it
Inventor
Calogero Mantellina
Roberto Trivella
Andrea Quadrauopolo
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Priority to IT24060/82A priority Critical patent/IT1153611B/it
Publication of IT8224060A0 publication Critical patent/IT8224060A0/it
Priority to DE8383110751T priority patent/DE3380151D1/de
Priority to EP83110751A priority patent/EP0108346B1/en
Priority to KR1019830005133A priority patent/KR880002657B1/ko
Priority to US06/547,268 priority patent/US4592011A/en
Priority to BR8306051A priority patent/BR8306051A/pt
Publication of IT8224060A1 publication Critical patent/IT8224060A1/it
Application granted granted Critical
Publication of IT1153611B publication Critical patent/IT1153611B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Logic Circuits (AREA)
IT24060/82A 1982-11-04 1982-11-04 Procedimento di mappatura della memoria in sistema di elaborazione dati IT1153611B (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT24060/82A IT1153611B (it) 1982-11-04 1982-11-04 Procedimento di mappatura della memoria in sistema di elaborazione dati
DE8383110751T DE3380151D1 (en) 1982-11-04 1983-10-27 Memory reconfiguration method in a data processing system
EP83110751A EP0108346B1 (en) 1982-11-04 1983-10-27 Memory reconfiguration method in a data processing system
KR1019830005133A KR880002657B1 (ko) 1982-11-04 1983-10-29 데이타 처리 시스템에서 메모리 매핑(mapping)방법
US06/547,268 US4592011A (en) 1982-11-04 1983-10-31 Memory mapping method in a data processing system
BR8306051A BR8306051A (pt) 1982-11-04 1983-11-03 Processo de mapeamento de memoria em um sistema de processamento de dados

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT24060/82A IT1153611B (it) 1982-11-04 1982-11-04 Procedimento di mappatura della memoria in sistema di elaborazione dati

Publications (3)

Publication Number Publication Date
IT8224060A0 true IT8224060A0 (it) 1982-11-04
IT8224060A1 IT8224060A1 (it) 1984-05-04
IT1153611B IT1153611B (it) 1987-01-14

Family

ID=11211745

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24060/82A IT1153611B (it) 1982-11-04 1982-11-04 Procedimento di mappatura della memoria in sistema di elaborazione dati

Country Status (6)

Country Link
US (1) US4592011A (it)
EP (1) EP0108346B1 (it)
KR (1) KR880002657B1 (it)
BR (1) BR8306051A (it)
DE (1) DE3380151D1 (it)
IT (1) IT1153611B (it)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1234224A (en) * 1985-05-28 1988-03-15 Boleslav Sykora Computer memory management system
JPS62208977A (ja) * 1986-03-10 1987-09-14 Brother Ind Ltd プリンタ
US4821185A (en) * 1986-05-19 1989-04-11 American Telephone And Telegraph Company I/O interface system using plural buffers sized smaller than non-overlapping contiguous computer memory portions dedicated to each buffer
JPS62190999U (it) * 1986-05-23 1987-12-04
JPS63143689A (ja) * 1986-12-06 1988-06-15 Tokyo Electric Co Ltd メモリカ−ドの容量検出装置
US4831522A (en) * 1987-02-17 1989-05-16 Microlytics, Inc. Circuit and method for page addressing read only memory
US4980850A (en) * 1987-05-14 1990-12-25 Digital Equipment Corporation Automatic sizing memory system with multiplexed configuration signals at memory modules
JPH0679290B2 (ja) * 1987-05-31 1994-10-05 日本電気株式会社 コンピュ−タ装置
US5003506A (en) * 1987-06-02 1991-03-26 Anritsu Corporation Memory capacity detection apparatus and electronic applied measuring device employing the same
IT1216087B (it) * 1988-03-15 1990-02-22 Honeywell Bull Spa Sistema di memoria con selezione predittiva di modulo.
US5418965A (en) * 1988-06-24 1995-05-23 Mahar; Robert C. Subroutine-type computer program for enhancing the speed of data processing in data management programs systems
US5095420A (en) * 1988-11-21 1992-03-10 International Business Machines Method and system for performing virtual address range mapping in a virtual storage data processing system
FR2639731A1 (fr) * 1988-11-30 1990-06-01 Europ Rech Electr Lab Ordinateur et procede de gestion de memoire d'un ordinateur
US5063499A (en) * 1989-01-09 1991-11-05 Connectix, Inc. Method for a correlating virtual memory systems by redirecting access for used stock instead of supervisor stock during normal supervisor mode processing
US5119486A (en) * 1989-01-17 1992-06-02 Prime Computer Memory board selection method and apparatus
JPH02245840A (ja) * 1989-03-20 1990-10-01 Fujitsu Ltd 記憶装置
US5163145A (en) * 1989-04-25 1992-11-10 Dell Usa L.P. Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory reference
JP3024767B2 (ja) * 1989-08-29 2000-03-21 株式会社日立製作所 アドレス供給システム
JPH03282648A (ja) * 1990-03-29 1991-12-12 Sharp Corp メモリ制御装置
JPH0418638A (ja) * 1990-05-11 1992-01-22 Fujitsu Ltd 静的メモリ割当て処理方法
US5241665A (en) * 1990-08-31 1993-08-31 Advanced Micro Devices, Inc. Memory bank comparator system
US5530934A (en) * 1991-02-02 1996-06-25 Vlsi Technology, Inc. Dynamic memory address line decoding
US5448710A (en) * 1991-02-26 1995-09-05 Hewlett-Packard Company Dynamically configurable interface cards with variable memory size
JP2987206B2 (ja) * 1991-12-13 1999-12-06 アヴィッド・テクノロジー・インコーポレーテッド バッファ及びフレーム索引作成
US5386383A (en) * 1994-02-28 1995-01-31 At&T Corp. Method and apparatus for controlling dynamic random access memory devices
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
JP3684685B2 (ja) * 1996-07-01 2005-08-17 ブラザー工業株式会社 双方向通信認識方法、双方向通信認識装置および記憶媒体
US5922055A (en) * 1997-02-25 1999-07-13 Motorola, Inc. Method for determining a type of a serial EEPROM and plug and play controller
US8250295B2 (en) 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US7289386B2 (en) 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US20060088284A1 (en) * 2004-10-26 2006-04-27 Paul Shen Digital photo kiosk and methods for digital image processing
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
US8787060B2 (en) 2010-11-03 2014-07-22 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
EP3629123B1 (en) 2013-07-27 2021-02-24 Netlist, Inc. Memory module with local synchronization

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3800289A (en) * 1972-05-15 1974-03-26 Goodyear Aerospace Corp Multi-dimensional access solid state memory
US3800292A (en) * 1972-10-05 1974-03-26 Honeywell Inf Systems Variable masking for segmented memory
US4025903A (en) * 1973-09-10 1977-05-24 Computer Automation, Inc. Automatic modular memory address allocation system
US3840863A (en) * 1973-10-23 1974-10-08 Ibm Dynamic storage hierarchy system
US3958222A (en) * 1974-06-27 1976-05-18 Ibm Corporation Reconfigurable decoding scheme for memory address signals that uses an associative memory table
US4001786A (en) * 1975-07-21 1977-01-04 Sperry Rand Corporation Automatic configuration of main storage addressing ranges
US4214303A (en) * 1977-12-22 1980-07-22 Honeywell Information Systems Inc. Word oriented high speed buffer memory system connected to a system bus
JPS5580164A (en) * 1978-12-13 1980-06-17 Fujitsu Ltd Main memory constitution control system

Also Published As

Publication number Publication date
KR840006850A (ko) 1984-12-03
DE3380151D1 (en) 1989-08-10
IT8224060A1 (it) 1984-05-04
EP0108346A2 (en) 1984-05-16
EP0108346B1 (en) 1989-07-05
KR880002657B1 (ko) 1988-12-17
BR8306051A (pt) 1984-06-12
EP0108346A3 (en) 1986-11-26
IT1153611B (it) 1987-01-14
US4592011A (en) 1986-05-27

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129