IT8021315A0 - Processo per la formazione di sottili pellicole metalliche. - Google Patents

Processo per la formazione di sottili pellicole metalliche.

Info

Publication number
IT8021315A0
IT8021315A0 IT8021315A IT2131580A IT8021315A0 IT 8021315 A0 IT8021315 A0 IT 8021315A0 IT 8021315 A IT8021315 A IT 8021315A IT 2131580 A IT2131580 A IT 2131580A IT 8021315 A0 IT8021315 A0 IT 8021315A0
Authority
IT
Italy
Prior art keywords
formation
thin metallic
metallic films
films
thin
Prior art date
Application number
IT8021315A
Other languages
English (en)
Other versions
IT1148818B (it
Inventor
Rothman Laura Beth
Totta Paul Anthony
White James Francis
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT8021315A0 publication Critical patent/IT8021315A0/it
Application granted granted Critical
Publication of IT1148818B publication Critical patent/IT1148818B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H01L23/4855—Overhang structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
IT21315/80A 1979-05-29 1980-04-11 Processo per la formazione di sottili pellicole metalliche IT1148818B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/043,416 US4272561A (en) 1979-05-29 1979-05-29 Hybrid process for SBD metallurgies

Publications (2)

Publication Number Publication Date
IT8021315A0 true IT8021315A0 (it) 1980-04-11
IT1148818B IT1148818B (it) 1986-12-03

Family

ID=21927069

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21315/80A IT1148818B (it) 1979-05-29 1980-04-11 Processo per la formazione di sottili pellicole metalliche

Country Status (6)

Country Link
US (1) US4272561A (it)
EP (1) EP0019781B1 (it)
JP (1) JPS606537B2 (it)
CA (1) CA1126629A (it)
DE (1) DE3071901D1 (it)
IT (1) IT1148818B (it)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4371423A (en) * 1979-09-04 1983-02-01 Vlsi Technology Research Association Method of manufacturing semiconductor device utilizing a lift-off technique
DE3005733A1 (de) * 1980-02-15 1981-08-20 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung einer halbleiteranordnung und nach diesem verfahren hergestellte halbleiteranordnung
US4351892A (en) * 1981-05-04 1982-09-28 Fairchild Camera & Instrument Corp. Alignment target for electron-beam write system
US4396458A (en) * 1981-12-21 1983-08-02 International Business Machines Corporation Method for forming planar metal/insulator structures
JPS592352A (ja) * 1982-06-28 1984-01-07 Toshiba Corp 半導体装置の製造方法
US4400257A (en) * 1982-12-21 1983-08-23 Rca Corporation Method of forming metal lines
US4493855A (en) * 1982-12-23 1985-01-15 International Business Machines Corporation Use of plasma polymerized organosilicon films in fabrication of lift-off masks
US4562091A (en) * 1982-12-23 1985-12-31 International Business Machines Corporation Use of plasma polymerized orgaosilicon films in fabrication of lift-off masks
US4539222A (en) * 1983-11-30 1985-09-03 International Business Machines Corporation Process for forming metal patterns wherein metal is deposited on a thermally depolymerizable polymer and selectively removed
JPS60138940A (ja) * 1983-12-27 1985-07-23 Toshiba Corp 半導体装置の製造方法
US4519872A (en) * 1984-06-11 1985-05-28 International Business Machines Corporation Use of depolymerizable polymers in the fabrication of lift-off structure for multilevel metal processes
US4640738A (en) * 1984-06-22 1987-02-03 International Business Machines Corporation Semiconductor contact protection
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material
JPS61249480A (ja) * 1985-04-30 1986-11-06 デンカ製薬株式会社 衣類に貼着する肩こり治療具
JPS61249481A (ja) * 1985-04-30 1986-11-06 デンカ製薬株式会社 繰返し使用できる肩こり治療具
JPS61182751U (it) * 1985-05-01 1986-11-14
JPS621030U (it) * 1985-06-17 1987-01-07
JPS621294U (it) * 1985-06-17 1987-01-07
JPS6237928A (ja) * 1985-08-13 1987-02-18 Matsushita Electronics Corp 金属パタ−ン形成方法
JPS6373660A (ja) * 1986-09-17 1988-04-04 Fujitsu Ltd 半導体装置
US4687541A (en) * 1986-09-22 1987-08-18 Rockwell International Corporation Dual deposition single level lift-off process
JPS6427567A (en) * 1987-07-22 1989-01-30 Matsushita Electric Works Ltd Blood circulation promoting apparatus
US5021840A (en) * 1987-08-18 1991-06-04 Texas Instruments Incorporated Schottky or PN diode with composite sidewall
US5132775A (en) * 1987-12-11 1992-07-21 Texas Instruments Incorporated Methods for and products having self-aligned conductive pillars on interconnects
US4835086A (en) * 1988-02-12 1989-05-30 Hoechst Celanese Corporation Polysulfone barrier layer for bi-level photoresists
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5057186A (en) * 1989-07-28 1991-10-15 At&T Bell Laboratories Method of taper-etching with photoresist adhesion layer
US5118584A (en) * 1990-06-01 1992-06-02 Eastman Kodak Company Method of producing microbump circuits for flip chip mounting
US5384283A (en) * 1993-12-10 1995-01-24 International Business Machines Corporation Resist protection of ball limiting metal during etch process
US5807766A (en) * 1995-09-21 1998-09-15 Mcbride; Donald G. Process for attaching a silicon chip to a circuit board using a block of encapsulated wires and the block of wires manufactured by the process
JP2004005923A (ja) * 2002-03-29 2004-01-08 Fujitsu Ltd 磁気ヘッドの製造方法および磁気ヘッド、パターン形成方法
US7129590B2 (en) * 2003-05-14 2006-10-31 Intel Corporation Stencil and method for depositing material onto a substrate
US20060076639A1 (en) * 2004-10-13 2006-04-13 Lypen William J Schottky diodes and methods of making the same
JP4588091B2 (ja) * 2008-02-29 2010-11-24 三洋電機株式会社 半導体モジュールの製造方法
US8349727B2 (en) * 2010-04-08 2013-01-08 Liang Guo Integrated method for high-density interconnection of electronic components through stretchable interconnects
US20150340611A1 (en) * 2014-05-21 2015-11-26 Sony Corporation Method for a dry exhumation without oxidation of a cell and source line
IT201700067128A1 (it) * 2017-06-16 2018-12-16 Sambusseti Antonio Rivestimento conduttivo

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2559389A (en) * 1942-04-02 1951-07-03 Keuffel & Esser Co Method of producing precision images
US3873361A (en) * 1973-11-29 1975-03-25 Ibm Method of depositing thin film utilizing a lift-off mask
US4004044A (en) * 1975-05-09 1977-01-18 International Business Machines Corporation Method for forming patterned films utilizing a transparent lift-off mask
US4088490A (en) * 1976-06-14 1978-05-09 International Business Machines Corporation Single level masking process with two positive photoresist layers
US4076575A (en) * 1976-06-30 1978-02-28 International Business Machines Corporation Integrated fabrication method of forming connectors through insulative layers
US4045318A (en) * 1976-07-30 1977-08-30 Rca Corporation Method of transferring a surface relief pattern from a poly(olefin sulfone) layer to a metal layer
US4070501A (en) * 1976-10-28 1978-01-24 Ibm Corporation Forming self-aligned via holes in thin film interconnection systems
US4092442A (en) * 1976-12-30 1978-05-30 International Business Machines Corporation Method of depositing thin films utilizing a polyimide mask
US4132586A (en) * 1977-12-20 1979-01-02 International Business Machines Corporation Selective dry etching of substrates

Also Published As

Publication number Publication date
CA1126629A (en) 1982-06-29
DE3071901D1 (en) 1987-03-05
EP0019781A2 (en) 1980-12-10
JPS55158630A (en) 1980-12-10
EP0019781B1 (en) 1987-01-28
EP0019781A3 (en) 1983-08-03
JPS606537B2 (ja) 1985-02-19
US4272561A (en) 1981-06-09
IT1148818B (it) 1986-12-03

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