IT202000018733A1 - INTEGRATED MOS TRANSISTOR WITH SELECTIVE DISABLING OF ITS CELLS - Google Patents

Description

DESCRIPTION

Technical field

This disclosure pertains to the field of embedded devices. Pi? specifically, this disclosure relates to MOS transistors.

Background

The background to this disclosure? hereinafter introduced with the discussion of techniques related to its context. However, even when this discussion pertains to documents, records, artifacts, and the like, it does not suggest or acknowledge that the techniques discussed are prior art or general knowledge in the field relevant to this disclosure.

Integrated devices based on MOS transistors are commonly used in various applications. In particular, the MOS transistors are among the most? common in power applications, in which they are treated large quantities? electricity; in this case, the MOS transistors are designed to operate at relatively high voltages and/or currents. MOS (power) transistors generally have a cellular structure. In particular, each MOS transistor replicates the same structure on multiple? cells. The cells comprise corresponding gate regions and source (base) regions which are connected in parallel, for example in the form of alternating strips. The cellular structure provides a high perimeter/area ratio of the source regions. There? allows to obtain a relatively wide channel (thereby increasing the current that can be sustained) in a relatively small area of a plate (die) on which ? integrated the MOS transistor (thereby reducing the size of the corresponding integrated circuit).

The performance of MOS transistors is defined by several of their characteristics. In particular, a very important characteristic of MOS transistors ? their safe operating area (SOA). The SOA of each MOS transistor ? defined by the drain/source voltage Vds and the drain/source current (Ids) that the MOS transistor is expected to sustain without damage (with the MOS transistor never expected to be exposed to operating conditions outside its SOA, even for an instant ).

Several factors limit the SOA of MOS transistors. In particular, in a diagram representing the drain/source voltage Vds and the drain/source current Ids on a logarithmic scale, the SOA ? bounded by substantially straight edge segments. These edge segments are defined (in succession for increasing values of the drain/source voltage Vds) by an access or output state drain/source resistance limitation RDSon (which impacts the MOS transistor operating in the linear or ohmic region in which the drain/source voltage Vds is substantially proportional to the drain/source current Ids), a drain/source limitation Ids (determined by its maximum value), a thermal limitation (determined by a maximum heat dissipation), a secondary breakdown limitation (caused by a thermal runaway impacting the MOS transistor when it operates in a linear mode where the drain/source current Ids is proportional to small variations of its gate/source voltage Vgs) and a drain/source voltage limitation source Vds (determined by its maximum value).

One technique for extending the SOA of a MOS transistor (with a cellular structure) is to remove the source regions in some cells (such as one out of every two). In this way, resulting dummy regions of the die in which the source regions are removed are inactive during operation of the MOS transistor and therefore do not generate heat. Additionally, the dummy regions act as a heat sink for the rest of the MOS transistor. Therefore, the heat generated by the MOS transistor (around the remaining source regions) ? partly dissipated by the fictitious regions, with the ci? limiting the heating of the MOS transistor.

However, the dummy regions reduce the number of source regions of the MOS transistor, and thus consequently increase its drain/source access state resistance RDSon. In fact, the drain/source access state resistor RDSon ? given by different contributions along a path of the drain/source current Ids from a drain terminal to a source terminal of the MOS transistor; in particular, these contributions include a resistance of the source regions. because source regions are connected in parallel, minor ? the number of source regions, greater ? their total resistance.

The increase of the drain/source access state resistance RDSon consequently increases the corresponding limitation in the SOA of the MOS transistor. Therefore, there? negatively affects the performance of the MOS transistor, especially when it operates in the linear region.

Summary

A simplified summary of this disclosure? presented here in order to provide a basic understanding thereof; however, the sole purpose of this summary is to introduce some concepts of disclosure in simplified form as a prelude to its following description more? detailed, isn't it ? to be interpreted as a? identification of its key elements n? as a delimitation of its scope.

In general terms, this disclosure ? based on the idea of selectively disabling cells.

In particular, one aspect provides an integrated device comprising at least one MOS transistor having a plurality of of cells. In each of one or more of the cells? provision of a disabling structure; the disabling structure ? configured to be in a non-conductive condition when the MOS transistor ? turned on in response to a control voltage between a MOS transistor threshold voltage and a disable structure trip voltage, or to be in a conductive condition otherwise.

A further aspect provides a system comprising at least one integrated device as above.

A further aspect provides a corresponding process for manufacturing this integrated device.

Pi? specifically, one or more aspects of the present disclosure are set forth in the independent claims and advantageous features thereof are set forth in the dependent claims, with the text of all claims incorporated herein by reference (with any beneficial features provided in respect of each specific aspect applying mutatis mutandis to every other aspect).

Brief description of the drawings

The solution of this disclosure, as well as additional features and benefits thereof, will be better understood with reference to the following detailed description, provided purely for indicative and non-limiting purposes, to be read in conjunction with the attached figures (in which, for simplicity?, corresponding elements are indicated with the same or similar references and their explanation is not repeated, and the name of each entity is generally used to denote both its type and its attributes, such as value, content, and representation). In this regard, ? expressly understood that the figures are not necessarily to scale (with some details that may be exaggerated and/or simplified) and that, unless otherwise indicated, they are simply used to conceptually illustrate the structures and procedures described herein. In particular: FIG.1 shows a partial cross-sectional illustrative representation of an integrated device according to an embodiment of the present disclosure,

FIG.2 shows an equivalent circuit of a MOS transistor according to an embodiment of the present disclosure,

FIG.3A-FIG.3K show the main steps of an integrated device manufacturing process according to an embodiment of the present disclosure, and

FIG.4 shows a principle block diagram of a system incorporating the integrated device according to an embodiment of the present disclosure.

Detailed description

With reference in particular to FIG. 1, ? shown is a partial cross-sectional illustrative representation of an integrated device 100 in accordance with an embodiment of the present disclosure.

The integrated device 100 comprises a MOS transistor 105 (or more). The MOS transistor 105 ? of double diffusion type (DMOS) and has a vertical structure based on trench gates, for example, with a U-shape (UMOS). The MOS transistor 105 implements a power component, which ? designed to handle relatively high electrical power (e.g., of the order of more than 10 W), as operating at corresponding relatively high currents and/or voltages (e.g., of the order of more than 10 A and 10 V, respectively).

The MOS transistor 105 ? integrated on a semiconductor body, such as a chip 110 of semiconductor material, for example, silicon (so as to define a corresponding chip). As usual, the concentrations of impurities? N- and P-type (or dopant) semiconductor material are denoted by adding the sign or - sign to the letters N and P to indicate high or low concentration of impurities, respectively, or the + sign or -- sign to indicate a very high or very low concentration, respectively, of impurities; the letters N and P without the addition of any signs or - denote concentrations of intermediate value. The chip 110 comprises a substrate 115 of the N++ type (much thicker in reality), on which arranged a (thin) N-type epitaxial layer 120. A free main surface of the epitaxial layer 120 defines a front surface 125f of the chip 110, while a free main surface of the substrate 115 defines a rear surface 125b of the chip 110 (opposite to each other) .

MOS transistor 105 includes the following components. An N++ type drain region? defined by substrate 115 (extending into die 110 from back surface 125b). A P-type body region 130 extends into the epitaxial layer 120 of the chip 110 from the front surface 125f, so as to remain separated from the drain region 115. The MOS transistor 105 has a cellular structure, with the same structure replicated in a plurality ? of cells (such as 100-1,000). In particular, each cell comprises the following components. An N+ type source region 135 extends into the body region 130 from the front surface 125f. A gate trench 140 extends into the body region 130 and then into the epitaxial layer 120 of the chip 110 from the front surface 125f. The trench of gate 140 ? coated with a (relatively thin) gate insulating layer 145 of (electrically) insulating material (e.g., silicon dioxide). THE GATE TRENCH (LINED) 140 ? filled with a gate element 150 of (electrically) conductive material, such as N+ type doped polysilicon. The MOS transistor has an interdigitated architecture; in particular, in plan view (on the front surface 125f) the source regions 135 and the gate elements 150 have an elongated shape (stripes) and are arranged parallel, alternating with each other (like crossed fingers). A drain contact 155 of (electrically) conductive material (e.g., metal) contacts the drain region 115 on the back surface 125b. A protective layer 160 of (electrically) insulating material (e.g., silicon dioxide) covers the front surface 125f (partially removed in the figure for clarity). A source contact 165 of (electrically) conductive material (e.g., metal) contacts all source regions 135 and the body region 130 through the protective layer 160. A gate contact 170 of (electrically) conductive material (e.g., , metal) contacts all the source regions 135 through the protective layer 160.

As usual, the MOS transistor 105 can? operate in three different regions of its characteristic according to the voltages at its terminals (defined by the drain contact 155, by the source contact 165 and by the gate contact 170). In particular, in a cutoff or subthreshold region, a gate/source (control) voltage Vgs ? lower than a threshold voltage Vth of the MOS transistor 105 (for example 1-2 V); in this condition, the MOS transistor 105 ? off (with no drain/source current Ids flowing through it). In a linear or ohmic region the gate/source voltage Vgs ? higher than the threshold voltage Vth and a drain/source voltage Vds ? strictly lower than an overdrive voltage Vov=Vgs-Vth (Vds<Vgs-Vth); in this condition the MOS transistor 105 ? on and the drain/source voltage Vds ? substantially proportional to the drain/source current Ids. In a saturation region or active gate/source voltage Vgs ? still higher than the threshold voltage Vth but the drain/source voltage Vds ? higher than the overdrive voltage (Vds?Vgs-Vth); in this condition, the MOS transistor 105 ? still on but now the current drain/source Ids ? substantially constant (regardless of the drain/source voltage Vds).

In the solution according to an embodiment of the present disclosure, as described in detail below, one or more Selected cells further comprise corresponding disabling structures which are capable of selectively disabling themselves. In particular, each disabling structure ? interposed between a portion of the gate element 150 coupled to the gate contact 170 and another portion of the gate element 150 decoupled from the gate contact 170. The disabling structure has a tripping voltage which is ? greater than the threshold voltage Vth (for example, equal to 1.5-3 times). The disabling structure ? configured to be in a non-conductive condition when the MOS transistor ? on in response to the gate/source voltage Vgs between the threshold voltage Vth and the trip voltage, and to be in a conductive condition otherwise.

Therefore, when the gate/source voltage Vgs ? slightly higher than the threshold voltage Vth, the disabling structures are in the nonconductive condition; typically, there? it occurs when the MOS transistor 105 operates in the saturation region (because Vgs?Vth+Vds). In this condition, a zero voltage ? applied between the corresponding (selected) gate elements 150 and the source regions 135. The selected cells are then inactive and generate no heat, further acting as a heat sink for the rest of the MOS transistor 105. Thus, the heat generated by the MOS transistor (around the source regions 135 of the other cells) ? partly dissipated by the selected cells, with the ci? limiting the heating of the MOS transistor 105.

Conversely, when the gate/source voltage Vgs ? much higher than the threshold voltage Vth the disabling structures are in the conductive condition; typically, there? it happens when the MOS transistor 105 operates in the linear region (because Vgs>Vth+Vds). In this condition, the disabling structures are substantially transparent to the operation of the MOS transistor 105; in particular, all cells are active with all source regions 135 contributing to the drain/source on-state resistor RDSon, which is not? therefore negatively impacted.

Finally, when the gate/source voltage Vgs ? lower than the threshold voltage Vth, the disabling structures are again in the conductive condition; There? it occurs when the MOS transistor 105 operates in the off region. Even in this condition, the disabling structures are substantially transparent to the operation of the MOS transistor 105.

Therefore, the solution described above allows the selected cells to be selectively disabled in a dynamic way, according to the current operating condition of the MOS transistor. In particular, the selected cells are inactive when the MOS transistor operates at a relatively high drain/source voltage Vds (as typical of the saturation region). In this condition, ? advantageous to limit the heating of the MOS transistor (since it mainly impacts the corresponding portion of the SOA); in this condition, the consequent increase in the RDSon access state resistance of the drain/source ? substantially irrelevant (since the drain/source current Ids is practically constant). Conversely, all the cells are active when the MOS transistor operates at a relatively low drain/source voltage Vds (as typical of the linear region, down to zero in the turn-off region). In this condition? it is advantageous to keep the RDS drain/source on-state resistance low (since it mainly impacts the corresponding portion of the SOA); in this condition, the failure to limit the heating? essentially irrelevant (because the MOS transistor generates a relatively small amount of heat).

In particular, in the specific embodiment shown in the figure, the gate element 150 of each selected cell comprises the following additional components. A separation region 175 of the P+ type (for example, also of doped polysilicon) extends in the gate element 150 from the front surface 125f until it reaches the insulating layer 145; in plan view (on the front surface 125f) the separation region 175 completely crosses the gate element 150 transversely (close to the gate contact 170). Accordingly, the separation region 175 separates the gate element 150 into two parts, denoted as the gate (coupled) portion 150c and the gate (decoupled) portion 150u. The gate portion 150c ? proximal to gate contact 170, so as to still be coupled therewith; the portion of the gate 150u ? distal from the gate contact 170 and therefore decoupled from it (and in particular in an area of the chip 110 in which the channel of the operating MOS transistor 105 is formed). Corresponding PN junctions are then created between the separation region 175 and the gate portion 150c and between the separation region 175 and the gate portion 150u. A bridge contact 180 of (electrically) conductive material (e.g., metal) contacts both the separation region 175 and the gate portion 150u (with the bridge contact 180 left floating).

Referring now to FIG.2 in conjunction with FIG.1, ? shown is an equivalent circuit of the MOS transistor 105 in accordance with an embodiment of the present disclosure.

The MOS transistor 105 comprises a plurality of basic MOS transistors Mi defined by its cells, with i = 1? N where N ? the number of cells (four shown in the figure). In particular, each basic MOS transistor Mi has a drain (formed by a corresponding portion of the drain region 115), a source (formed by the corresponding source region 135) and a gate (formed by the corresponding gate element 150), with a body (formed by a corresponding portion of the body region 130) which ? shorted to source (via source contact 165). A gate resistor Rgi connected to the gate of each basic MOS transistor Mi represents a resistance of the gate element 150 between the gate contact 170 and the area of the chip 110 in which the channel of the operating MOS transistor 105 is formed.

In the solution according to an embodiment of the present disclosure, in the base MOS transistor Ms of each selected cell, with s=1.3 in the example in question, a diode Dds (formed by the PN junction between the separation region 175 and the gate portion 150u) and a diode Dps (formed by the PN junction between the separation region 175 and the gate portion 150c) are connected in anti-series to the gate resistor Rgs; in particular, the anode of the Dds diode ? connected to the anode of the Dps diode (common separation region 175), and the cathode of the Dds diode ? connected to the gate resistor Rgs (portion of gate 150u which mainly contributes to it). Also, the Dds diode has its anode and cathode which are shorted (via the bridge contact 180). The Dps diode has a (reverse) breakdown voltage Vbk (defined by the minimum voltage that causes the Dps diode to conduct appreciably when reverse biased) well above the threshold voltage Vth (e.g., 2-4 V), which voltage voltage Vbk defines the tripping voltage of the disabling structure.

The basic MOS transistors Mi are connected substantially in parallel (apart from the diodes Dds, Dps where present) to form the entire MOS transistor 105. In particular, the MOS transistor 105 has a drain terminal D (formed by the drain contact 155), a source terminal S (formed by the source contact 165) and a gate terminal G (formed by the gate contact 170). The drain terminal D ? connected to the drains of all the base MOS transistors Mi (drain region 115). The source terminal S ? connected to the sources of all the basic MOS transistors Mi (corresponding source regions 135). The G gate terminal ? coupled with the gates of all base MOS transistors Mi (corresponding gate elements 150). In particular, in the base MOS transistor Mu of each non-selected cell, with u=2.4 in the example in question, the gate terminal G ? connected to the gate through the gate resistor Rgu; in the base MOS transistor Ms of each selected cell, instead, the gate terminal G ? connected to the cathode of diode Dps (gate portion 150c, neglecting its resistance), and then to the gate via diode Dps and gate resistor Rgs (the diode Dds being short-circuited).

When the gate/source voltage Vgs ? higher than the threshold voltage Vth but lower than the breakdown voltage Vbk (as typical of the saturation region), Dps diodes are reverse biased and therefore non-conductive. Therefore, only the base MOS transistors Mu receive the gate/source voltage Vgs and therefore are on, while the base MOS transistors Ms have their gates floating and therefore are off.

Conversely, when the gate/source voltage Vgs ? greater than the breakdown voltage Vbk (typical of the linear region), Dps diodes become conductive (inversely) due to their electrical breakdown. Therefore, all the basic MOS transistors Mu,Ms receive the gate/source voltage Vgs and are therefore turned on.

Finally, when the gate/source voltage Vgs ? lower than the threshold voltage Vth (off region), Dps diodes are forward biased and therefore conductive. Therefore, all the basic MOS transistors Mu,Ms receive the gate/source voltage Vgs and are turned off.

The implementation described above ? very simple, but at the same time effective. Furthermore, it allows to obtain the desired result with a limited impact on the structure of the MOS transistor 105.

Referring now to FIG.3A-FIG.3K , the main steps of a manufacturing process of the integrated device according to an embodiment of the present disclosure are shown.

Starting from FIG.3A, how usual is the manufacturing process? realized at the level of a wafer 305 of semiconductor material, on which the same structure ? integrated simultaneously in a large number of its identical areas (only one considered below for simplicity?). The 305 wafer comprises an N++ type substrate, which former? the substrate of the integrated devices and therefore ? indicated with the same reference 115. An N-type epitaxial layer, which will form? the epitaxial layer of the integrated devices and therefore ? indicated with the same reference 120, ? thermally grown on the substrate 115. A mask 310 for the gate trenches ? formed on a free main surface of the epitaxial layer 120, which will form? the front surface of the integrated devices and therefore ? indicated with the same reference 125f; for example, mask 310 ? obtained by growing a (relatively thick) layer of silicon oxide with a thermal oxidation step and then etching it through a suitably defined photoresist layer with photolithographic techniques (then removed). The 305 wafer? then etched through the jig 310 (e.g., with a dry etch step) to form the gate trenches 140.

Moving on to FIG.3B, is the (oxide) mask ? removed. A (relatively thin) layer of silicon oxide 315 ? grown with a thermal oxidation step on the wafer 305, i.e., the front surface 125f and an exposed surface of the gate trenches 140; in particular, the portion of the silicon dioxide layer 315 that lines the gate trenches 140 defines their gate insulating layers 145.

Turning to FIG. 3C, an N+ type doped polysilicon layer 320 ? deposited on the wafer 305, i.e., the silicon oxide layer 315, so as to fill the (coated) gate trenches 140 and to cover the (coated) front surface 125f.

Turning to FIG. 3D, wafer 305 is planarized (e.g., with a chemical mechanical smoothing step, CMP) to remove an excess of the doped polysilicon layer from the silicon oxide layer 315 on the face surface 125f. The operation leaves the gate trenches 140 (coated with the insulating gate layers 145) filled with the (remaining) doped polysilicon, on which corresponding (thin) layers of silicon oxide 325 are formed, so as to obtain the gate 150.

Turning to FIG. 3E , in the solution according to one embodiment of the present disclosure a mask 330 for the separation regions ? formed on the wafer 305, i.e., the silicon oxide layers 315,325; for example, mask 330 ? obtained by depositing a layer of photoresist and subsequently defining it with photolithographic techniques. The 305 wafer? etched across the mask 330 (e.g., with a dry etch step) to form separation trenches 335 corresponding to the separation regions.

Turning to FIG.3F, the mask (of photoresist) ? removed. A P+ type 340 doped polysilicon layer? deposited on the wafer 305, i.e., the silicon oxide layers 315,325, so as to fill the separation trenches 335 and cover the front (coated) surface 125f.

Turning to FIG. 3G, the wafer 305 is planarized (e.g., with a CMP step) to remove excess doped polysilicon from the silicon oxide layers 315,325 on the face surface 125f. The operation leaves the separation trenches 335 filled with the (remaining) doped polysilicon, on which corresponding (thin) layers of silicon oxide 345 are formed, so as to obtain the separation regions 175.

Turning to FIG. 3H , the P-type body region 130 and the N+-type source regions 135 are formed as usual. For example, not shown in the figure, the body region 30 ? formed with an ion implantation step through a photoresist mask (then removed), followed by a thermal diffusion step; similarly, the source regions 135 are formed with an ion implantation step through another photoresist mask (therefore removed), followed by a thermal diffusion step.

Turning to FIG. 3I, a (relatively thick) layer of silicon oxide 350 is grown with a thermal oxidation step on the wafer 305, i.e., the silicon oxide layers 315,325 (which together define the protective layer 160). Source windows 355 for the source contact, gate windows 360 for the gate contact and bridge windows 365 for the bridge contacts are opened in the protective layer 160 by sticking it through a photoresist mask, then removed (not shown in the figure) .

Turning to FIG. 3J , a layer of metal 370 (e.g., tungsten) is deposited on the wafer 305, i.e., the protective layer 160, so as to fill the source windows 355, the gate windows 360 and the bridge windows 365, and to cover the front (coated) surface 125f.

Turning to FIG.3K, the wafer 305 is planarized (e.g., with a CMP step) to remove excess metal from the protective layer 160 on the face surface 125f. The operation leaves corresponding source taps 375 in source windows 355, gate taps 380 in gate windows 360, and bridge taps 385 in bridge windows 365. At this point, not shown in the figure, a layer of metal (e.g. example, copper) ? deposited on the wafer 305, i.e., the protective layer 160, the source taps 375, the gate taps 380 and the bridge taps 385. The metal layer is attached through a photoresist mask, then removed, so as to define a bar and corresponding strips in contact with the source taps 375 (forming the source contact), a bar and corresponding strips in contact with the gate taps 380 ( which form the gate contact), and corresponding pads in contact with the bridge sockets 385 (which form the bridge contacts), with what? obtaining the structure shown in FIG.1.

The implementation described above allows to obtain the desired result with a limited number of additional process steps (and therefore with limited added costs).

Referring now to FIG. 4, ? shown is a principle block diagram of a system 400 incorporating the integrated device in accordance with an embodiment of the present disclosure.

The system 400 (for example, a control unit for automotive applications) comprises several components which are interconnected through a bus structure 405 (with one or more levels). In particular, one or more microprocessors (?P) 410 provide a capacity? system logic 400; a non-volatile memory (ROM) 415 stores basic code for a bootstrap of the system 400 and a volatile memory (RAM) 420 ? used as working memory by the microprocessors 410. The system has a mass memory 425 for storing programs and data (for example, a flash E<2>PROM). Additionally, system 400 includes several unit controllers. peripherals, or input/output (I/O), 430 (such as a Wi-Fi WNIC, Bluetooth transceiver, GPS receiver, accelerometer, gyroscope, and so on). In particular, one or more of the peripherals 430 each comprises an (electromechanical) microstructure 435 (for example, one or more sensors/actuators) and the integrated device 100 for controlling the micro-structure 435.

Changes

Naturally, in order to satisfy contingent and specific needs, a person expert in the field can make numerous logical and/or physical modifications and variations to this disclosure. Pi? specifically, although this disclosure has been described with some level of detail with respect to one or more? its embodiments, it is understood that various omissions, substitutions and changes in form and details so? as other embodiments are possible. In particular, different embodiments of the present disclosure can be put into practice even without the specific details (such as numerical values) set forth in the previous description to provide a more accurate understanding of them. complete understanding; conversely, well-known features may have been omitted or simplified in order not to obscure the description with unnecessary detail. Furthermore, ? It is expressly understood that specific elements and/or method steps described in connection with each embodiment of the present disclosure may be incorporated into any other embodiment as a normal design choice. Furthermore, elements presented in the same group and different embodiments, examples or alternatives should not be interpreted as de facto equivalent to each other (but are separate and autonomous entities). In any case, any numerical value should be read as modified in accordance with applicable tolerances; in particular, unless otherwise indicated, the terms "substantially", "approximately" "approximately" and the like are to be understood as within 10%, preferably 5% and even more? preferably 1%. Furthermore, any range of numeric values should be understood as expressly specifying any possible number along the continuum within the range (including its endpoints). Are ordinal or other qualifiers merely used as labels to distinguish elements of the same name but do not connote per se? themselves no priority, precedence or order. The terms include, comprise, have, contain, entail and the like should be understood to have an open meaning and not exhaustive (i.e., not limited to the recited elements), the terms based on, dependent on, in accordance with, according to, according to and the like should be understood with a non-exclusive relationship (that is, with any additional variables involved), the term one/one should be understood as one or more? elements (unless expressly stated otherwise), and the term means for (or any functional formulation) should be understood as any structure suitable or configured to perform the relevant function.

For example, one embodiment provides an integrated device. However, the integrated device pu? be of any kind (for example, in the form of a raw wafer, as a bare chip, in a container (package) and so on).

In one embodiment, the integrated device comprises at least one MOS transistor. However, the integrated device pu? include any number and type of MOS transistors (e.g., NMOS, PMOS, power type, signal type, mixed type, operating at any current/voltage, etc.).

In one embodiment, the MOS transistor is integrated on a chip of semiconductor material. However, the plate can? be of any type (for example, an epitaxial layer grown on a substrate, a monocrystalline substrate, a SOI, and so on) and of any semiconductor material (for example, silicon, germanium, with any type and concentration of dopants, and so on). Street).

In one embodiment, the MOS transistor comprises a plurality of of cells. However, cells can be in any number and of any type (eg, striped, blocky, interdigitated, in a matrix, and so on).

In one embodiment, each cell comprises a source region of semiconductor material. However, the source region pu? be of any shape, size, depth? and type (for example, N, P, any type and concentration of dopants, etc.).

In one embodiment, each cell comprises a gate element of electrically conductive material. However, the gate element pu? be of any shape, size, and type (for example, buried to any depth, shallow, polysilicon, metal, and so on).

In one embodiment, each cell comprises a gate insulating layer of electrically insulating material which insulates the gate element from the semiconductor material of the chip. However, the insulating layer of the gate pu? be of any thickness, extent, and type (e.g., a single layer extending across all gate elements, separate portions for each gate element or group of them, of silicon dioxide, silicon nitride, TEOS, etc.) Street).

In one embodiment, the MOS transistor comprises a source contact coupled to the source regions. However, the source contact can? be of any type (for example, metal, doped polysilicon, and so on) and pu? be coupled with the source regions in any way (for example, through corresponding buried sockets, superficially, coupled also with the body region, if any, or not, and so on).

In one embodiment, the MOS transistor comprises a gate contact coupled to the gate elements. However, the gate contact pu? be of any type and pu? be coupled to the gate elements in any way (same or different than the source contact).

In one embodiment, one or more Selected cells are differentiated between cells. However, the selected cells can be in any number and arranged in any way (for example, alternating with other non-selected cells, one for every two or more non-selected cells, evenly distributed, more concentrated in some areas, and so on). Street).

In one embodiment, each selected cell comprises a disabling structure interposed between a coupled gate portion of the gate element coupled with the gate contact and a decoupled gate portion of the gate element decoupled from the gate contact. However, the disabling structure can? be of any type (for example, two diodes in anti-series, a single diode, a transistor, an additional disable contact coupled with the gate element, and so on) and pu? be disposed in any position between the coupled gate portion and the decoupled gate portion (for example, in the middle, proximal to the gate contact, proximal to the source region, and so on).

In one embodiment, the disabling structure has a tripping voltage greater than a threshold voltage of the MOS transistor. However, the tripping voltage and the threshold voltage can have any value (in absolute or relative terms); moreover, the intervention voltage pu? be defined in any way (for example, by a reverse breakdown voltage, a threshold voltage, an external bias voltage, and so on).

In one embodiment, the disabling structure is configured to be in a non-conductive condition when the MOS transistor ? turned on in response to a control voltage (applied between the gate contact and the source contact) between the threshold voltage and the trip voltage, or to be in a conductive condition otherwise. However, this result can be achieved in several ways (e.g., with a diode/transistor that is conductive only when forward biased or reverse biased into reverse breakdown in response to control voltage below the threshold voltage or above the trip voltage, respectively, or vice versa, with the control voltage reaching the decoupled portion of the gate only when it exceeds the bias voltage applied to the disable contact, and so on).

Further embodiments provide additional advantageous features, which however can be omitted altogether in a basic implementation.

In particular, in one embodiment in each of the selected cells the disabling structure comprises a diode having a reverse breakdown voltage which defines the tripping voltage. However, the diode pu? be of any type (for example, an avalanche diode, a Zener diode, and so on).

In one embodiment, the diode ? configured to be reverse biased when the MOS transistor ? turned on and to be directly biased when the MOS transistor ? worn out. Anyway, isn't it? excluding the opposite behavior (ie diode forward biased when the MOS transistor is on, conductive or not according to the control voltage, and reverse biased when the MOS transistor is off).

In one embodiment, the chip ? of a first type of conductivity? and has a principal surface area. However, the first type of conductivity? can? be of any type (e.g., N, P, with any type and concentration of dopants, etc.).

In one embodiment, the MOS transistor comprises at least one body region of a second conductivity type. extending from the main surface into the platelet. However, the second type of conductivity? can? be of any type (e.g., P, N, with any type and concentration of dopants, and so on); furthermore, the body regions can be in any number, of any shape, size, depth? and type (for example, one for all cells, one for each cell or group of them, and so on).

In one embodiment, each of the cells comprises the source region of the first conductivity type. which extends from the main surface into the body region. However, the source region pu? extend into the body region in any way (for example, in any position, at any depth with respect to it, and so on).

In one embodiment, each of the cells comprises a gate trench extending from the main surface into the body region and into the semiconductor material of the die. However, the gate trench pu? be of any shape, size and depth? (for example, with a U-section in a UMOS, a V-section in a VMOS and so on).

In one embodiment, each of the cells comprises the gate insulating layer lining the gate trench. However, the insulating layer of the gate pu? lining the gate trench in any way (for example, extending only into the gate trench, extending further onto the front surface, and so on).

In one embodiment, each of the cells comprises the gate element which fills the gate trench lined with the gate insulating layer. Anyway, isn't it? excluded the possibility to have the MOS transistor with a planar structure.

In one embodiment, the chip has a further major surface opposite the major surface; does the MOS transistor comprise a drain region of the first type of conductivity? extending from the further major surface into the chip. Anyway, isn't it? excluded the possibility to have the MOS transistor with a lateral structure.

In one embodiment, in each of the selected cells, the gate element comprises the coupled gate portion of semiconductor material of one conductivity type. of gate (consisting of one between the first type of conductivity? or the second type of conductivity?). However, the coupled portion of the gate can? be of any type (e.g., P, N, with any type and concentration of dopants, and so on).

In one embodiment, in each of the selected cells the gate element comprises the decoupled gate portion of semiconductor material of the conductivity type? of gate. However, the decoupled portion of the gate can? be of any type (e.g., with or without the same type and concentration of dopants with respect to the coupled gate portion).

In one embodiment, in each of the selected cells the disabling structure comprises a separation region of semiconductor material of a conductivity type ? separation (as opposed to gate conductivity type) which separates the coupled gate portion from the decoupled gate portion. However, the region of separation pu? be of any shape, size, depth? and type (for example, N, P, any type and concentration of dopants, etc.).

In one embodiment, the separation region and the coupled gate portion define the diode and the separation region and the decoupled gate portion define a further diode connected in anti-series with the diode. However, the additional diode can? be of any type (same or different with respect to the diode) and the two diodes can be connected in any way in anti-series (e.g. by sharing their anodes or their cathodes).

In one embodiment, in each of the selected cells the disabling structure comprises a bridge element of electrically conductive material connected between the separation region and the decoupled gate portion, the bridge element short-circuiting the further diode. However, the bridge element pu? be of any shape, size, depth? and type (eg, metal, doped polysilicon, any location, etc.).

In one embodiment, in each of the selected cells the coupled gate portion, the decoupled gate portion and the separation region fill corresponding portions of the gate trench extending from the main surface to the gate insulating layer. Anyway, isn't it? excluded the possibility to have a different arrangement (for example, with the coupled/decoupled gate portions extending to a shallower depth and thus a bottom of the gate trench filled by the separation region).

In one embodiment, in each of the selected cells the bridging element comprises a bridging trench extending from the main surface into the separation region and into the decoupled gate portion. However, the bridge trench can? be of any shape, size and depth.

In one embodiment, in each of the selected cells the bridge element comprises a bridge plug of electrically conductive material which fills the bridge trench. Anyway, isn't it? excluded the possibility to contact the separation region and the decoupled gate portion differently (for example, only on the front surface of the chip and so on).

One embodiment provides a system comprising at least one integrated device as above. However, the same structure pu? be integrated with other circuits on the same chip; the chip can? also be coupled with one or more? other chips, can? be mounted in intermediate products or pu? be used in complex equipment. In any case, the resulting system pu? be of any type (for example, for use in automotive applications, smartphones, computers, and so on) and pu? include any number of these integrated devices.

In general, similar considerations apply if the integrated device and system each have a different structure or comprise equivalent components (e.g., of different materials) or have other operating characteristics. In any case, any of its components can? be separated into more elements, or two or more? components can be combined into a single element; moreover, each component pu? be replicated to support the execution of the corresponding operations in parallel. Also, unless otherwise noted, any interactions between different components generally need not be continuous, and can be continuous. be both direct and indirect through one or more? intermediaries.

One embodiment provides a process for manufacturing the above-mentioned integrated device. However, the integrated device pu? be manufactured with any technology, with different number and type of masks, or with other process steps/parameters. Furthermore, the solution described above can? be part of the design of an embedded device. The project can also be created in a hardware description language; also, if the designer does not produce chips or masks, the project can? be transmitted to others by physical means.

In general, similar considerations apply if the same solution ? implemented with an equivalent method (using similar steps with the same functions of multiple steps or their portions, removing some non-essential steps or adding further optional steps); moreover, the steps can be performed in different order, in parallel or overlapping (at least partially).

Claims (11)

1. An integrated device (100) comprising at least one MOS transistor (105) integrated on a chip (110) of semiconductor material, wherein the MOS transistor (105) comprises: a plurality? of cells (135,150) each comprising: a source region (135) of semiconductor material, a gate element (150) of electrically conductive material, and a gate insulating layer (145) of electrically insulating material which insulates the gate element (150) from the semiconductor material of the plate (110), a source contact (165) coupled with the source regions (135), a gate contact (170) coupled with the gate elements (150), in which one or more selected cells of cells (135,150) each includes: a disabling structure (175,180) interposed between a coupled gate portion (150c) of the gate element (150) coupled with the gate contact (170) and a decoupled gate portion (150u) of the gate element (150 ) decoupled from the gate contact (170), the disabling structure (175,180) having a tripping voltage greater than a threshold voltage of the MOS transistor (105) and being configured: to be in a non-conductive condition when the MOS transistor (105) is turned on in response to a control voltage applied between the gate contact (165) and the source contact (170) between the threshold voltage and the trip voltage, or to be in a conductive condition otherwise. The integrated device (100) according to claim 1, wherein in each of the selected cells (135,150) the disabling structure (175,180) comprises a diode (Dp1, Dp3) having a reverse breakdown voltage which defines the tripping voltage , the diode (Dp1,Dp3) being configured to be reverse biased when the MOS transistor (105) ? on and to be forward biased when the MOS transistor (105) ? worn out. 3. The integrated device (100) according to claim 1 or 2, wherein the chip (110) is of a first type of conductivity? and has a main surface (125f), the MOS transistor (105) comprising: at least one body region (130) of a second conductivity type? extending from the main surface (125f) into the die (110), each of the cells (135,150) comprising: the source region (135) of the first type of conductivity? extending from the main surface (125f) into the body region (130), a gate trench (140) extending from the main surface (125f) into the body region (130) and into the semiconductor material of the chip (110), the gate insulating layer (145) coating the gate trench (140) , and the gate (150) filling the gate trench (140) lined with the gate insulating layer (145). 4. The integrated device (100) according to claim 3, wherein the chip (110) has a further main surface (125b) opposite the main surface (125f), the MOS transistor (105) comprising: a drain region (115) of the first type of conductivity? extending from the further major surface (125b) into the chip (110). 5. The integrated device (100) according to claim 3 or 4 when dependent on claim 2, wherein in each of the selected cells (135,150) the gate element (150) comprises: the coupled gate portion (150c) of semiconductor material of a conductivity type? gate, consisting of one of the first type of conductivity? or the second type of conductivity?, the decoupled gate portion (150u) of semiconductor material of the type of conductivity? of gate, and the disabling structure (175,180) includes: a separation region (175) of semiconductor material of a conductivity type? of separation opposite to the type of conductivity? separating the coupled gate portion (150c) from the decoupled gate portion (150u), the separation region (175) and the coupled gate portion (150c) defining the diode (Dp1, Dp3) and the separation region (175) and the decoupled gate portion (150u) defining a further diode (Dd1, Dd3) connected in anti-series with the diode (Dp1, Dp3), and a bridge element (180) of electrically conductive material connected between the separation region (175) and the decoupled gate portion (150u), the bridge element (180) short-circuiting the further diode (Dd1, Dd3). The integrated device (100) according to claim 5, wherein in each of the selected cells (135,150) the coupled gate portion (150c), the decoupled gate portion (150u) and the separation region (175) fill corresponding portions of the gate trench (140) extending from the main surface (125f) to the gate insulating layer (145). The integrated device (100) according to claim 6, wherein in each of the selected cells (135,150) the bridge element (180) comprises: a bridge trench (365) extending from the main surface (125f) into the separation region (170) and the decoupled gate portion (150u), and a bridge plug (385) of electrically conductive material which fills the trench with bridge (365). 8. A system (400) comprising at least one integrated device (100) according to any one of claims 1 to 7. 9. A process for manufacturing an integrated device (100) comprising at least one MOS transistor (105) integrated on a chip (110) of semiconductor material, wherein the process comprises: form a plurality of cells (135,150), for each of the cells (135,150) the process comprising: forming a source region (135) of semiconductor material, forming a gate (150) of electrically conductive material, and forming a gate insulating layer (145) of electrically insulating material which insulates the gate element (150) from the semiconductor material of the chip (110), forming a source contact (165) coupled with the source regions (135), forming a gate contact (170) coupled with the gate elements (150), wherein for each of one or more? selected cells of cells (135,150) the process includes: forming a disabling structure (175,180) interposed between a coupled gate portion (150c) of the gate element (150) coupled with the gate contact (170) and a decoupled gate portion (150u) of the gate element ( 150) decoupled from the gate contact (170), the disabling structure (175,180) having a tripping voltage greater than a threshold voltage of the MOS transistor (105) and being configured to be in a non-conductive condition when the MOS transistor (105) ? turned on in response to a control voltage applied between the gate contact (165) and the source contact (170) between the threshold voltage and the trip voltage, or to be in a conductive condition otherwise. 10. The process according to claim 9, wherein the chip (110) is of a first type of conductivity? and has a principal area (125f), the process comprising: form a body region (130) of a second type of conductivity? extending from the main surface (125f) into the die (110), for each of the cells (135,150) the process including: form the source region (135) of the first type of conductivity? extending from the main surface (125f) into the body region (130), forming a gate trench (140) extending from the main surface (125f) into the body region (130) and into the semiconductor material of the chip (110) , forming the gate insulating layer (145) which lines the gate trench (140), e forming the gate (150) which fills the gate trench (140) lined with the gate insulating layer (145). The process according to claim 10, wherein for the gate element (150) of each of the selected cells (135,150) the process comprises: form the gate element (150) of semiconductor material of a conductivity type? gate, consisting of one of the first type of conductivity? or the second type of conductivity?, forming a separation trench (365) extending from the main surface (125f) into the gate region (150), the separation trench (365) separating the gate element (150) into the mating gate portion (150c), and decoupled gate portion (150u), fill the separation trench (365) with a separation region (175) of a conductivity type? of separation opposite to the type of conductivity? gate, the separation region (175) and the coupled gate portion (150c) defining a diode (Dp1, Dp3), having a reverse breakdown voltage which defines the pick-up voltage, and the separation region (175) and the decoupled gate portion (150u) defining a further diode (Dd1,Dd3) connected in anti-series with the diode (Dp1, Dp3), and forming a bridge element (180) of electrically conductive material connected between the separation region (175) and the decoupled gate portion (150u), the bridge element (180) short-circuiting the further diode (Dd1, Dd3).