CN105914149B - The manufacturing method of groove grid super node power device - Google Patents
The manufacturing method of groove grid super node power device Download PDFInfo
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- CN105914149B CN105914149B CN201610470549.6A CN201610470549A CN105914149B CN 105914149 B CN105914149 B CN 105914149B CN 201610470549 A CN201610470549 A CN 201610470549A CN 105914149 B CN105914149 B CN 105914149B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 76
- 238000005530 etching Methods 0.000 claims abstract description 31
- 239000011241 protective layer Substances 0.000 claims abstract description 31
- 238000000407 epitaxy Methods 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000001259 photo etching Methods 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000012856 packing Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 238000010586 diagram Methods 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a kind of manufacturing methods of groove grid super node power device, comprising steps of forming hard mask layers on N-type epitaxy layer surface；Define first and two groove forming regions of trench gate and superjunction simultaneously using photoetching process；N-type epitaxy layer etch for the first time until reaching depth required by first groove；Protective layer is formed to cover the inner surface of first groove；It carries out second to N-type epitaxy layer to etch, second of etching only performs etching depth required by until reaching second groove to the N-type epitaxy layer of the forming region of second groove；Extension fills P-type silicon in second groove；Remove hard mask layers and protective layer and in the interior formation gate dielectric layer of first groove and filling grid conducting material.The present invention can prevent register partial difference occur between trench gate and p-type column, can improve technology stability and the cut-in voltage for making device and conduction voltage drop more evenly, superjunction unit size can be made smaller.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of groove grid super node (super
Junction) the manufacturing method of power device.
Background technique
Super-junction structure is exactly alternately arranged N-type column and p-type column composed structure.If replaced with super-junction structure vertical double
It spreads in MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) device
N-type drift region, provide conduction path by N-type column in the on-state, p-type column does not provide conduction path when conducting；It is cutting
Only reversed bias voltage is born by PN column under state jointly, is formed superjunction Metal-Oxide Semiconductor field effect transistor
(Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET).Super node MOSFET can be reversed
Under breakdown voltage and traditional VDMOS device unanimous circumstances, by using the epitaxial layer of low-resistivity, and make the conducting of device
Resistance is greatly reduced.
As shown in Figure 1, the structural schematic diagram of existing planar gate super junction power device；Here with N-type groove grid super node power
It is introduced for device, as shown in Figure 1, N-type groove grid super node power device includes:
Semiconductor substrate such as silicon substrate 1 is formed with N-type epitaxy layer such as N-type silicon epitaxy layer 2 on the surface of semiconductor substrate 1,
Super-junction structure is by the p-type column 3 being formed in N-type epitaxy layer 2 and the N-type column 4 being made of the N-type epitaxy layer 2 between each p-type column 3
It is alternately arranged to be formed.
The area PXing Ti 5a is formed in the top of each p-type column 3.
Polysilicon gate 6a is formed in the top of the selection area of the area PXing Ti 5a and is mutually separated with gate dielectric layer such as grid therebetween
Oxide layer is used to form channel by the surface for the area the PXing Ti 5a that polysilicon gate 6a is covered, so the area PXing Ti 5a is as channel region.
The N-type column surface outside the area PXing Ti 5a is also extended by the gate structure that polysilicon gate 6a and gate dielectric layer form.
By N+ district's groups at source region 7 be formed in the surface of the area PXing Ti 5a, the side of source region 7 and polysilicon gate 5a autoregistration.
Interlayer film 8 is formed in the front of semiconductor substrate 1 and the polysilicon gate 6a by device, source region 7 and the area PXing Ti 5a etc.
Covering.Contact hole 9 passes through corresponding source region 7 or polysilicon gate the 6a contact of interlayer film 8 and bottom.In the corresponding contact of source region 7
The bottom in hole 9 is formed with the contact implanted layer 10 of P+ doping, contacts bottom and the area the PXing Ti 5a contact of implanted layer 10.7 He of source region
The area PXing Ti 5a is connected to the source electrode being made of front metal layer 11 by the contact hole 9 at top；Polysilicon gate 6a passes through top
Contact hole 9 is connected to the grid being made of front metal layer 11.
When groove grid super node power device is MOSFET element, drain region is formed by the highly doped semiconductor substrate 1 of N-type, and
The drain electrode being made of metal layer on back is formed at the back side of semiconductor substrate 1.
As shown in Figure 1 it is found that a p-type column 3 and adjacent p-type column 4 form a superjunction unit, in a superjunction unit
A super junction power device unit i.e. primitive unit cell is formed, polysilicon gate 6a is formed in the top of N-type column 4 and is two adjacent superjunction
Units shared；Since polysilicon gate 6a is planar structure, biggish area can be occupied, this can also make the size meeting of superjunction unit
It is larger.
It is well known that replacing planar gate using trench gate in super junction power device, it is i.e. super that P/N column dimension can be effectively reduced
The size of statement of account member, the size refer to transverse width, and P/N column dimension, which reduces, to be meaned to realize charge with denseer epitaxial layer
Balance, therefore the available reduction of conduction voltage drop.As shown in Fig. 2, being the structural schematic diagram of existing groove grid super node power device；Figure
In place of the difference of structure shown in 2 and Fig. 1 are as follows:
The area PXing Ti 5 can horizontally cover the surface of entire super-junction structure, and polysilicon gate 6 is formed in groove, polysilicon
Grid 6 can cover the area PXing Ti 5 across the area PXing Ti 5 and from side, be used for by the surface in the area PXing Ti 5 that 6 side of polysilicon gate covers
Form channel.The groove of polysilicon gate 6 requires the top for being located at N-type column 4.
Although trench gate structure shown in Fig. 2 can reduce the size of device, no matter multilayer is used in actual process
Extension or the mode of extension filling form p-type column 3, because p-type column 3 and trench gate, that is, polysilicon gate 6 are that Twi-lithography is formed, work
Register partial difference in skill, which will lead to, there is the case where accumulation area that p-type column 3 influences trench gate；The accumulation area of trench gate is located at P
, there is register partial difference between p-type column 3 and trench gate in the bottom in the area Xing Ti 5 and the N-type epitaxy layer 2 covered by 6 side of polysilicon gate
When, the lateral dimension of accumulation area will receive influence, so that the cut-in voltage of device and conduction voltage drop can be made to be deteriorated.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of manufacturing methods of groove grid super node power device, can prevent
There is register partial difference between trench gate and p-type column, technology stability can be improved and makes the cut-in voltage and conduction voltage drop of device
More evenly, the groove grid super node power device of smaller primitive unit cell size can be produced.
In order to solve the above technical problems, the manufacturing method of groove grid super node power device provided by the invention includes following step
It is rapid:
Step 1: providing semi-conductive substrate, formed in the semiconductor substrate surface by N-type epitaxy layer；In the N-type
Epi-layer surface forms hard mask layers.
Step 2: defined simultaneously using photoetching process the first groove of trench gate forming region and super-junction structure the
The forming region of two grooves；The hard mask layers are performed etching the forming region of the first groove and second ditch
The forming region of slot is opened.
Step 3: carrying out first time etching to the N-type epitaxy layer, the first time etching is with the hard mask layers
The depth of mask, the first time etching reaches depth required by the first groove.
The bottom surface of the first groove and side are covered Step 4: forming protective layer.
Etched Step 5: carrying out second to the N-type epitaxy layer, second of etching with the hard mask layers and
The protective layer is mask, and second of etching only carries out the N-type epitaxy layer of the forming region of the second groove
It etches, the depth after second of etching will reach depth required by the second groove.
Step 6: carry out selective epitaxial growth process fills P-type silicon in the second groove, outside the second groove
By the hard mask layers and protective layer protection without epitaxial growth.
P-type column is formed by the P-type silicon being filled in the second groove, by the N-type extension between each p-type column
The N-type column of layer composition, is alternately arranged by the p-type column and the N-type column and is formed super-junction structure；The first groove is located at each institute
State N-type column top.
Step 7: the hard mask layers and the protective layer are removed, bottom surface and side in the first groove
Form gate dielectric layer；Later, grid conducting material is filled in the first groove, groove is formed by the grid conducting material
Grid.
A further improvement is that the protective layer in step 4 is made of silicon nitride or is superimposed silicon nitride group by silica
At；The protective layer partly or completely full packing institute under conditions of guaranteeing to cover the bottom surface of the first groove and side
State first groove.
A further improvement is that step 4 forms the protective layer of the bottom surface and side that cover the first groove
The step of include:
Step 41 grows the protective layer in the entire semiconductor substrate front.
Step 42 is opened the second groove forming region by photoetching process formation photoetching offset plate figure.
Step 43 is removed the protective layer in the second groove region using etching technics；The light is removed later
Photoresist figure.
A further improvement is that being further comprised the steps of: after step 7
Step 8: forming the area PXing Ti at the top of the super-junction structure, the trench gate bottom passes through the area PXing Ti,
Channel is used to form by the p-type body surface that the trench gate side covers.
Step 9: the surface in the area PXing Ti forms source region.
Step 10: forming interlayer film, contact hole and front metal layer.
A further improvement is that the gate dielectric layer in step 7 is gate oxide.
A further improvement is that grid conducting material described in step 7 is polysilicon.
A further improvement is that a superjunction unit is formed by a p-type column and the adjacent one N-type column,
Define the width and the trench gate and the adjacent p-type column of the superjunction unit simultaneously by the photoetching process of step 2
Between interval enable the width of the superjunction unit to eliminate the register partial difference between the trench gate and the p-type column
It is enough to reduce.
The method of the present invention uses the first groove of trench gate and the second groove of super-junction structure same with a photoetching process
Shi Dingyi is respectively formed the groove of required depth, since first groove and second groove are to adopt using twice etching technique later
It to be formed with being defined with a photoetching process, eliminate register partial difference problem when Twi-lithography technique defines namely energy of the present invention
Prevent register partial difference occur between trench gate and p-type column, so as to improve technology stability and make device cut-in voltage and
Conduction voltage drop more evenly, due to not having register partial difference, enables superjunction unit to make smaller, makes to make small primitive unit cell size
Groove grid super node power device is possibly realized.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the structural schematic diagram of existing planar gate super junction power device；
Fig. 2 is the structural schematic diagram of existing groove grid super node power device；
Fig. 3 is the flow chart of the manufacturing method of groove grid super node power device of the embodiment of the present invention；
Fig. 4 A- Fig. 4 N is the device architecture in each step of manufacturing method of groove grid super node power device of the embodiment of the present invention
Schematic diagram.
Specific embodiment
As shown in figure 3, being the flow chart of the manufacturing method of groove grid super node power device of the embodiment of the present invention；Extremely such as Fig. 4 A
It is the device architecture schematic diagram in each step of manufacturing method of groove grid super node power device of the embodiment of the present invention shown in Fig. 4 N,
The manufacturing method of groove grid super node power device of the embodiment of the present invention includes the following steps:
Step 1: as shown in Figure 4 A, providing semi-conductive substrate 1, formed outside by N-type on 1 surface of semiconductor substrate
Prolong layer 2.In the embodiment of the present invention, semiconductor substrate 1 is silicon substrate, and N-type epitaxy layer 2 is N-type silicon epitaxy layer；In other embodiments
In, semiconductor substrate 1 can also select other semiconductor materials.
As shown in Figure 4 B, hard mask layers 101 are formed on 2 surface of N-type epitaxy layer.
Step 2: as shown in Figure 4 B, forming photoetching offset plate figure 102 using photoetching process and defining the of trench gate 6 simultaneously
The forming region of the second groove 104 of the forming region and super-junction structure of one groove 103；The hard mask layers 101 are carried out
Etching opens the forming region of the forming region of the first groove 103 and the second groove 104.
Step 3: as shown in Figure 4 C, carrying out first time etching to the N-type epitaxy layer 2, the first time etching is with described
Hard mask layers 101 are mask, and the depth of the first time etching reaches depth required by the first groove 103.
The bottom surface of the first groove 103 and side are covered Step 4: forming protective layer.
In the embodiment of the present invention, the protective layer is superimposed silicon nitride 106 by silica 105 and forms, and wherein silica 105 is used
In reduction silicon nitride to the stress of silicon.In other embodiments, silica 105 can be also omitted, institute is individually formed by silicon nitride 106
State protective layer.The protective layer under conditions of guaranteeing to cover the bottom surface of the first groove 103 and side part or
It is filled up completely the first groove 103.Silicon nitride 106 needs enough thickness, and can be corresponding in subsequent second groove
Hard template is used as in second of etching.Bottom surface and the side for covering the first groove 103 are formed in the embodiment of the present invention
The protective layer the step of include:
Step 41, as shown in Figure 4 D, the entire 1 front growing silicon oxide 105 of semiconductor substrate and silicon nitride 106 simultaneously
Superposition forms the protective layer；At this point, the protective layer can be located at the surface of the entire semiconductor substrate.
Step 42, as shown in Figure 4 E, forms photoetching offset plate figure 107 by photoetching process and forms the second groove 104
It opens in region；The corresponding width of photoetching offset plate figure 107 is less than the width of hard mask layers 101, this is photoetching offset plate figure 107
The forming region of the second groove 104 can be opened together with hard mask layers 101.
Step 43 is removed the protective layer in 104 region of second groove using etching technics.First, such as Fig. 4 F
It is shown, the 104 region silicon nitride 106 of second groove is removed using wet-etching technology；Later, it as shown in Figure 4 G, removes
The photoetching offset plate figure 107；Followed by, as shown in Figure 4 G, using wet-etching technology by 104 zone oxidation of second groove
Silicon 105.
Step 5: as shown at figure 4h, carrying out second to the N-type epitaxy layer 2 and etching, second of etching is with described
Hard mask layers 101 and the protective layer are mask, and second of etching is only to the forming region of the second groove 104
The N-type epitaxy layer 2 performs etching, and the depth after second of etching will reach depth required by the second groove 104
Degree.
Step 6: as shown in fig. 41, carrying out selective epitaxial growth process and filling P-type silicon in the second groove 104
3, the second groove 104 is outer by the hard mask layers 101 and protective layer protection and without epitaxial growth.
P-type column 3 is formed by the P-type silicon 3 being filled in the second groove 104, forms the p-type in the embodiment of the present invention
Column 3 further include it is following step by step:
As shown in fig. 41, selective epitaxial growth is carried out first, and the surface of the P-type silicon 3 at this moment formed is simultaneously uneven.Selection
Property epitaxial process in because the bottom surface of first groove 103 and side all protected seams cover, therefore extension can not be the
It is grown in one groove 103, is only capable of being filled in second groove 104.
As shown in fig. 4j, extension, that is, P-type silicon 3 is planarized, which generally uses chemical mechanical grinding
Technique (CMP) is completed.
As shown in Figure 4 K, the P-type silicon 3 carve, make surface and the N-type epitaxy layer 2 of the P-type silicon 3
Surface is equal.
The N-type column 4 being made of the N-type epitaxy layer 2 between each p-type column 3, by the p-type column 3 and the N-type
Column 4 is alternately arranged composition super-junction structure；The first groove 103 is located at each 4 top of the N-type column.
One superjunction unit is formed by a p-type column 3 and the adjacent one N-type column 4, passes through the light of step 2
Carving technology defines the interval between the width of the superjunction unit and the trench gate 6 and the adjacent p-type column 3 simultaneously,
To eliminate the register partial difference between the trench gate 6 and the p-type column 3, the width of the superjunction unit is enable to reduce.
Step 7: as illustrated in fig. 4l, removing the hard mask layers 101 and the protective layer；As shown in fig. 4m, described
The bottom surface of first groove 103 and side form gate dielectric layer such as gate oxide；Later, it is filled out in the first groove 103
The grid conducting material i.e. polysilicon gate 6 being made of polysilicon is filled, trench gate 6 is formed by the grid conducting material.In other realities
It applies in example, the grid conducting material also can be other metal materials.
It is further comprised the steps of: after step 7
Step 8: forming the area PXing Ti 5 at the top of the super-junction structure, 6 bottom of trench gate is worn as shown in Fig. 4 N
The area PXing Ti 5 is crossed, channel is used to form by 5 surface of the area PXing Ti that 6 side of trench gate covers.
Step 9: forming source region 7 on the surface in the area PXing Ti 5 as shown in Fig. 4 N.
Step 10: as shown in Fig. 2, forming interlayer film 8, contact hole 9 and front metal layer 11.
Interlayer film 8 is formed in the front of semiconductor substrate 1 and by the polysilicon gate of device 6, and source region 7 and the area PXing Ti 5 etc. are covered
Lid.Contact hole 9 passes through corresponding source region 7 or polysilicon gate 6 contact of interlayer film 8 and bottom.In the corresponding contact hole 9 of source region 7
Bottom be formed with P+ doping contact implanted layer 10, contact implanted layer 10 bottom and the area PXing Ti 5 contact.Source region 7 and p-type
Body area 5 is connected to the source electrode being made of front metal layer 11 by the contact hole 9 at top；The contact that polysilicon gate 6 passes through top
Hole 9 is connected to the grid being made of front metal layer 11.
Groove grid super node power device be MOSFET element when, further include the semiconductor substrate 1 is carried out it is thinned and by
The highly doped semiconductor substrate 1 of N-type after being thinned forms drain region, and drain region carries out after capable of being also thinned by the semiconductor substrate 1
The back side is injected to be formed.Later, the drain electrode being made of metal layer on back is formed at the back side of semiconductor substrate 1.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (7)
1. a kind of manufacturing method of groove grid super node power device, which comprises the steps of:
Step 1: providing semi-conductive substrate, N-type epitaxy layer is formed in the semiconductor substrate surface；In the N-type extension
Layer surface forms hard mask layers；
Step 2: defining the forming region of the first groove of trench gate and the second ditch of super-junction structure simultaneously using photoetching process
The forming region of slot；The hard mask layers are performed etching the forming region of the first groove and the second groove
Forming region is opened；
Step 3: carrying out first time etching to the N-type epitaxy layer, the first time etching is to cover with the hard mask layers
The depth of mould, the first time etching reaches depth required by the first groove；
The bottom surface of the first groove and side are covered Step 4: forming protective layer；
It is etched Step 5: carrying out second to the N-type epitaxy layer, second of etching is with hard mask layers and described
Protective layer is mask, and second of etching only performs etching the N-type epitaxy layer of the forming region of the second groove,
Depth after second of etching will reach depth required by the second groove；
Step 6: carry out selective epitaxial growth process fills P-type silicon in the second groove, the second groove is outer by institute
State hard mask layers and the protective layer protection and without epitaxial growth；
P-type column is formed by the P-type silicon being filled in the second groove, by the N-type epitaxy layer group between each p-type column
At N-type column, be alternately arranged by the p-type column and the N-type column and formed super-junction structure；The first groove is located at each N
Type column top；
Step 7: removing the hard mask layers and the protective layer, formed in the bottom surface of the first groove and side
Gate dielectric layer；Later, grid conducting material is filled in the first groove, trench gate is formed by the grid conducting material.
2. the manufacturing method of groove grid super node power device as described in claim 1, it is characterised in that: described in step 4
Protective layer is made of silicon nitride or is made of silica superposition silicon nitride；The protective layer is guaranteeing the bottom of the first groove
Partly or completely first groove described in full packing under conditions of portion surface and side covering.
3. the manufacturing method of groove grid super node power device as claimed in claim 1 or 2, it is characterised in that: step 4 is formed
Cover the first groove bottom surface and side the protective layer the step of include:
Step 41 grows the protective layer in the entire semiconductor substrate front；
Step 42 is opened the second groove forming region by photoetching process formation photoetching offset plate figure；
Step 43 is removed the protective layer in the second groove region using etching technics；The photoresist is removed later
Figure.
4. the manufacturing method of groove grid super node power device as described in claim 1, which is characterized in that also wrapped after step 7
Include step:
Step 8: forming the area PXing Ti at the top of the super-junction structure, the trench gate bottom passes through the area PXing Ti, by institute
The p-type body surface for stating the covering of trench gate side is used to form channel；
Step 9: the surface in the area PXing Ti forms source region；
Step 10: forming interlayer film, contact hole and front metal layer.
5. the manufacturing method of groove grid super node power device as described in claim 1, it is characterised in that: described in step 7
Gate dielectric layer is gate oxide.
6. the manufacturing method of groove grid super node power device as described in claim 1, it is characterised in that: grid described in step 7
Pole conductive material is polysilicon.
7. the manufacturing method of groove grid super node power device as described in claim 1, it is characterised in that: by a p-type
Column and the adjacent one N-type column form a superjunction unit, are defined simultaneously by the photoetching process of step 2 described super
Interval between the width of statement of account member and the trench gate and the adjacent p-type column, to eliminate the trench gate and the P
Register partial difference between type column enables the width of the superjunction unit to reduce.
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| KR101201382B1 (en) * | 2010-12-02 | 2012-11-14 | (주) 트리노테크놀로지 | Power semiconductor device having decreased cell pitch |
| US8564058B1 (en) * | 2012-08-07 | 2013-10-22 | Force Mos Technology Co., Ltd. | Super-junction trench MOSFET with multiple trenched gates in unit cell |
| WO2013187017A1 (en) * | 2012-06-13 | 2013-12-19 | 株式会社デンソー | Silicon carbide semiconductor device and method for producing same |
| CN103794649A (en) * | 2012-10-31 | 2014-05-14 | 英飞凌科技奥地利有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| JP2014110382A (en) * | 2012-12-04 | 2014-06-12 | Denso Corp | Semiconductor device |
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| KR101201382B1 (en) * | 2010-12-02 | 2012-11-14 | (주) 트리노테크놀로지 | Power semiconductor device having decreased cell pitch |
| WO2013187017A1 (en) * | 2012-06-13 | 2013-12-19 | 株式会社デンソー | Silicon carbide semiconductor device and method for producing same |
| US8564058B1 (en) * | 2012-08-07 | 2013-10-22 | Force Mos Technology Co., Ltd. | Super-junction trench MOSFET with multiple trenched gates in unit cell |
| CN103794649A (en) * | 2012-10-31 | 2014-05-14 | 英飞凌科技奥地利有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| JP2014110382A (en) * | 2012-12-04 | 2014-06-12 | Denso Corp | Semiconductor device |
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