IT201900025411A1 - Dispositivo di memoria includente un decodificatore di colonna che riduce la caduta di tensione lungo le linee di bit locali selezionate - Google Patents

Dispositivo di memoria includente un decodificatore di colonna che riduce la caduta di tensione lungo le linee di bit locali selezionate

Info

Publication number
IT201900025411A1
IT201900025411A1 IT102019000025411A IT201900025411A IT201900025411A1 IT 201900025411 A1 IT201900025411 A1 IT 201900025411A1 IT 102019000025411 A IT102019000025411 A IT 102019000025411A IT 201900025411 A IT201900025411 A IT 201900025411A IT 201900025411 A1 IT201900025411 A1 IT 201900025411A1
Authority
IT
Italy
Prior art keywords
reduces
memory device
device including
bit lines
voltage drop
Prior art date
Application number
IT102019000025411A
Other languages
English (en)
Inventor
Maurizio Francesco Perroni
Fabio Enrico Carlo Disegni
Massimo Caruso
Cesare Torti
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT102019000025411A priority Critical patent/IT201900025411A1/it
Priority to US17/129,016 priority patent/US11380393B2/en
Priority to CN202011539051.3A priority patent/CN113096701A/zh
Publication of IT201900025411A1 publication Critical patent/IT201900025411A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
IT102019000025411A 2019-12-23 2019-12-23 Dispositivo di memoria includente un decodificatore di colonna che riduce la caduta di tensione lungo le linee di bit locali selezionate IT201900025411A1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT102019000025411A IT201900025411A1 (it) 2019-12-23 2019-12-23 Dispositivo di memoria includente un decodificatore di colonna che riduce la caduta di tensione lungo le linee di bit locali selezionate
US17/129,016 US11380393B2 (en) 2019-12-23 2020-12-21 Memory device and method for coupling a main bitline to two points of a local bitline
CN202011539051.3A CN113096701A (zh) 2019-12-23 2020-12-23 存储器设备及其操作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102019000025411A IT201900025411A1 (it) 2019-12-23 2019-12-23 Dispositivo di memoria includente un decodificatore di colonna che riduce la caduta di tensione lungo le linee di bit locali selezionate

Publications (1)

Publication Number Publication Date
IT201900025411A1 true IT201900025411A1 (it) 2021-06-23

Family

ID=70009321

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102019000025411A IT201900025411A1 (it) 2019-12-23 2019-12-23 Dispositivo di memoria includente un decodificatore di colonna che riduce la caduta di tensione lungo le linee di bit locali selezionate

Country Status (3)

Country Link
US (1) US11380393B2 (it)
CN (1) CN113096701A (it)
IT (1) IT201900025411A1 (it)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1708202A2 (en) * 2005-03-24 2006-10-04 Samsung Electronics Co., Ltd. Pram device
US20070133268A1 (en) * 2005-12-09 2007-06-14 Byung-Gil Choi Phase change memory device and memory cell array thereof
US20090040819A1 (en) * 2007-08-10 2009-02-12 Samsung Electronics Co., Ltd. Nonvolatile memory device using resistive elements and an associated driving method
US20090285015A1 (en) * 2008-05-19 2009-11-19 Samsung Electronics Co., Ltd. Phase-change memory device including biasing circuit
US20160141334A1 (en) * 2014-11-14 2016-05-19 Sandisk 3D Llc Monolithic three dimensional memory arrays with staggered vertical bit line select transistors and methods therfor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1047077A1 (en) * 1999-04-21 2000-10-25 STMicroelectronics S.r.l. Nonvolatile memory device with double hierarchical decoding
US7126853B2 (en) * 2003-08-14 2006-10-24 Mosel Vitelic, Inc. Electronic memory having impedance-matched sensing
ITUB20151112A1 (it) * 2015-05-27 2016-11-27 St Microelectronics Srl Dispositivo di memoria non-volatile e corrispondente metodo di funzionamento con riduzione degli stress
IT201700019514A1 (it) * 2017-02-21 2018-08-21 St Microelectronics Srl Dispositivo di memoria non volatile a cambiamento di fase dotato di una funzione di accesso alla memoria
IT201800000632A1 (it) * 2018-01-09 2019-07-09 St Microelectronics Srl Dispositivo per commutare tra diverse modalita' di lettura di una memoria non volatile e metodo di lettura di una memoria non volatile
IT201800003796A1 (it) * 2018-03-20 2019-09-20 St Microelectronics Srl Dispositivo di memoria non volatile con modalita' di lettura commutabile e relativo metodo di lettura

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1708202A2 (en) * 2005-03-24 2006-10-04 Samsung Electronics Co., Ltd. Pram device
US20070133268A1 (en) * 2005-12-09 2007-06-14 Byung-Gil Choi Phase change memory device and memory cell array thereof
US20090040819A1 (en) * 2007-08-10 2009-02-12 Samsung Electronics Co., Ltd. Nonvolatile memory device using resistive elements and an associated driving method
US20090285015A1 (en) * 2008-05-19 2009-11-19 Samsung Electronics Co., Ltd. Phase-change memory device including biasing circuit
US20160141334A1 (en) * 2014-11-14 2016-05-19 Sandisk 3D Llc Monolithic three dimensional memory arrays with staggered vertical bit line select transistors and methods therfor

Also Published As

Publication number Publication date
US20210193221A1 (en) 2021-06-24
CN113096701A (zh) 2021-07-09
US11380393B2 (en) 2022-07-05

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