IT201700062830A1 - Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento - Google Patents

Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento

Info

Publication number
IT201700062830A1
IT201700062830A1 IT102017000062830A IT201700062830A IT201700062830A1 IT 201700062830 A1 IT201700062830 A1 IT 201700062830A1 IT 102017000062830 A IT102017000062830 A IT 102017000062830A IT 201700062830 A IT201700062830 A IT 201700062830A IT 201700062830 A1 IT201700062830 A1 IT 201700062830A1
Authority
IT
Italy
Prior art keywords
procedure
integrated circuit
processing system
related integrated
circuit
Prior art date
Application number
IT102017000062830A
Other languages
English (en)
Inventor
Roberto Colombo
Original Assignee
Stmicroelectronics Application Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stmicroelectronics Application Gmbh filed Critical Stmicroelectronics Application Gmbh
Priority to IT102017000062830A priority Critical patent/IT201700062830A1/it
Priority to EP18173959.0A priority patent/EP3413195B1/en
Priority to US16/002,534 priority patent/US10922015B2/en
Publication of IT201700062830A1 publication Critical patent/IT201700062830A1/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Software Systems (AREA)
  • Storage Device Security (AREA)
IT102017000062830A 2017-06-08 2017-06-08 Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento IT201700062830A1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT102017000062830A IT201700062830A1 (it) 2017-06-08 2017-06-08 Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento
EP18173959.0A EP3413195B1 (en) 2017-06-08 2018-05-24 Processing system, related integrated circuit, device and method
US16/002,534 US10922015B2 (en) 2017-06-08 2018-06-07 Processing system, related integrated circuit, device and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102017000062830A IT201700062830A1 (it) 2017-06-08 2017-06-08 Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento

Publications (1)

Publication Number Publication Date
IT201700062830A1 true IT201700062830A1 (it) 2018-12-08

Family

ID=60020526

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102017000062830A IT201700062830A1 (it) 2017-06-08 2017-06-08 Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento

Country Status (3)

Country Link
US (1) US10922015B2 (it)
EP (1) EP3413195B1 (it)
IT (1) IT201700062830A1 (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT201700082176A1 (it) 2017-07-19 2019-01-19 Stmicroelectronics Application Gmbh Sistema di elaborazione, relativo circuito integrato e procedimento
US12118088B2 (en) * 2020-04-22 2024-10-15 Arm Limited Moderator system for a security analytics framework
IT202100030332A1 (it) 2021-11-30 2023-05-30 Stmicroelectronics Application Gmbh Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5379382A (en) * 1991-04-22 1995-01-03 Pilkington Micro-Electronics Limited Uni and bi-directional signal transfer modes in peripheral controller and method of operating same
US6643777B1 (en) * 1999-05-14 2003-11-04 Acquis Technology, Inc. Data security method and device for computer modules
US20040210720A1 (en) * 2003-04-17 2004-10-21 Wong Yuqian C. Patch momory system for a ROM-based processor
US20120029664A1 (en) * 2005-09-29 2012-02-02 Rockwell Automation Technologies, Inc. Editing lifecycle and deployment of objects in an industrial automation environment
US20130185482A1 (en) * 2012-01-18 2013-07-18 Samsung Electronics Co., Ltd. Memory system using a storage having firmware with a plurality of features
US20150331043A1 (en) * 2014-05-15 2015-11-19 Manoj R. Sastry System-on-chip secure debug
US20150370580A1 (en) * 2013-02-12 2015-12-24 Freescale Semiconductor, Inc. Configuration controller for and a method of controlling a configuration of a circuitry

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100397331C (zh) * 2001-09-07 2008-06-25 Ip菲力股份有限公司 数据处理系统以及控制方法
US20030233534A1 (en) * 2002-06-12 2003-12-18 Adrian Bernhard Enhanced computer start-up methods
DE602005021344D1 (de) * 2005-07-28 2010-07-01 St Microelectronics Srl Konfigurierung eines Multibit-Flashspeichers

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5379382A (en) * 1991-04-22 1995-01-03 Pilkington Micro-Electronics Limited Uni and bi-directional signal transfer modes in peripheral controller and method of operating same
US6643777B1 (en) * 1999-05-14 2003-11-04 Acquis Technology, Inc. Data security method and device for computer modules
US20040210720A1 (en) * 2003-04-17 2004-10-21 Wong Yuqian C. Patch momory system for a ROM-based processor
US20120029664A1 (en) * 2005-09-29 2012-02-02 Rockwell Automation Technologies, Inc. Editing lifecycle and deployment of objects in an industrial automation environment
US20130185482A1 (en) * 2012-01-18 2013-07-18 Samsung Electronics Co., Ltd. Memory system using a storage having firmware with a plurality of features
US20150370580A1 (en) * 2013-02-12 2015-12-24 Freescale Semiconductor, Inc. Configuration controller for and a method of controlling a configuration of a circuitry
US20150331043A1 (en) * 2014-05-15 2015-11-19 Manoj R. Sastry System-on-chip secure debug

Also Published As

Publication number Publication date
EP3413195B1 (en) 2020-04-22
EP3413195A1 (en) 2018-12-12
US10922015B2 (en) 2021-02-16
US20180357012A1 (en) 2018-12-13

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